DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 5/11/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 and 10-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karda et al. (US 2021/0013305 A1) in view of Pillarisetty et al. (US 10,991,802 B2).
Regarding claim 1, Karda discloses an apparatus (Fig. 1) comprising:
a recess formed in a semiconductor material (124);
a dielectric structure (137) formed in the recess; and
a control gate (combination of 106 and 136) for a transistor of a memory cell, the control gate including a first conductive portion (106) and second conductive portion (136) formed in the recess, the first and second conductive portions including different conductive materials (¶ 0021).
Karda differs from the claimed invention by the substitution of a multilayer dielectric structure with a single layer dielectric structure. However, multilayer dielectric structures and the corresponding function was known in the art (“multilayer gate dielectric (e.g., with multiple materials used . . . for example silicon oxide, aluminum oxide, or . . . hafnium oxide”, Col. 4 of Pillarisetty). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known structure of a multilayer structure with a layer of silicon dioxide over a layer of hafnium oxide as taught by Pillarisetty for the dielectric structure of Karda and the results of the substitution would have been predictable as a gate dielectric layer. (see MPEP § 2143(I)(B)).
In the resulting configuration, the first conductive portion is separated from the semiconductor material by a first portion of the dielectric structure (portion of 107 below the top surface of 106 in Fig. 1 of Karda), the first dielectric portion including a first dielectric material (the silicon dioxide of Pillarisetty) and a second dielectric material (the hafnium oxide of Pillarisetty), the first dielectric material being between the semiconductor material and the second dielectric material, and the second dielectric material being between the first dielectric material and the first conductive portion; and
the second conductive portion is formed over the first conductive portion and is separated from the semiconductor material by a second portion of the dielectric structure (corresponding to the remaining portion of the dielectric structure which is also formed of a multilayer of silicon dioxide and hafnium oxide in the device of the combination) between the semiconductor material and second conductive portion.
Regarding claim 2, in the device of the combination, the second dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide (as hafnium oxide has a higher dielectric constant than silicon dioxide).
Regarding claim 3, in the device of the combination, the first dielectric material includes a first thickness; the second dielectric material includes a second thickness; and the second portion of the dielectric structure includes a third thickness, wherein each of the first and second thicknesses is less than the third thickness (as the first and second portions of the dielectric structure are equally thick, the third thickness is equal to the sum of the first and second thicknesses).
Regarding claim 4, in the device of the combination, a sum of the first thickness and the second thickness is not greater than the third thickness (as the first and second portions of the dielectric structure are equally thick, the third thickness is equal to the sum of the first and second thicknesses).
Regarding claim 5, in the device of the combination, the second dielectric material has a dielectric constant greater than a dielectric constant of the first dielectric material (as hafnium oxide has a higher dielectric constant than silicon dioxide).
Regarding claim 6, in the device of the combination, wherein the second dielectric material has a dielectric constant greater than a dielectric constant of a material of the second portion of the dielectric structure (as the second portion also includes silicon dioxide and hafnium oxide has a higher dielectric constant than silicon dioxide).
Regarding claim 7, in the device of the combination, the second portion of the dielectric structure includes a same dielectric material as the first dielectric material (as both portions comprise the same materials).
Regarding claim 8, in the device of the combination, the second conductive portion includes polysilicon (¶ 0021 of Karda.
Regarding claim 10, in the device of the combination, the second dielectric material includes hafnium oxide.
Regarding claim 11, in the device of the combination, the control gate is part of an access line for the memory cell (¶ 0020).
Regarding claim 12, Karda discloses an apparatus (Fig. 1) comprising:
a conductive structure (combination of 106 and 136) formed in a material (124) of a memory device and separated from the material of the memory device by a dielectric structure (137), the conductive structure including a first conductive portion (106) and second conductive portion (136) formed over the first conductive portion.
Karda differs from the claimed invention by the substitution of a multilayer dielectric structure with a single layer dielectric structure. However, multilayer dielectric structures and the corresponding function was known in the art (“multilayer gate dielectric (e.g., with multiple materials used . . . for example silicon oxide, aluminum oxide, or . . . hafnium oxide”, Col. 4 of Pillarisetty). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known structure of a multilayer structure with a layer of silicon dioxide over a layer of hafnium oxide as taught by Pillarisetty for the dielectric structure of Karda and the results of the substitution would have been predictable as a gate dielectric layer. (see MPEP § 2143(I)(B)).
In the resulting configuration, the dielectric structure includes a first dielectric portion (portion of 107 extending from the bottom of 106 and ending halfway up 106 in Fig. 1 of Karda) between the material of the memory device and the first conductive portion, and the first dielectric portion includes a first dielectric material (the silicon dioxide of Pillarisetty) having a first thickness, and a second dielectric material (the hafnium oxide of Pillarisetty) having a second thickness and a dielectric constant greater than a dielectric constant of silicon dioxide; and
the dielectric structure includes a second dielectric portion (remaining portion of the dielectric structure) between the material of the memory device and the second conductive portion, and the second dielectric portion includes a third thickness greater than each of the first and second thicknesses (as the first and second portions of the dielectric structure are equally thick, the third thickness is equal to the sum of the first and second thicknesses).
Regarding claim 13, in the device of the combination, the second dielectric portion includes a dielectric material having a dielectric constant less than the dielectric constant of the second dielectric material (as the second dielectric portion includes silicon dioxide which has a dielectric constant less than hafnium oxide).
Regarding claim 14, in the device of the combination, the second dielectric portion includes a dielectric material having a same dielectric constant as the first dielectric material (as the second dielectric portion includes a silicon dioxide).
Regarding claim 15, in the device of the combination, the first dielectric material includes silicon dioxide (as discussed above).
Regarding claim 16, in the device of the combination, the second dielectric portion includes silicon dioxide (as both portions include silicon dioxide).
Regarding claim 17, in the device of the combination, the first portion contains titanium nitride (¶ 0021 of Karda); and the second conductive portion includes polysilicon (¶ 0021).
Regarding claim 18, in the device of the combination, the second dielectric material contacts the second dielectric portion at a first interface;
the first conductive portion contacts the second conductive portion at a second interface; and the first interface is at a level below a level of the second interface (see Fig. 1 of Karda).
Regarding claim 19, in the device of the combination, the conductive structure is part of a word line for a memory cell of the memory device (¶ 0020 of Karda).
Regarding claim 20, in the device of the combination, the memory device includes a semiconductor material (116), and wherein:
the semiconductor material includes a first portion on a first side of the conductive structure;
the semiconductor material includes a second portion on a second side the conductive structure; and
the first and second portions form source and drain, respectively, of a transistor, and the conductive structure forms a control gate of the transistor (¶ 0021-0023 of Karda).
Regarding claim 21, in the device of the combination, one of the first and second semiconductor portions is coupled to a capacitor of the apparatus (¶ 0073 of Karda).
Regarding claim 22, in the device of the combination, one of the first and second semiconductor portions is coupled to a data line of the apparatus (¶ 0022 of Karda).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karda in view of Pillarisetty as applied to claim 8 above, and further in view of Kim et al. (US 2021/0132489 A1).
Regarding claim 9, Karda differs from the claimed invention by the substitution of a second conductive portion containing metal with a doped polysilicon layer. However, using metal as the dopant in polysilicon layers and the corresponding function was known in the art (¶ 0125 of Kim). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known composition of metal doped polysilicon Kim for the doped polysilicon of Karda and the results of the substitution would have been predictable as a gate electrode. (see MPEP § 2143(I)(B)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
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