Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of Priority
The specification asserts the following:
“[0001] This application claims priority to U.S. Provisional Patent Application No. 63/328,543, filed on April 7, 2022, and titled, "Artificial Neural Network Comprising Monte Carlo Reference Array for I-V Slope Configuration," which is incorporated by reference herein.”
The effective filing date of 04/07/2022 is acknowledged.
Information Disclosure Statement
The information disclosure statements submitted on 06/23/2022, 12/19/2022, 07/01/2024, 10/21/2025, 01/13/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Status of Claims
The present application is being examined under the claims filed on 11/21/2025.
Claims 1-9, 11-16, 18-22, 24, 26-29, 31-37 are rejected and pending.
Claims 10, 17, 23, 25, 30 are cancelled.
Prior Art References
The short names that are used to identify the references of prior art in the analysis that follows are:
Short Name
Reference
Kim
Kim, M., 2020. Non-Volatile Neuromorphic Computing based on Logic-Compatible Embedded Flash Memory Technology (Doctoral dissertation, University of Minnesota).
Pavan
Pavan, P., Bez, R., Olivo, P. and Zanoni, E., 2002. Flash memory cells-an overview. Proceedings of the IEEE, 85(8), pp.1248-1271.
Hush
US10741241B2 APPARATUSES AND METHODS FOR SUBARRAY ADDRESSING IN A MEMORY DEVICE
Tang
US20110006347A1 LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS
Wang
Wang, Y.H., Wu, M.C., Lin, C.J., Chu, W.T., Lin, Y.T., Wang, C.S. and Cheng, K.Y., 2005. An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM. IEEE transactions on electron devices, 52(3), pp.385-391.
Ozalevli
US 7280063 B2 - Programmable Voltage-output Floating-gate Digital To Analog Converter And Tunable Resistors
Response to Arguments and Remarks
Examiner finds the amendments and claim cancellations to have resolved the previously cited claim objections, 35 U.S.C. 112(b) rejections, and 35 U.S.C. 112(d) rejections and thus withdraws them. However, new 35 U.S.C. 112(d) rejections have been introduced with the cancellation of claim 10. Refer to the 35 U.S.C. 112(d) rejections in this document.
Applicant remarks:
“Applicant is amending independent claim 1 to recite, "a plurality of reference arrays characterized by different I-V curves, each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells ..." […]
Kim does not disclose this limitation. The Office Action concluded that the "plurality of reference arrays" limitation is satisfied by the "HVS" in Figure 3.9 of Kim. However, the HVS is a high-voltage switch. See Figure 3.9 and accompanying text ("The overall chip architecture is shown in Fig. 3. 9 which contains high voltage switch (HVS) circuits ... "). The HVS does not comprise "a plurality of reference non-volatile memory cells" as required by independent claims 1, 18, 28, and 33. See Kim at p. 50.” (pg. 8)
Examiner response:
Applicant’s arguments have been fully considered but and they are persuasive. Examiner agrees that the high-voltage switch fails to teach the portion of the limitation concerning comprisal of “reference non-volatile memory cells”. In light of this narrower definition, further search and consideration is required. The amended limitation is taught by Ozalevli – refer to the updated claim mappings in this document.
Applicant remarks:
“Moreover, Kim does not indicate that the HVS structures are characterized by different IV curves as required by independent claim 1; instead, the I-V curve language in Kim relates to non-volatile memory cells in the main array and not the HVS or any reference array. See Kim at Figure 3.8 and accompanying text.” (pg. 8)
Examiner response:
Applicant’s arguments have been fully considered but they are not persuasive. Under a broadest reasonable interpretation of the claim language, the HVS structures are characterized by different IV curves because they supply voltage to NVM cells which are themselves have different IV curves as evident by Kim.
Claim Rejections - 35 U.S.C. § 112(d)
The following is a quotation of 35 U.S.C. § 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. § 112(d) as being of improper dependent form. The claims depend on claim 10 which has been canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 13, 14, 16, 18, 20, 21, 24, 28, 29, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ozalevli.
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ozalevli in view of a second embodiment of Kim (Kim 2nd).
Claims 9, 11, 12, 22, 26, 27, 31, 32 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ozalevli in view of Pavan.
Claims 15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ozalevli in view of Hush.
Claims 34, 36, 37 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ozalevli in view of Tang.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ozalevli in view of Wang.
In reference to claim 1.
Kim teaches:
“1. A system comprising: a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells in an artificial neural network (Kim Fig. 3.4, Examiner notes the Xi is the input vector, Wi is the weight matrix and the depicted circuit is performing multiplication with them.);”
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“and a plurality of reference arrays (Kim Fig. 3.9, “HVS”, The HVS blocks generate the reference voltage and collectively constitute the reference arrays) characterized by different I-V curves (Kim Fig. 3.8, The flash cells have different I-V curves based on location and temperature. Thus, each individual array of cells is characterized by different I-V curves.), [each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells],”
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“wherein one or more of the plurality of reference arrays are used to generate an input voltage applied to the vector-by-matrix multiplication array during operation (Kim Fig. 3.9, “VPASS”; Kim Fig. 3.11, “VPASS”).”
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Ozalevli teaches:
“each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells” (Ozalevli (18), “The epots 210 provide dynamically adjustable, non-volatile, on-chip reference voltages. The use of a plurality of epots 210 allows a distinct input voltage to be supplied to each of a plurality of capacitors 242, rather than providing a fixed reference input voltage (i.e., V.sub.ref). This approach may improve the accuracy and speed of the DAC's performance”)
Motivation to combine Kim, Ozalevli.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Kim, Ozalevli. Kim discloses a neuromorphic system implemented on non-volatile memory. Ozalevli discloses a digital-to-analog (DAC) converter implementation requiring non-volatile memory for dynamic voltage inputs. One would be motivated to combine these references because the dynamic voltage output circuit of Ozalevli would be an obvious substitution for the HVS of Kim. Further, MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
In reference to claim 2.
Ozalevli teaches:
“2. The system of claim 1, comprising a control circuit providing a target current through reference non-volatile memory cells of the one or more of the plurality of reference arrays to generate the input voltage (Ozalevli (18), “The epots 210 provide dynamically adjustable, non-volatile, on-chip reference voltages. The use of a plurality of epots 210 allows a distinct input voltage to be supplied to each of a plurality of capacitors 242, rather than providing a fixed reference input voltage (i.e., V.sub.ref). This approach may improve the accuracy and speed of the DAC's performance”).”
In reference to claim 3.
Kim teaches:
“3. The system of claim 1, wherein the respective reference arrays of the plurality of reference arrays differ in at least one dimension (Kim Fig. 3.8; Kim Fig. 3.9, Each HVS module operates on a different IV characteristic curve and thus differs on at least one dimension).”
In reference to claims 4-8.
The claims recite:
“4. The system of claim 3, wherein the dimension is a width of a control gate line of transistors of the respective reference array.”
“5. The system of claim 3, wherein the dimension is a width of a word line of transistors of the respective reference array.”
“6. The system of claim 3, wherein the dimension is a width of a floating gate of transistors of the respective reference array.”
“7. The system of claim 3, wherein the dimension is an overall width of a non-volatile memory cell in the respective reference array.”
“8. The system of claim 3, wherein the dimension is shallow trench isolation spacing of transistors of the respective reference array.”
In all of the above claims, a dimension is being varied. When varying the dimensionality, examiner notes that having different widths itself is not nonobvious. Refer to MPEP2144.04(IV)(A) Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) - Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art. Examiner further notes that all elements of the above claims (width of control gate, width of word line, width of floating gate, overall width of NVM cell, and shallow trench isolation spacing) are all aspects of floating gate transistors that would be obvious to vary.
Kim teaches both an HVS which is composed of transistors (Kim 58, “In this circuit, we added a level shifter circuit and 2 PMOS transistors connected PMOS gate to M and F signals to control VPASS bias with the program and read bias during the program and read operations, respectively compared to the prior HVS circuit [42].”) as well as floating gate transistors (Kim Fig. 3.8). Thus, it would be obvious to combine these two distinct elements of Kim to arrive at the claimed invention.
Motivation to combine Kim, Ozalevli and another embodiment of Kim.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Kim, Ozalevli and a second embodiment of Kim. Kim, Ozalevli discloses a neuromorphic system implemented on non-volatile memory. The second embodiment of Kim discloses floating gate transistors. One would be motivated to combine these references because the floating gate transistor of the second embodiment would be an obvious substitution for the PMOS transistor in the HVS of Kim. Further, MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
In reference to claim 9.
Pavan teaches:
“9. The system of claim 1, wherein the respective reference arrays of the plurality of reference arrays differ in a doping characteristic (Pavan 1250, "The “read” operation is performed by applying to the cell a gate voltage that is between the values of the thresholds of the erased and programmed cells and senses the current flowing through the device. The threshold voltage VT of a MOS transistor can be written as VT = K – Q/Cox where K is a constant that depends on the gate and substrate material, doping, and gate oxide thickness, Q is the charge weighted with respect to its position in the gate oxide, and Cox is the gate oxide capacitance.", As the quoted text notes, cell operation varies with the doping of the underlying material.).”
Motivation to combine Kim, Ozalevli, Pavan.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Kim, Ozalevli and Pavan. Kim discloses a neuromorphic system implemented on non-volatile memory. Pavan discloses an overview of flash memory technology. One would be motivated to combine these references because the disclosure of Pavan provides nuanced details regarding the flash memory cells utilized in Kim and thus may be useful for optimizing the system of Kim. Further, MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
In reference to claim 11.
Pavan teaches:
“11. The system of claim 10, wherein the plurality of non-volatile memory cells are stacked-gate flash memory cells (Pavan Fig. 29).”
In reference to claim 12.
Pavan teaches:
“12. The system of claim 10, wherein the plurality of non-volatile memory cells are split-gate flash memory cells (Pavan Fig. 33).”
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In reference to claim 13.
Kim teaches:
“13. The system of claim 1, wherein the reference arrays generate a bias for the neural network array (Kim 58, "Fig. 3.15,16,17 show the high voltage switch (HVS) circuit to control wordline bias for erase, program, and read operations. In this circuit, we added a level shifter circuit and 2 PMOS transistors connected PMOS gate to M and F signals to control VPASS bias with the program and read bias during the program and read operations, respectively compared to the prior HVS circuit.").”
In reference to claim 14.
Kim teaches:
“14. The system of claim 1, wherein the reference arrays generate a bias for rows of the neural network array (Kim 58, "Fig. 3.15,16,17 show the high voltage switch (HVS) circuit to control wordline bias for erase, program, and read operations. In this circuit, we added a level shifter circuit and 2 PMOS transistors connected PMOS gate to M and F signals to control VPASS bias with the program and read bias during the program and read operations, respectively compared to the prior HVS circuit.").”
In reference to claim 15.
Hush teaches:
“15. The system of claim 1, wherein the plurality of reference arrays and the vector-by-matrix multiplication array are in a same physical array (Hush Abstract, “Concurrent access to different rows within different subarrays may be enabled via independent subarray addressing such that each of the subarrays may serve as a virtual bank.”).”
Motivation to combine Kim, Ozalevli, Hush.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Kim, Ozalevli and Hush. Kim discloses a neuromorphic system implemented on non-volatile memory. Hush discloses subarray addressing methodology in memory arrays. One would be motivated to combine these references because the disclosure of Hush may be integrated into the disclosure of Kim as a methodology for addressing the neuromorphic system. Further, MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (B) Simple substitution of one known element for another to obtain predictable results.
In reference to claim 16.
Kim teaches:
“16. The system of claim 1, wherein the plurality of reference arrays and the vector-by-matrix multiplication array are in different physical arrays (Kim Fig. 3.9, HVS and the synaptic blocks are distinct).”
In reference to claim 18.
Kim teaches:
“18. A method comprising: determining respective metrics for a plurality of reference arrays (Kim Fig. 3.8);”
“identifying a reference array in the plurality of reference arrays for which the determined metric is closest to a target value (Kim 58, "Fig. 3.15,16,17 show the high voltage switch (HVS) circuit to control wordline bias for erase, program, and read operations. In this circuit, we added a level shifter circuit and 2 PMOS transistors connected PMOS gate to M and F signals to control VPASS bias with the program and read bias during the program and read operations, respectively compared to the prior HVS circuit.");”
“and using the identified reference array to generate the input bias of a vector-by-matrix multiplication array in an artificial neural network (Kim 58, "Fig. 3.15,16,17 show the high voltage switch (HVS) circuit to control wordline bias for erase, program, and read operations. In this circuit, we added a level shifter circuit and 2 PMOS transistors connected PMOS gate to M and F signals to control VPASS bias with the program and read bias during the program and read operations, respectively compared to the prior HVS circuit.").”
Ozalevli teaches:
“each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells” (Ozalevli (18), “The epots 210 provide dynamically adjustable, non-volatile, on-chip reference voltages. The use of a plurality of epots 210 allows a distinct input voltage to be supplied to each of a plurality of capacitors 242, rather than providing a fixed reference input voltage (i.e., V.sub.ref). This approach may improve the accuracy and speed of the DAC's performance”)
In reference to claim 19.
Hush teaches:
“19. The method of claim 18, wherein the plurality of reference arrays and the artificial neural network array are in a same physical array (Hush Abstract, “Concurrent access to different rows within different subarrays may be enabled via independent subarray addressing such that each of the subarrays may serve as a virtual bank.”).”
In reference to claim 20.
Kim teaches:
“20. The method of claim 18, wherein the plurality of reference arrays and the artificial neural network array are in different physical arrays (Kim Fig. 3.9, HVS and the synaptic blocks are distinct).”
In reference to claim 21.
Kim teaches:
“21. The method of claim 18, wherein respective reference arrays of the plurality of reference arrays have different electrical characteristics (Kim Fig. 3.8, The flash cells have different I-V curves based on location and temperature. Thus, each individual array of cells have different electrical characteristics.).”
In reference to claim 22.
Pavan teaches:
“22. The method of claim 18, wherein respective reference arrays of the plurality of reference arrays differ in a doping characteristic (Pavan 1250, "The “read” operation is performed by applying to the cell a gate voltage that is between the values of the thresholds of the erased and programmed cells and senses the current flowing through the device. The threshold voltage VT of a MOS transistor can be written as VT = K – Q/Cox where K is a constant that depends on the gate and substrate material, doping, and gate oxide thickness, Q is the charge weighted with respect to its position in the gate oxide, and Cox is the gate oxide capacitance.", As the quoted text notes cell operation varies with the doping of the underlying material.).”
In reference to claim 24.
Kim teaches:
“24. The method of claim 18, wherein the identified reference array is used to generate a bias for rows of the neural network array (Kim 58, "Fig. 3.15,16,17 show the high voltage switch (HVS) circuit to control wordline bias for erase, program, and read operations. In this circuit, we added a level shifter circuit and 2 PMOS transistors connected PMOS gate to M and F signals to control VPASS bias with the program and read bias during the program and read operations, respectively compared to the prior HVS circuit.").”
In reference to claim 26.
Pavan teaches:
“26. The method of claim 18, wherein the plurality of reference non-volatile memory cells are stacked-gate flash memory cells (Pavan Fig. 29).”
In reference to claim 27.
Pavan teaches:
“27. The method of claim 18, wherein the plurality of reference non-volatile memory cells are split-gate flash memory cells (Pavan Fig. 33).”
In reference to claim 28.
Kim teaches:
“28. A system comprising: a vector-by-matrix multiplication array (Kim Fig. 3.4, Examiner notes the Xi is the input vector, Wi is the weight matrix and the depicted circuit is performing multiplication with them.);”
“and a plurality of reference arrays, [each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells], wherein one or more of the plurality of reference arrays are used to generate a bias input applied to the vector-by-matrix multiplication array during operation (Kim Fig. 3.9, “VPASS”; Kim Fig. 3.11, “VPASS”).”
Ozalevli teaches:
“each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells” (Ozalevli (18), “The epots 210 provide dynamically adjustable, non-volatile, on-chip reference voltages. The use of a plurality of epots 210 allows a distinct input voltage to be supplied to each of a plurality of capacitors 242, rather than providing a fixed reference input voltage (i.e., V.sub.ref). This approach may improve the accuracy and speed of the DAC's performance”)
In reference to claim 29.
Kim teaches:
“29. The system of claim 28, wherein the vector-by-matrix multiplication array is a neural network array (Kim Fig. 3.4).”
In reference to claim 31.
Pavan teaches:
“31. The system of claim 28, wherein the plurality of reference non-volatile memory cells are stacked-gate flash memory cells (Pavan Fig. 29).”
In reference to claim 32.
Pavan teaches:
“32. The system of claim 28, wherein the plurality of reference non-volatile memory cells are split-gate flash memory cells (Pavan Fig. 29).”
In reference to claim 33.
Kim teaches:
“33. A system comprising: a plurality of reference arrays, [each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells],wherein one or more of the plurality of reference arrays are used to generate a bias voltage for a vector-by-matrix multiplication array during operation (Kim Fig. 3.9, “VPASS”; Kim Fig. 3.11, “VPASS”).”
Ozalevli teaches:
“each of the plurality of reference arrays comprising a plurality of reference non-volatile memory cells” (Ozalevli (18), “The epots 210 provide dynamically adjustable, non-volatile, on-chip reference voltages. The use of a plurality of epots 210 allows a distinct input voltage to be supplied to each of a plurality of capacitors 242, rather than providing a fixed reference input voltage (i.e., V.sub.ref). This approach may improve the accuracy and speed of the DAC's performance”)
In reference to claim 34.
Tang teaches:
“34. The system of claim 33, wherein the plurality of reference arrays are coupled to bit lines in the same metal layer (Tang Abstract, “In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer.”).”
Motivation to combine Kim, Ozalevli, Tang.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Kim, Ozalevli and Tang. Kim discloses a neuromorphic system implemented on non-volatile memory. Tang discloses a method for connecting a plurality of bit lines. One would be motivated to combine these references because the disclosure of Tang provides a method for physically arranging the system of Kim. Further, MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (B) Simple substitution of one known element for another to obtain predictable results.
In reference to claim 35.
Wang teaches:
“35. The system of claim 33, wherein cells in the plurality of reference arrays are deeply programmed (Wang 388, “When the FG is deeply programmed, the lateral field at the gap is too small to effectively accelerate electrons onto the FG and thus the storage charges vary very little with time and with a density proportional to the applied.”).”
Motivation to combine Kim, Ozalevli, Wang.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Kim, Ozalevli and Wang. Kim discloses a neuromorphic system implemented on non-volatile memory. Wang discloses an analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. One would be motivated to combine these references because the disclosure of Wang provides nuanced details regarding the programming of the floating gates disclosed in Kim. Further, MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
In reference to claim 36.
Tang teaches:
“36. The system of claim 33, wherein the plurality of reference arrays are coupled to bit lines in different metal layers (Tang Abstract, “The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer.”).”
In reference to claim 37.
Tang teaches:
“37. The system of claim 36, wherein the plurality of reference arrays use the same metal layer to route bit lines to a peripheral circuitry (Tang Abstract, “In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer.”).”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CODY RYAN GILLESPIE/Examiner, Art Unit 2147
/VIKER A LAMARDO/Supervisory Patent Examiner, Art Unit 2147