DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 16 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, and 13 are rejected under 35 U.S.C. 103 as unpatentable over Otsubo et al. (“Otsubo” US 2020/0161259) and Kim et al. (“Kim” US 2022/0189929), as evidenced by Shimizu et al. (“Shimizu” US 2023/0142877).
Regarding claim 1, Otsubo discloses a semiconductor package (Figure 12B) comprising:
an upper substrate (8, heat dissipation member is interpreted as a substrate because metallic substrates are known and used in the art, further discussion below);
a lower substrate (2, 12) spaced apart from the upper substrate (8, see Figure 12B);
a semiconductor chip (4) installed on the lower or upper substrate (installed on both the lower and upper substrate, see Figure 12B);
a terminal lead (outer electrodes 11) electrically connected to the lower or upper substrate (connected to the lower substrate 2, see Figure 12B);
an electrical connector (connection terminal of component 4, on lower surface of component 4) for connecting the semiconductor chip (4) to the upper or lower substrate (to the lower substrate, see Figure 12B and para. [0033]);
a sealing member (lower section of sealing resin layer 9b) filled in a space between the upper and lower substrates (2, 8, see Figure 12B), the sealing member (9b) covering the semiconductor chip (4, see Figure 12B) and the electrical connector (connection terminal of component 4);
at least one stopper (upper section of housing 9a) an entire portion of which is disposed on an upper surface of the upper substrate (8, see Figure 12B), the at least one stopper (9a) being formed of a material identical to a material of the sealing member (9b, since both the stoppers 9a and the sealing member 9b are portions of the housing molding 9, they are made of the same material);
a plurality of heat transfer connectors (18, para. [0064]) spaced apart from each other in a horizontal direction (horizontal direction in Figure 12B) and disposed on the upper surface of the upper substrate (8, see Figure 12B); and
a heat sink (heat dissipation fin 20 and shielding layer 10, both provide heat dissipation for the device) provided on upper surfaces of the at least one stopper (9a) and the heat transfer connectors (18, see Figure 12B) for dissipating heat from the semiconductor chip (4, para. [0065]),
wherein the at least one stopper (9a) is provided between the heat transfer connectors (18, positioned in an alternating fashion as shown in the cross-section of Figure 12B),
wherein the heat sink (20/10) is in direct contact with the upper surface of the at least one stopper (9a, see direct contact shown in Figure 12B).
Otsubo does not disclose a substrate that includes an insulating layer, or that the sealing member (9b) further covers side surfaces of the upper substrate (8) and side surfaces of the lower substrate (2/12, see Figure 12B, here “side surfaces” is interpreted to refer to the lateral side surfaces of the substrate 2/12).
Kim discloses an upper substrate (30, see Figure 3) and a lower substrate (20) that both include an insulating layer (ceramic layers 32, 22, para. [0056]-[0057]) and at least one metal layer (21, 23, 31, 33, para. [0056]-[0057]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Otsubo to include an insulating layer for the upper substrate, specifically, for the purpose of using an additional insulating layer for improved thermal dissipation (Kim, para. [0058], [0088]). It is known in the art that ceramic layers (even specifically when used as a substrate) have high thermal conductivity.
Kim further discloses a sealing member (40) that covers side surfaces of the upper substrate (30) and side surfaces of the lower substrate (20, see Figure 3, here “side surface” is interpreted to mean lateral side surfaces of the substrate).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Otsubo to include the sealing member covering side surfaces of the upper and lower substrates for the purpose of suppressing physical damage to the substrates as evidenced by Shimizu (see Figure 27, para. [0125]).
Regarding claim 2, Otsubo discloses wherein the lower substrate (2, 12) comprises an insulating layer (2, insulating material, para. [0031]) and at least one metal layer (12, wiring, para. [0032]).
Otsubo does not disclose that the upper substrate comprises an insulating layer and at least one metal layer, Otsubo discloses that the upper substrate (8) is a metal layer (para. [0035]).
Kim discloses wherein each of the upper and lower substrates (30, 20, respectively, see Figure 3) comprises an insulating layer (ceramic layers 32, 22, para. [0056]-[0057]) and at least one metal layer (21, 23, 31, 33, para. [0056]-[0057]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Otsubo to include an insulating layer and at least one metal layer for each of the upper and lower substrates for the purpose of using a double-sided cooling configuration (Kim, para. [0058], [0088]). It is known in the art that ceramic layers (even specifically when used as a substrate) have high thermal conductivity.
Regarding claim 4, Otsubo discloses wherein the at least one stopper (9a) has a circular, quadrangular, or polygonal shape (Figure 12B shows a polygonal and quadrangular cross-sectional shape of the at least one stopper 9a).
Regarding claim 5, Otsubo discloses wherein the at least one stopper (9a) is formed by partially engraving a surface of the sealing member (engraved surface of molding compound 9) using a laser (para. [0061]).
Regarding claim 6, Otsubo discloses wherein the height of the at least one stopper (9a) is determined by a partial surface of the sealing member (lower surface of 9a, see also upper surface of upper substrate 8) which is not engraved (see Figure 12B).
Regarding claim 13, Otsubo discloses wherein the heat sink (20/10) comprises at least one metal layer (para. [0038]) or at least one ceramic layer.
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Otsubo, Kim, and Shimizu as applied to claim 1 above, and further in view of Otremba et al. (“Otremba” US 2017/0098598).
Regarding claim 3, Otsubo does not explicitly disclose the height of the at least one stopper is 1 µm through 1 mm.
Otremba discloses wherein the height of the at least one stopper (108, para. [0068]) is 1 µm through 1 mm (para. [0068] discloses a height of 300 microns).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Otremba into the teachings of Otsubo to include wherein the height of the at least one stopper is 1 micrometer through 1 mm for the purpose of reducing parasitic capacitance and reduce electric losses (Otremba, para. [0015]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Otsubo, Kim, and Shimizu as applied to claim 1 above, and further in view of Funakoshi et al. (“Funakoshi” US 2008/0224303).
Regarding claim 7, Otsubo discloses wherein the electrical connector (interconnects on lower surface of component 4, electrically connecting the component to the lower substrate 2) is a conductive spacer (the interconnects are a conductive spacer in that they conduct electricity and space apart the component from the upper surface of the lower substrate, i.e. the interconnects determine the spacing between the component and the substrate) in a hexahedral or a cylindrical form (Figure 12B shows a cross-sectional view of the electrical connector having a rectangular shape, which means that the electrical connector seen from a 3D point of view would either be cylindrical or hexahedral in shape).
Further, the courts have ruled that, absent persuasive evidence that the particular configuration (shape) of a claimed element is significant or has unexpected results, the shape of a claimed element is obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04(IV)(B).
In the event that the interconnects on the lower surface of component 4 of Otsubo are wrongly construed as spacers, which the Examiner does not concede, it would have been obvious to incorporate spacers as taught by Funakoshi (spacer 6, see Figure 1) into the teachings of Otsubo for the purpose of preventing electrical discharge between electrodes or interconnects within the device (Funakoshi, para. [0036]).
Regarding claim 8, Otsubo discloses wherein a first end of the spacer (upper surface of electrical interconnect on lower surface of component 4) is electrically joined to the semiconductor chip (4) [using a first conductive adhesive] and a second end of the spacer (lower surface of electrical interconnect on lower surface of component 4) is electrically joined to the upper or lower substrate (2, 12) using a second conductive adhesive (solder used to connect the connection terminal of component 4 to land electrodes on the upper surface of the lower substrate 2, see Figure 12B and para. [0033]).
Otsubo does not explicitly disclose that the first end of the spacer is electrically joined to the semiconductor chip using a first conductive adhesive.
Funakoshi discloses that the first end of the spacer (upper surface of 6, Figure 1) is electrically joined to the semiconductor chip (2) using a first conductive adhesive (solder 4, para. [0035]).
It would have been obvious to incorporate the teachings of Funakoshi into the teachings of Otsubo to include said solder layer for the purpose of improving heat dissipation or refrigerating capability (Funakoshi, para. [0007]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Otsubo, Kim, and Shimizu as applied to claim 1 above, and further in view of Eid et al. (“Eid” US 2021/0249375).
Regarding claim 11, Otsubo does not disclose the at least one stopper comprise at least one spherical grain or at least one round groove on a wall of the at least one stopper.
Eid discloses wherein the at least one stopper (103, 104, para. [0036]) comprise at least one spherical grain (103, Figure 1A) or at least one round groove on the wall of the at least one stopper.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Eid into the teachings of Otsubo to include wherein the at least one stopper comprises at least one spherical grain or at least one round groove on the wall thereof for the purpose of achieving certain coefficients of thermal expansion to mitigate warpage and thermally induced stress (Eid, para. [0044]).
Regarding claim 12, Otsubo does not disclose a diameter of the grain or a depth of the round groove is 1 µm through 100 µm.
Eid discloses, however, wherein a diameter of the grain (103) or a depth of the round groove is 1 micrometer through 100 micrometers (para. [0036] discloses the same range of diameter size).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Eid into the teachings of Otsubo to include wherein a diameter of the grain or a depth of the round groove is 1 micrometer through 100 micrometers for the purpose of adjusting the size of particles in order to achieve certain coefficients of thermal expansion to mitigate warpage and thermally induced stress (Eid, para. [0044]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Otsubo, Kim, and Shimizu as applied to claim 1 above, and further in view of Hashinaga et al. (“Hashinaga” US 2021/0265237).
Regarding claim 14, Otsubo does not explicitly disclose a thickness of the heat transfer connectors is 1 µm through 1 mm.
However, Hashinaga discloses a thickness of the heat transfer connectors (50, para. [0065]) is 1 micrometer through 1 mm (para. [0065] discloses the thickness of heat transfer connector 50, which is within the claimed range).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Hashinaga into the teachings of Otsubo to include wherein the thickness of the heat transfer connector interposed between one surface of the heat sink and the exposed surface of the at least one substrate is 1 micrometer through 1 mm for the purpose of obtaining excellent thermal conductivity (Hashinaga, para. [0098]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Otsubo, Kim, Shimizu, and Hashinaga as applied to claim 14 above, and further in view of Chen et al. (“Chen” US 2021/0082894).
Regarding claim 15, Otsubo discloses the heat transfer connectors have a thermal conductivity (para. [0066] discloses forming heat transfer connectors 18 of a high thermal conductivity substance) [of 1W/m-K through 400W/m-K].
Otsubo does not explicitly disclose the specific vale of the thermal conductivity of the heat transfer connectors (18).
Chen discloses using an interface material (610) with a good thermal conductivity of about 3-10 W/m-K which is within the claimed range of thermal conductivity values.
It would have been obvious to incorporate the teachings of Chen into the teachings of Otsubo to include a thermal conductivity of 1 W/m-K through 400 W/m-K for the purpose of using an interface material with sufficient thermal conductivity (Chen, para. [0090]).
Response to Arguments
Applicant’s arguments and amendments filed March 16 2026 with respect to the 112(a) rejection of claim 1 have been fully considered and overcome the 112(a) rejection. Thus, the 112(a) rejection of claim 1 has been withdrawn.
Applicant’s arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any interpretation of the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The Examiner would like to note after further consideration, however, that the shield layer (10) of Otsubo should not be construed as a sealing member. Rather a sealing member in the art is typically an encapsulant, or a organic polymer layer that serves to electrically insulate and provide physical protection to components and/or interconnects within a package from the external environment.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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