Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 1/08/2026 has been entered. Claims 1, 3-5, 7-11, 14-20, and 33-36 remain pending.
Applicant’s amendments have overcome the 112(a) and 112(b) rejections. Thus, Examiner withdraws the 112(a) and 112(b) rejections.
Response to Arguments
With respect to claims 1 and 11, Applicant presents two arguments.
Applicant’s first argument with respect to claims 1 and 11 is that the combination of Kao, Kissing, Lee, and Kuo does not teach or suggest the added limitation: “an aggressor device disposed entirely within a projection area of the electronic device when viewing along a direction from the semiconductor die to the substrate.” This argument is moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. See Claim Rejections below.
Applicant’s second argument is that the combination of Kao and Lee is improper because Lee’s shielding structure is used to prevent magnetic fields, while Kao’s is for electromagnetic fields, and Lee teaches that magnetic shielding structure must be separated from peripheral circuits. Examiner finds this unpersuasive. First, the fact that Lee’s structure is used as a magnetic shield does not preclude it from being used as an electromagnetic shield. Second, grounding the magnetic shield would serve to suppress EMI. For these reasons, Examiner maintains that a person of ordinary skill in the art would be motivated to combine features of Kao and Lee.
With respect to claims 10 and 20, Applicant states that the amendments render the claims patentable over the prior art. Examiner agrees. Thus, Examiner withdraws the rejections. See Allowable Subject Matter.
With respect to the other claims (including the new claims) see Claim Rejections and Allowable Subject Matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3-5, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over US20180019210A1 (Kao) in view of US20080129394A1 (Kissing), US20150221598A1 (Lee), and US20080211067A1 (Nakashiba).
PNG
media_image1.png
353
588
media_image1.png
Greyscale
Regarding Claim 1, Kao discloses a semiconductor device (Fig. 5 (see above), el. 1, Para. [0027]) comprising: a substrate (Fig. 5, el. 10, Para. [0027]); a semiconductor die (Fig. 5, el. 20, Para. [0030]), disposed on the substrate (Figs. 5, 1, Para. [0023]) and comprising an electronic device (Fig. 5, el. 22, Para. [0027]); and a first shielding structure (Fig. 5, el. 32, Para. [0027]), formed outside of the semiconductor die (Fig. 5, the first shielding structure 32 is outside the semiconductor die 20) and disposed under the electronic device (Fig. 5; the first shielding structure 32 is under the electronic device 22); wherein the substrate comprises a first metal layer disposed below the semiconductor die (Fig. 5, el. 30, Para. [0027]).
Kao does not disclose that the first shielding structure is disposed in the substrate and below the first metal layer, and does not disclose that the substrate further comprises a second metal layer disposed below the first metal layer and level with the first shielding structure, and a third metal layer disposed below the second metal layer. Kao also does not disclose an aggressor device disposed entirely within a projection area of the electronic device when viewing along a direction from the semiconductor die to the substrate.
Kissing discloses a first shielding structure (Fig. 3, see above, el. 1.1, Para. [0019]) that is disposed in a substrate and below a first metal layer (Para. [0022] – although Fig. 3 shows the first shielding structure 1.1 in the first metal layer 1.2, it can also be located in the metal layer 1.3, which is below the first metal layer 1.2 and within the substrate 1).
Lee discloses first, second, and third metal layers (Fig. 9, els. 520, 530, and 540, Para. [0091]) with a second metal layer (Fig. 7C, el. 530, Para. [0086]) disposed below the first metal layer (Fig. 7B, el. 520) with a shielding structure (Fig. 7C, el. 535, Para. [0086]) that is level with the metal layer (Fig. 7C, where the circuit patterns 537 are level with the shielding layer 535).
Nakashiba discloses an aggressor device (Fig. 1, el. 34, Para. [0026]) placed underneath a shielding structure (Fig. 1, el. 40, Para. [0028]), and an electronic device (Fig. 1, el. 16, Para. [0024]) placed above the shielding structure, located in a semiconductor die (Fig. 1, el. 10, Para. [0024]), such that the aggressor device is disposed entirely within a projection area of the electronic device when viewing along a direction from the semiconductor die to the substrate (see Fig. 1).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the shielding structure disclosed by Kao, and move it to a lower layer in the substrate, below the first metal layer, as disclosed by Kissing. In case there is an aggressor device underneath the substrate, it would be advantageous to have the shielding structure closer to the aggressor, and moving it down in the substrate would be beneficial.
Further, it would be obvious to add second and third metal layers, with the shielding layer level with the second metal layer, as disclosed by Lee. Adding a metal layer below the shielding structure increases flexibility in the design, and allows for another routing layer for greater interconnections.
Finally, it would have been obvious to have a shielding layer between an aggressor device and an electronic device such that the aggressor device is entirely within a projection area of the electronic device. As disclosed by Nakashiba, such a configuration prevents the influence of an eddy current generated in the aggressor device from influencing the electronic device (Para. [0013]).
Regarding Claim 3, Kao in view of Kissing and Lee discloses the semiconductor device of claim 1, wherein the first shielding structure (Fig. 4, see below, el. 32, Para. [0027]) is disposed in a keep out zone (Fig. 2, see below, el. 30a, Para. [0024]) of the substrate (Para. [0024]).
PNG
media_image2.png
368
1119
media_image2.png
Greyscale
Regarding claim 4, Kao in view of Kissing and Lee discloses the semiconductor device of claim 3, wherein the keep out zone is disposed in a projection area of the electronic device in a vertical direction (Figs. 2 and 5, see above, Para. [0024] and [0027], Fig. 2 above shows the keep out zone 30a in a projection area of the electronic device 22. Fig 5 above shows that it is in a vertical direction Y).
Regarding Claim 5, Kao in view of Kissing and Lee discloses the semiconductor device of claim 1, wherein the first shielding structure is disposed in a projection area of the electronic device in a vertical direction (Fig. 5, see above, Para. [0027]).
Regarding Claim 7, Kao in view of Kissing and Lee discloses the semiconductor device of claim 1, wherein the electronic device is an inductor (Para. [0034]) and the first shielding structure is a patterned ground shield (Fig. 4, see above, el. 32, Para. [0027]).
PNG
media_image3.png
368
561
media_image3.png
Greyscale
Regarding Claim 8, Kao in view of Kissing and Lee discloses the semiconductor device of claim 1, further comprising: at least two ground connections (Fig. 4, see above, Para. [0027]), each being configured to connect the first shielding structure to a ground plane (Fig. 4, Para. [0027]).
Regarding Claim 9, Kao in view of Kissing and Lee discloses the semiconductor device of claim 8, wherein the at least two ground connections are connected to different sides of the first shielding structure (Fig. 4, see above, Para. [0027]) and arranged along a direction of current flow (as mentioned in the specification of the current application, the direction of current flow may be in the horizontal direction. As shown in Fig. 4 above, the ground connections can be in the horizontal direction or the vertical direction).
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kissing, Lee, and Nakashiba.
Regarding Claim 33, Kao in view of Kissing, Lee, and Nakashiba discloses the semiconductor device of claim 8.
Nakashiba further discloses that the aggressor device is disposed within a projection area of the first shielding structure when viewing along the direction from the semiconductor die to the substrate.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to place the aggressor device between the ground connections so that it is within the projection area formed by the two ground connections and the first shielding structure in order to fully shield the electronic device from the aggressor.
Claims 11 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kissing, Lee, Nakashiba, and US20140284763A1 Yeh et. al (Yeh).
Regarding Claim 11, Kao discloses a semiconductor device (Fig. 5 (see above), el. 1, Para. [0027]), comprising, a substrate (Fig. 5, el. 10, Para. [0027]); a semiconductor die (Fig. 5, el. 20, Para. [0030]), disposed on the substrate (Figs. 5, 1, Para. [0023]) and comprising an electronic device (Fig. 5, el. 22, Para. [0027]); and a first shielding structure (Fig. 5, el. 32, Para. [0027]), formed outside of the semiconductor die (Fig. 5, the first shielding structure 32 is outside the semiconductor die 20) and disposed under the electronic device (Fig. 5; the first shielding structure 32 is under the electronic device 22), wherein the substrate comprises a first metal layer disposed below the semiconductor die (Fig. 5, el. 30, Para. [0027]).
Kao does not disclose a second shielding structure, formed inside of the semiconductor die and disposed above the electronic device, does not disclose that the first shielding structure is disposed in the substrate and below the first metal layer, and does not disclose that the substrate further comprises a second metal layer disposed below the first metal layer and level with the first shielding structure, and a third metal layer disposed below the second metal layer. Kao also does not disclose an aggressor device disposed entirely within a projection area of the electronic device when viewing along a direction from the semiconductor die to the substrate.
Nakashiba discloses an aggressor device (Fig. 1, el. 34, Para. [0026]) placed underneath a shielding structure (Fig. 1, el. 40, Para. [0028]), and an electronic device (Fig. 1, el. 16, Para. [0024]) placed above the shielding structure, located in a semiconductor die (Fig. 1, el. 10, Para. [0024]), such that the aggressor device is disposed entirely within a projection area of the electronic device when viewing along a direction from the semiconductor die to the substrate (see Fig. 1).
Yeh discloses a second shielding structure (Fig. 10, see above, el. 704, Para. [0044]), formed inside of the semiconductor die (Fig. 10, Para. [0044]) and disposed above the electronic device (Fig. 10, Para. [0044]), Kissing discloses a first shielding structure disposed in the substrate (Fig. 3, see above, el. 1.1, Para. [0019]) and below the first metal layer. (Para. [0022] – although Fig. 3 shows the first shielding structure 1.1 in the first metal layer 1.2, it can also be located in the metal layer 1.3, which is below the first metal layer 1.2 and within the substrate 1), and Lee discloses first, second, and third metal layers (Fig. 9, els. 520, 530, and 540, Para. [0091]) with a second metal layer (Fig. 7C, el. 530, Para. [0086]) disposed below the first metal layer (Fig. 7B, el. 520) with a shielding structure (Fig. 7C, el. 535, Para. [0086]) that is level with the metal layer (Fig. 7C, where the circuit patterns 537 are level with the shielding layer 535).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the structure disclosed by Kao, and add the second shielding structure above the electronic device as disclosed by Yeh. As disclosed by Yeh, having a second shielding structure above the inductor would further reduce the forming of eddy current in the semiconductor substrate and possible occurring paths of eddy current are blocked to attain the optimal blocking effect, and the Q-factor can be increased (Para. [0058]). Further, it would be obvious to then move the first shielding structure disclosed by Kao below the first metal layer, as disclosed by Kissing. Doing so would be beneficial if there were an aggressor device below the substrate to prevent coupling between the aggressor and the electronic device. Further, it would be obvious to add second and third metal layers, with the shielding layer level with the second metal layer, as disclosed by Lee. Adding a metal layer below the shielding structure increases flexibility in the design, and allows for another routing layer for greater interconnections.
Finally, it would have been obvious to have a shielding layer between an aggressor device and an electronic device such that the aggressor device is entirely within a projection area of the electronic device. As disclosed by Nakashiba, such a configuration prevents the influence of an eddy current generated in the aggressor device from influencing the electronic device (Para. [0013]).
Regarding claim 13, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 11, wherein the first shielding structure (Fig. 4, see above, el. 32, Para. [0027]) is disposed in a keep out zone of the substrate (Fig. 2, see above, el. 30a, Para. [0024]) of the substrate (Para. [0024]).
Regarding claim 14, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 13, wherein the keep out zone is disposed in a projection area of the electronic device in a vertical direction (Figs. 2 and 5, see above, Para. [0024] and [0027], Fig. 2 above shows the keep out zone 30a in a projection area of the electronic device 22. Fig 5 above shows that it is in a vertical direction Y).
Regarding claim 15, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 11, wherein the first shielding structure is disposed in a projection are of the electronic device in a vertical direction (Fig. 5, see above, Para. [0027]).
Regarding claim 16, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 11, wherein the electronic device is an inductor (Kao, Para. [0034]).
Regarding claim 17, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 11, wherein the first shielding structure and the second shielding structure are patterned ground shields (PGSs) (Kao, Fig. 4, see above, el. 32, Para. [0027], Kao discloses that the first shielding structure is a patterned ground shield; Yeh, Fig. 11, el. 708, Para. [0044], Yeh discloses that the second shielding structure is a patterned ground shield).
Regarding claim 18, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 11, further comprising: at least two ground connections (Yeh, Fig. 4, see above, Para. [0027]), each being configured to connect the first shielding structure to a ground plane (Yeh, Fig. 4, Para. [0027]).
Regarding claim 19, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 18, wherein the at least two ground connections are connected to different sides of the first shielding structure (Kao, Fig. 4, see above, Para. [0027]) and arranged along a direction of current flow (as mentioned in the specification of the current application, the direction of current flow may be in the horizontal direction. As shown in Fig. 4 above, the ground connections can be in the horizontal direction or the vertical direction).
Regarding claim 20, Kao in view of Kissing, Lee, Nakashiba and Yeh discloses the semiconductor device of claim 18 wherein the at least two ground connections are arranged along a direction in which a predetermined trace extends (Fig. 4, see above; as mentioned in the specification of the current application, the direction in which a predetermined trace extends may be the horizontal direction. As shown in Fig. 4 above, the ground connections can be in the horizontal direction or the vertical direction).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kissing, Lee, Nakashiba and Yeh.
Regarding Claim 34, Kao in view of Kissing, Lee, Nakashiba, and Yeh discloses the semiconductor device of claim 18.
Nakashiba further discloses that the aggressor device is disposed within a projection area of the first shielding structure when viewing along the direction from the semiconductor die to the substrate.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to place the aggressor device between the ground connections so that it is within the projection area formed by the two ground connections and the first shielding structure in order to fully shield the electronic device from the aggressor.
Allowable Subject Matter
Claims 10, 20, and 35-36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 10 and 20, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the at least two ground connections are arranged along a direction in which a predetermined trace of the aggressor device extends.
Regarding Claims 35-36, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the electronic device is disposed on and directly contacts a metal layer, the metal layer directly contacts an underfill encapsulant, and the underfill encapsulant is disposed between the semiconductor die and the substrate.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899