DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 11-12, 15, 17, 23 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shih et al. (U.S. Publication No. 2016/0358847).
Regarding claim 1, Shih teaches a substrate comprising:
an electrically conductive pad (Fig. 1H annotated) on a first layer (Fig. 1H annotated) of the substrate;
an electrically conductive feature (Fig. 1H) in the first layer of the substrate, the electrically conductive feature electrically coupled with the electrically conductive pad (Fig. 1H);
an electrically conductive routing (Fig. 1H) in a second layer of the substrate, wherein the electrically conductive routing is electrically coupled with the electrically conductive feature (Fig. 1H);
and a layer that includes silicon and nitrogen (layer 130, see Fig. 1E and 1H, paragraph [0038])) adjacent to the electrically conductive pad (see Fig. 1H, adjacent does not imply direct contact, see Applicant’s paragraph [0020], and therefore the layer 130 is adjacent to the pad through intervening insulating layer), the layer in direct contact with the electrical routing (see Fig. 1H).
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Regarding claim 2, Shih teaches the substrate of claim 1, wherein the layer that includes silicon and nitrogen is at least partially between the electrically conductive pad and the electrically conductive routing in the second layer of the substrate (Fig. 1H).
Regarding claim 3, Shih teaches the substrate of claim 1, wherein the second layer of the substrate is adjacent to the first layer of the substrate (Fig. 1H).
Regarding claim 5, Shih teaches the substrate of claim 1, wherein the layer that includes silicon and nitrogen extends along the first layer of the substrate beyond an edge of the electrically conductive pad (see Fig. 1H).
Regarding claim 6, Shih teaches the substrate of claim 1, wherein the layer that includes silicon and nitrogen includes a silicon nitride (see paragraph [0038]).
Regarding claim 7, Shih teaches the substrate of claim 6, wherein the silicon nitride includes SixNy, wherein X and Y are integers greater than zero, and wherein X is a multiple of three and Y is a multiple of four (see paragraph [0038], SiN is a known abbreviation of Si3N4 when discussing solid layers in electronics).
Regarding claim 11, Shih teaches the substrate of claim 1, wherein the electrically conductive pad includes copper (paragraph [0037]).
Regarding claim 12, Shih teaches the substrate of claim 1, wherein the electrically conductive pad is at a surface of the substrate (Fig. 1K, pad is exposed at bottom surface of substrate).
Regarding claim 15, Shih teaches the substrate of claim 1, wherein a plane of the electrically conductive pad and a plane of the electrically conductive routing are substantially parallel to each other (Fig. 1H).
Regarding claim 17, Shih teaches the substrate of claim 1, wherein the electrically conductive feature and the electrically conductive routing include copper (see paragraph [0037]).
Regarding claim 23, Heo teaches a method comprising:
providing a substrate (Fig. 1H, substrate not labeled as a whole);
placing a layer that includes silicon and nitrogen on a side of the substrate (Fig. 1E and 1H, layer 130);
drilling a via through the layer that includes silicon and nitrogen into the substrate (see Fig. 1E-1F, 130 has holes drilled for vias 128), wherein the via extends to a routing within the substrate (see Fig. 1E-1F, via extends to routing labeled 126 in Fig. 1E);
filling the via with a material that includes copper (via 128, see paragraph [0037]); and
forming a pad (pad labeled in annotated Fig. 1H above) that includes copper on the layer that includes silicon and nitrogen (Fig. 1H, paragraph [0037]), wherein the pad is physically and electrically coupled with the filled via (Fig. 1H), and wherein the layer that includes silicon and nitrogen extends beyond an edge of the pad (Fig. 1H), and wherein the layer that includes silicon and nitrogen is in direct contact with the routing (Fig. 1H).
Regarding claim 25, Heo teaches the method of claim 23, wherein the layer that includes silicon and nitrogen further includes silicon nitride (paragraph [0097]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Heo et al. (U.S. Publication No. 2023/0307340).
Regarding claim 4, Shih teaches the substrate of claim 1, but does not specifically teach wherein a thickness of the layer that includes silicon and nitrogen ranges between 50 nm and 1 um.
However, Heo teaches a similar SiN layer has a thickness of the layer that includes silicon and nitrogen ranges between 50 nm and 1 um (see Heo paragraph [0097], US Publication lists a typo of a square, but should read angstrom Å, see Korean equivalent, paragraph [0121]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the unknown thickness of the layer of Shih could have been the same as that of Heo because it would have been a simple substitution of one thickness for another with predictable results.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Yoo et al. (U.S. Publication No. 2023/0411268)
Regarding claim 9, Shih teaches the substrate of claim 1, but does not teach further comprising a layer on the first layer of the substrate, wherein the layer is on a same side as the electrically conductive pad, wherein the layer is separated from the electrically conductive pad by at least a distance D along the side of the first layer, and wherein the distance D is greater than zero.
However, Yoo teaches a similar substrate having a layer (Yoo Fig. 3, layer 141) on the first layer of the substrate (see Yoo Fig. 3), wherein the layer is on a same side as the electrically conductive pad (Yoo Fig. 3, pad not specifically labeled), wherein the layer is separated from the electrically conductive pad by at least a distance D along the side of the first layer, and wherein the distance D is greater than zero (see Yoo Fig. 1). It would have been obvious to a person of skill in the art at the time of the effective filing date that a layer could have been on the surface of the substrate, separated from the pad, because this a common technique to control solder flow, non-solder mask defined, see Yoo paragraph [0180]).
Regarding claim 10, Shih in view of Yoo teaches the substrate of claim 9, wherein the layer on the first layer of the substrate is a dielectric (Yoo paragraph [0091]).
Claims 13-14 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Han et al. (WO 2022/022419)
Regarding claim 13, Shih teaches the substrate of claim 12, but does not teach further comprising a layer on a surface of the electrically conductive pad that includes a selected one or more of: nickel, palladium, or gold.
However, Han teaches a pad surface treatment including nickel, gold and palladium (Fig. 7, ENEPIG layer 6122). It would have been obvious to a person of skill in the art at the time of the effective filing date that an ENEPIG layer could have been formed on the pad because this improves solderability of the pad.
Regarding claim 14, Heo in view of Han teaches the substrate of claim 13, wherein the layer on the surface of the electrically conductive pad is an ENEPIG (Han Fig. 7, layer 6122).
Regarding claim 24, Shih teaches the method of claim 23, but does not teach further comprising coating a portion of a surface of the pad with a layer that includes a selected one or more of: nickel, palladium, or gold.
However, Han teaches a pad surface treatment including nickel, gold and palladium (Fig. 7, ENEPIG layer 6122). It would have been obvious to a person of skill in the art at the time of the effective filing date that an ENEPIG layer could have been formed on the pad because this improves solderability of the pad.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Kang (U.S. Publication No. 2023/0411275)
Regarding claim 16, Heo teaches the substrate of claim 1, but does not teach wherein the electrically conductive pad is a portion of a landing grid array.
Shih teaches a BGA, however, Kang teaches that LGA and BGA can be interchangeable for semiconductor packages (Kang paragraph [0048]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the solder balls could have not been pre-attached to the package in order to make a LGA because it would have been a simple substitution of one known grid array type for another with predictable results.
Response to Arguments
Applicant’s arguments with respect to all claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 18-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 18-22, the prior art, alone or in combination, fails to teach or suggest wherein the layer that includes silicon and nitrogen is at least partially between the copper pad and the first side of the substrate, and the layer in direct contact with the electrical routing.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899