DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, direct to Claims 1-21 in the reply filed on 02/16/2026 is acknowledged and is under consideration.
Information Disclosure Statement
No Information Disclosure Statement (IDS) has been filed.
Response to Amendment
The amendment with respect to claims 1-21 filed on 02/16/2026 have been fully considered for examination based on their merits. The previously presented claims 22-23 have been withdrawn based on the election by the applicant mentioned above.
Response to Arguments
Applicant’s election to claims 1-21 filed on 02/16/2026, as mentioned above are considered and entered. The non-elected claims 22-23 are hereby withdrawn from further consideration by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, and 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woon Seong Kwon et al, (hereinafter KWON) US 20190312002 A1, in view of Debendra Mallik et al, (hereinafter MALLIK) US 20200273784 A1.
Regarding Claim 1, KWON teaches an apparatus (Fig. 1, 100, integrated component package) comprising:
a substrate (Fig. 1, 107) with a first side (annotated Figure 1) and a second side (annotated Figure 1) opposite the first side (annotated Figure 1), wherein the substrate (Fig. 1, 107) has a first trace width and a first trace spacing (Fig. 1, 117a/117b, traces) that are less than or equal to 3 µm ([0027]); and
a die (Fig. 1, 101, processor) electrically and physically coupled ([0026]) with the first side (annotated Figure 1) of the substrate (Fig. 1, 107) by an array of interconnects (Fig. 1, 113, bump bonds).
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Though KWON teaches an apparatus comprising a die electrically and physically couple with the first side of the substrate by bump bonds. KWON does not explicitly disclose teaches an apparatus comprising a die electrically and physically couple with the first side of the substrate by an array of interconnects.
MALLIK teaches an apparatus (Fig. 1A, 100, package) comprising a die (Fig. 1A, 128, package) electrically and physically couple with the first side (annotated Figure 1A) of the substrate (Fig. 1A, 108, substrate) by an array of interconnects (Fig. 1A, 102, interconnect structures).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KWON to incorporate the teachings of MALLIK, such that an apparatus comprising a die electrically and physically couple with the first side of the substrate by an array of interconnects, so that the interconnect structures, 102 may be used for coupling the interposer, 106 to the package, 128 (MALLIK, [0021]).
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Regarding Claim 2, KWON as modified by MALLIK teaches the apparatus of claim 1.
MALLIK further teaches the apparatus (Fig. 1A, 100, package), wherein the substrate (Fig. 1A, 108, substrate) is a hyper density package (HDP) substrate (Fig. 2G, 204, HDP substrate, [0034]).
Regarding Claim 4, KWON as modified by MALLIK teaches the apparatus of claim 1.
MALLIK further teaches the apparatus (Fig. 1A, 100, package), wherein the array of interconnects (Fig. 1A, 102, interconnect structures) has a pitch of 110 µm or less between adjacent interconnects of the array of interconnects (Fig. 1A, 106, pitch translation interposer has a nominal thickness approximately 60-63 µm, [0021]).
Regarding Claim 5, KWON as modified by MALLIK teaches the apparatus of claim 1.
MALLIK further teaches the apparatus (Fig. 1A, 100, package), wherein the array of interconnects comprises a first array of interconnects (Fig. 1A, 102, interconnect structures), and wherein second side (annotated Figure 1A) of the substrate (Fig. 1A, 108, substrate) has a second array of interconnects (Figs. 1A/1B, 114/154, metal pillars) having a pitch of 210 µm or less (Fig. 1A, 154, ultra-fine pitch (e.g.) a pitch that is greater than or equal to 150 µm, [0014]) between adjacent interconnects of the second array of interconnects (Figs. 1A/1B, 114/154, metal pillars).
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Claim(s) 3, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON, in view of MALLIK, and further in view of Tien-Yu Lee et al, (hereinafter LEE), US 9204542 B1.
Regarding Claim 3, KWON as modified by MALLIK teaches the apparatus of claim 1.
KWON further teaches the apparatus (Fig. 1, 100, integrated component package), wherein the die is a base die of a multi-die complex (Fig. 1, 101, processor include, but are not limited to an application specific integrated circuit (ASIC) and other special purpose processors, [0020]).
KWON as modified by MALLIK does not explicitly disclose the apparatus, wherein the die is a base die of a multi-die complex.
LEE teaches the apparatus (Fig. 1, SSIT product), wherein the die is a base die of a multi-die complex (Fig. 1, 102, top dies).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KWON as modified by MALLIK to incorporate the teachings of LEE, such that the die is a base die of a multi-die complex, so that the SSIT product have compatible top die coupled to each other (LEE, [Col. 7, Lines 25-45]).
Regarding Claim 6, KWON as modified by MALLIK teaches the apparatus of claim 1.
KWON further teaches the apparatus (Fig. 1, 100, integrated component package), wherein the die is a first die (Fig. 1, 101, processor include, but are not limited to an application specific integrated circuit (ASIC) and other special purpose processors, [0020]).
KWON as modified by MALLIK does not explicitly disclose the apparatus, wherein the die is a first die and further comprising: a second die electrically and physically coupled with the first side of the substrate.
LEE teaches the apparatus (Fig. 4-1, 402, SSIT product), wherein the die is a first die (Fig. 4-1, 412a, top dies) and further comprising: a second die (Fig. 4-1, 412b, top dies) electrically and physically coupled ([Col. 10, Lines 15-30]) with the first side of the substrate (Fig. 4-2, 112, package substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KWON as modified by MALLIK to incorporate the teachings of LEE, such that the apparatus, wherein the die is a first die and further comprising: a second die electrically and physically coupled with the first side of the substrate, so that the electrical function of the product is enhanced (LEE, [Col. 10, Lines 15-30]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON, in view of MALLIK, and further in view of Chen-Hua Yu et al, (hereinafter YU), US 20210327778 A1.
Regarding Claim 7, KWON as modified by MALLIK teaches the apparatus of claim 1.
KWON as modified by MALLIK does not explicitly disclose the apparatus, wherein the substrate is a first substrate; and wherein the die includes a second substrate; and further comprising one or more dies electrically and physically coupled with a side of the second substrate.
YU teaches the apparatus (Fig. 18, package structure, [0063]), wherein the substrate is a first substrate (Fig. 18, 300); and wherein the die (Fig. 18, 68) includes a second substrate (Fig. 18, 70); and
further comprising one or more dies (Fig. 18, 88, [0027]) electrically and physically coupled (Figs. 3/18, 77/78, electrical connectors, [0026]) with a side of the second substrate (Fig. 18, 70).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KWON as modified by MALLIK to incorporate the teachings of YU, such that the apparatus, wherein the substrate is a first substrate; and wherein the die includes a second substrate; and further comprising one or more dies electrically and physically coupled with a side of the second substrate, so that forming the electrical connection between the substrate and the dies including memory dies for enhancing their functionality (YU, [0077-0079]).
Claim(s) 8, and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU, in view of KWON.
Regarding Claim 8, YU teaches a package (Fig. 18, package structure, [0063]) comprising:
a first substrate (Fig. 18, 300) having a first side (annotated Figure 18) and a second side (annotated Figure 18) opposite the first side (annotated Figure 18);
a second substrate (Fig. 18, 70) having a first side (annotated Figure 18) and a second side (annotated Figure 18) opposite the first side (annotated Figure 18), the second side (annotated Figure 18) of the second substrate (Fig. 18, 70) electrically and physically coupled (Fig. 18, 120, electrical connectors) with the first side (annotated Figure 18) of the first substrate (Fig. 18, 300);
one or more dies (Fig. 18, 68/88, [0027]) coupled with the first side (annotated Figure 18) of the second substrate (Fig. 18, 70); and
one or more dynamic random-access memory (DRAM) (Fig. 18, 88, [0027]) electrically and physically coupled (Figs. 3/18, 77/78, electrical connectors, [0026]) with the first side (annotated Figure 18) of the first substrate (Fig. 18, 300).
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YU does not explicitly disclose a package comprising: the second substrate has a trace width and a trace spacing of 3 µm or less.
KWON teaches a package (Fig. 1, 100, integrated component package) comprising: the second substrate (Fig. 1, 107) has a trace width and a trace spacing (Fig. 1, 117a/117b, traces) of 3 pm or less ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YU to incorporate the teachings of KWON, such that a package comprising: the second substrate has a trace width and a trace spacing of 3 µm or less, so that the traces (117) between the processor (101) and the HBMs (105) can allow for transfer of data at speeds greater than 2.4 gigabits per second (KWON, Fig. 1A, [0027]).
Regarding Claim 13, YU as modified by KWON teaches the package of claim 8.
YU teaches a package (Fig. 18, package structure, [0063]), wherein the one or more dies (Fig. 19, 400B/412, die/top die) further includes:
a base die (Fig. 19, 400B, die) having a first side (annotated Figure 19) and a second side opposite the first side YU teaches a package (Fig. 18, package structure, [0063]), wherein the second side YU teaches a package (Fig. 18, package structure, [0063]) of the base die (Fig. 19, 400B, die) is physically and electrically coupled (Fig. 19, [0022]) with the first side of the second substrate (Fig. 19, 70); and
a top die (Fig. 19, 412) having a first side (annotated Figure 19) and a second side (annotated Figure 19) opposite the first side (annotated Figure 19), wherein the second side (annotated Figure 19) of the top die (Fig. 19, 412) is physically and electrically coupled (Fig. 19, 410, through vias, [0067]) with the first side (Fig. 19, 412) of the base die (Fig. 19, 400B, die).
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Regarding Claim 14, YU as modified by KWON teaches the package of claim 13.
YU further teaches a package (Fig. 18, package structure, [0063]), wherein a distance between the first side (annotated Figure 19) of the top die (Figs. 19/20, 412) and the first side (annotated Figure 19) of the second substrate (Fig. 19, 70) is 315 µm or less (Fig. 20, (6 xT4 = 6 x 20 µm = 120 µm of memory dies 408 + (T5 = 150 µm of top die) = 270 µm, [0045-0046], [0067], [0069]).
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Regarding Claim 15, YU as modified by KWON teaches the package of claim 13.
YU further teaches a package (Fig. 18, package structure, [0063]), wherein the base die (Fig. 19, 400B, die) includes active circuitry (Figs. 19/20, [0066]).
Regarding Claim 16, YU as modified by KWON teaches the package of claim 8.
YU further teaches a package (Fig. 18, package structure, [0063]), wherein the one or more DRAM (Figs. 19/20, 400B, memory dies, DRAM dies, [0066]) have a first side (annotated Figure 20) and a second side (annotated Figure 20) opposite the first side (annotated Figure 20), wherein the second side (annotated Figure 20) of the one or more DRAM (Figs. 19/20, 400B, memory dies, DRAM dies, [0066]) is physically and electrically coupled (Figs. 19/20, [0022], [0067]) with the first side (annotated Figure 20) of the first substrate (Fig. 18, 300), and wherein a distance between the first side (annotated Figure 20) of the one or more DRAM (Figs. 19/20, 400B, memory dies, DRAM dies, [0066]) and the first side (annotated Figure 20) of the first substrate (Fig. 18, 300) is 900 µm or less (Fig. 20, (6 xT4 = 6 x 60 µm = 360 µm of memory dies 408 + (T5 = 150 µm of top die) + (T3 = 180 µm) = 690 µm, [0045-0046], [0067], [0069]).
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Regarding Claim 17, YU as modified by KWON teaches the package of claim 16.
YU further teaches a package (Fig. 18, package structure, [0063]), wherein a distance between the first side (annotated Figure 20) of the one or more DRAM (Figs. 19/20, 400B, memory dies, DRAM dies, [0066]) and the second side (annotated Figure 20) of the first substrate (Fig. 18, 300) is 1200 µm or less (Fig. 20, (6 xT4 = 6 x 20 µm = 120 µm of memory dies 408 + (T5 = 150 µm of top die) + (T3 = 180 µm) + (T2 = 760 µm) = 1110, [0045-0046], [0067], [0069]).
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Claim(s) 9, 12, 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU, in view of KWON, and further in view of Aniket Patil et al, (hereinafter PATIL), US 20220328417 A1.
Regarding Claim 9, YU as modified by KWON teaches the package of claim 8.
YU as modified by KWON does not explicitly disclose the package, wherein the first substrate is a modified semi-additive process (mSAP) board.
PATIL teaches the package (Fig. 2, 200), wherein the first substrate (Fig. 2, 202/204) is a modified semi-additive process (mSAP) board (Fig. 2, 202/204, [0024-0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YU as modified by KWON to incorporate the teachings of PATIL, such that the package, wherein the first substrate is a modified semi-additive process (mSAP) board, wherein the substrate, 202/204 may be fabricated using different processes, including and ETS process, a semi-additive process (SAP), and a modified semi-additive process (mSAP) (PATIL, [0024-0025]).
Regarding Claim 12, YU as modified by KWON teaches the package of claim 8.
YU as modified by KWON does not explicitly disclose the package, wherein a distance between the first side of the second substrate and the first side of the first substrate is 200 µm or less.
PATIL teaches the package (Fig. 2, 200), wherein a distance between the first side (annotated Figure 2) of the second substrate (Fig. 2, 202) and the first side (annotated Figure 2) of the first substrate (Fig. 2, 204) is 200 µm or less ([0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YU as modified by KWON to incorporate the teachings of PATIL, such that the package, wherein a distance between the first side of the second substrate and the first side of the first substrate is 200 µm or less, so that the configuration and designs of the package, 200 provide packages with improved PDN performance due to the fact that at least one of the passive components may be physically close to at least some of the integrated devices (PATIL, [0037]).
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Regarding Claim 18, YU as modified by KWON teaches the package of claim 8.
YU as modified by KWON does not explicitly disclose the package, wherein the first substrate includes a plurality of layers, wherein one or more of the plurality of layers are mSAP layers.
PATIL teaches the package (Fig. 2, 200), wherein the first substrate (Fig. 2, 202/204) includes a plurality of layers, wherein one or more of the plurality of layers (Fig. 2, 208/220/260, encapsulation layer/dielectric layer) are mSAP layers (Fig. 2, 202/204, [0024-0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YU as modified by KWON to incorporate the teachings of PATIL, such that the package, wherein the first substrate includes a plurality of layers, wherein one or more of the plurality of layers are mSAP layers, so that the substrate, 202/204 may be fabricated using different processes, including and ETS process, a semi-additive process (SAP), and a modified semi-additive process (mSAP) (PATIL, [0024-0025]).
Regarding Claim 19, YU as modified by KWON and PATIL teaches the package of claim 18.
PATIL further teaches the package (Fig. 2, 200), wherein the plurality of layers include eight layers (Figs. 6A/6B, 202/2024, may include different number of layers, [0041], [0045]), and wherein two of the plurality of layers (Figs. 6A/6B, 202/2024, may include different number of layers, [0041], [0045]) are mSAP layers (Fig. 2, 202/204, [0024-0025]).
Regarding Claim 20, YU as modified by KWON and PATIL teaches the package of claim 19.
PATIL further teaches the package (Fig. 2, 200), wherein layer 4 and layer 7 (Figs. 6A/6B, 202/2024, may include different number of layers, [0041], [0045]) of the plurality of layers (Figs. 6A/6B, 202/2024, may include different number of layers, [0041], [0045]) are mSAP layers (Fig. 2, 202/204, [0024-0025]).
Regarding Claim 21, YU as modified by KWON teaches the package of claim 8.
YU as modified by KWON does not explicitly disclose the package, wherein a distance between the first side of the first substrate and the second side of the second substrate is 300 µm or less.
PATIL teaches the package (Fig. 2, 200), wherein a distance between the first side (annotated Figure 2) of the first substrate (Fig. 2, 204) and the second side (annotated Figure 2) of the second substrate (Fig. 2, 202) is 300 µm or less ([0035]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YU as modified by KWON to incorporate the teachings of PATIL, such that the package, wherein a distance between the first side of the first substrate and the second side of the second substrate is 300 µm or less, so that the configuration and designs of the package, 200 provide packages with improved PDN performance due to the fact that at least one of the passive components may be physically close to at least some of the integrated devices (PATIL, [0037]).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over YU, in view of KWON, and further in view of MALLIK.
Regarding Claim 10, YU as modified by KWON teaches the package of claim 8.
YU as modified by KWON does not explicitly disclose the package, wherein a pitch of the second side of the second substrate is less than or equal to 210 µm.
MALLIK teaches the package (Fig. 1A, 100, package), wherein a pitch (Fig. 1A, 154, ultra-fine pitch (e.g.) a pitch that is greater than or equal to 150 µm, [0014]) of the second side (annotated Figure 1A) of the second substrate (Fig. 1A, 108, substrate) is less than or equal to 210 µm (Fig. 1A, 154, ultra-fine pitch (e.g.) a pitch that is greater than or equal to 150 µm, [0014]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YU as modified by KWON to incorporate the teachings of MALLIK, such that the package, wherein a pitch of the second side of the second substrate is less than or equal to 210 µm, so that the thinner pitch (e.g. spacing between package components, etc.) will get finer, which may increase the occurrence of warpage in cored or coreless packages (MALLIK, [0003]).
Regarding Claim 11, YU as modified by KWON teaches the package of claim 8.
YU as modified by KWON does not explicitly disclose the package, wherein a pitch of the first side of the second substrate is less than or equal to 110 µm.
MALLIK further teaches the package (Fig. 1A, 100, package), wherein a pitch (Fig. 1A, 106, pitch translation interposer has a nominal thickness approximately 60-63 µm, [0021]) of the first side (annotated Figure 1A) of the second substrate (Fig. 1A, 108, substrate) is less than or equal to 110 µm (Fig. 1A, 106, pitch translation interposer has a nominal thickness approximately 60-63 µm, [0021]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YU as modified by KWON to incorporate the teachings of MALLIK, such that the package, wherein a pitch of the second side of the second substrate is less than or equal to 210 µm, so that the thinner pitch (e.g. spacing between package components, etc.) will get finer, which may increase the occurrence of warpage in cored or coreless packages (MALLIK, [0003]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220068734 A1 – Figure 4
STATEMENT OF RELEVANCE – Schematic cross-sectional view of mounting the circuit module (1), with the voltage generating circuit (8) and the first capacitors (6) mounted on the module substrate (4), on the main substrate (5).
US 20170064837 A1 – Figure 2
STATEMENT OF RELEVANCE – Integrated circuit (IC) module (200) that includes an integrated circuit (IC) package (201), an interposer (202) and a printed circuit board (PCB) (204).
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812