CTNF 17/848,660 CTNF 98637 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 April 2026 has been entered. Response to Amendment The Office acknowledges receipt on 9 April 2026 of Applicants’ amendments in which claims 1, 11, 12, 16, 19, and 20 are amended and claim 13 is cancelled. The Office withdraws the indefiniteness rejections identified in the Office Communication dated 9 February 2026 in view of the amendments. Response to Arguments Applicants’ argument in the second and third paragraphs of page 8 with respect to claim 1 (and similarly with respect to independent claims 11 and 16) have been considered but are not persuasive. Specifically, Applicants argue [a]mended claim 1 is indeed patentable over the cited references as all the cited references are silent regarding at least the [newly-recited] limitations . Amended claim 1 is rejected over the combined teachings of Lin, Vaed, and Lin ‘612 and recites, in relevant part, “wherein the layer is a ground plane, and wherein the semiconductor region is coupled to a signal plane that is closer to the second surface than the first surface.” Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so . MPEP §2143.01. As this principle applies to the present circumstance, Vaed teaches in Fig. 9 and paragraphs [0065, 0067] a layer (230) is a ground plane (see Examiner’s Note below), and wherein a semiconductor region (173) is coupled to a signal plane (signal plane of 185) (see Examiner’s Note below) that is closer to a second surface (top surface) [of a substrate (102)] than a first surface (bottom surface) [of the substrate (102)]. Examiner’s Note: With respect to the recited “ground” and “signal,” these labels relate to a manner of employing the claimed device rather than to its structure, and accordingly, do not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim Claim Objections 07-29-01 AIA Claim 16 is objected to because of the following informalities: Claim 16, lines 15 and 18, each contain a period indicating the end of a sentence. Because a claim may contain a single sentence and a single period, the period in line 15 should be removed. Claim 16, line 16, recites “is connect ot,” which should read “is connected to” for proper composition Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-5, 9-12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US20140264628A1) (Lin) in view of Vaed et al. (US20070275533A1) and Lin et al. (US20230063612A1) (Lin ‘612) Regarding claim 1 , Lin teaches in Fig. 3A an integrated circuit (IC) device, comprising: a structure (D1 of 22A) comprising a semiconductor material {¶0021}; an additional structure (S1 of 22A) comprising an additional semiconductor material {¶0021} {[0021]}; a semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2) {¶0014} wherein the semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2) is between the structure (D1 of 22A) and the additional structure (S1 of 22A) in a first direction (horizontal), wherein the first direction (horizontal) is orthogonal to a second direction (vertical) {¶0014, 0021}. Lin does not teach: a substrate having a first surface and a second surface, the second surface opposite the first surface; a layer comprising an electrically conductive material, wherein the layer is outside the substrate and is closer to the first surface than the second surface; wherein at least a portion of the structure is closer to the second surface than to the first surface; wherein at least a portion of the additional structure is closer to the second surface than to the first surface; at least of portion of the semiconductor region is closer to the second surface than to the first surface; and a contact structure at least partially enclosed by the substrate, wherein the contact structure comprises an electrically conductive material, a first end of the contact structure is connected to the layer, and a second end of the contact structure is connected to the structure; wherein the second surface is opposite the first surface in a second direction, and the layer is a ground plane, and wherein the semiconductor region is coupled to a signal plane that is closer to the second surface than the first surface. In an analogous art, Vaed teaches in Fig. 9: a substrate (102) having a first surface (bottom surface) and a second surface (top surface), the second surface (top surface) opposite the first surface (bottom surface) {¶0065}; a layer (230) comprising an electrically conductive material, wherein the layer (230) is outside the substrate (102) and is closer to the first surface (bottom surface) than the second surface (top surface) {¶0067}; a contact structure (215) at least partially enclosed by the substrate (102), wherein the contact structure (215) comprises an electrically conductive material, a first end of the contact structure (215) is connected to the layer (230), and a second end of the contact structure (215) is connected to a structure (170/{170, 173}) {¶0067}; wherein the second surface (top surface) is opposite the first surface (bottom surface) in a second direction (vertical), and the layer (230) is a ground plane (see Examiner’s Note below), and wherein a semiconductor region (173) is coupled to a signal plane (signal plane of 185) (see Examiner’s Note below) that is closer to the second surface (top surface) than the first surface (bottom surface). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device based on the teachings of Vaed, to acquire the above-identified features, so as to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance . Vaed ¶0068. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Vaed) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Consequences of this modification are that: (1) at least a portion of Lin’s structure (170) is closer to Vaed’s second surface (top surface) than to Vaed’s first surface (bottom surface), (2) at least a portion of Lin’s additional structure (S1 of 22A) is closer to Vaed’s second surface (top surface) than to Vaed’s first surface (bottom surface); and (3) at least of portion of Lin’s semiconductor region is closer to Vaed’s second surface (top surface) than to Vaed’s first surface (bottom surface). Examiner’s Note: With respect to the recited “ground” and “signal,” these labels relate to a manner of employing the claimed device rather than to its structure, and accordingly, do not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim Lin as modified by Vaed does not teach: the semiconductor material having a dopant concentration of at least 10 18 dopants per cubic centimeter (cm -3 ), and the additional semiconductor material having a dopant concentration of at least 10 18 cm -3 In an analogous art, Lin ‘612 teaches a semiconductor material having a dopant concentration of about 1x10 19 atoms/cm to about 9x10 20 atoms/cm . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed based on the teachings of Lin ‘612 – such that each of the semiconductor material and the additional semiconductor material has a dopant concentration of at least 10 18 dopants per cubic centimeter (cm -3 ) – to improve[] the mobility of charge carriers that migrate … during operation . Lin ¶0039. Regarding claim 2 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein the semiconductor region (region comprising portions of 22s overlapped by G1 and/or G2) comprises a plurality of semiconductor structures (22s) that are in parallel. Regarding claim 3 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein: the layer is a first layer {in the modification of Lin’s IC device discussed with respect to claim 1, Vaed’s layer (230) may be deemed a first layer}, the IC device further comprises a second layer (layer of wiring/(electrical node) above gate G1) comprising another electrically conductive material {Fig. 3A}, and the second layer (layer of wiring/(electrical node) above gate G1) is coupled to the semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2) {¶0021}. Regarding claim 4 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 3, and Lin further teaches wherein the second layer (layer of wiring/(electrical node) above gate G1 in Fig. 3A) is outside the substrate (Vaed’s 100 as integrated within Lin’s modified IC device in modification of claim 1) and is closer to the second surface (top surface of Vaed’s 100 as integrated within Lin’s modified IC device in modification of claim 1) than the first surface (bottom surface of Vaed’s 100 as integrated within Lin’s modified IC device in modification of claim 1). Regarding claim 5 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 3, and Lin further teaches further comprising a gate (G1) coupled to the second layer (layer of wiring/(electrical node) above G1 in Fig. 3A) and to the semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2). Regarding claim 9 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein the IC device is a varactor device {¶0021}. Regarding claim 10 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, but Lin does not teach further comprising: an additional contact structure at least partially enclosed by the substrate, wherein a first end of the additional contact structure is connected to the layer, and a second end of the additional contact structure is connected to the additional structure. Vaed teaches in Fig. 9 an additional contact structure (225) at least partially enclosed by a substrate (100), wherein a first end of the additional contact structure (225) is connected to a layer (230), and a second end of the additional contact structure (225) is connected to an additional structure (145). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Lin ‘612 based on the further teachings of Vaed – to include Vaed’s additional contact structure at least partially enclosed by Vaed’s substrate, wherein a first end of Vaed’s additional contact structure is connected to Vaed’s layer, and a second end of Vaed’s additional contact structure is connected to Lin’s additional structure – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance . Vaed ¶0068. Regarding claim 11 , Lin teaches in Fig. 3A a varactor device, comprising: a plurality of semiconductor structures (D1,22A; S1,22A; D1,22B; S1,22B), an individual semiconductor structure (D1,22A) comprising a doped semiconductor material {¶0022}; a plurality of semiconductor regions (e.g., regions of fins 22A, 22B overlapped by gate G1) coupled (indirectly) to a second electrically conductive layer (layer of wiring/(electrical node[s]) above gate G1) {¶0014}, wherein an individual semiconductor region (e.g., region of fin 22A overlapped by gate G1) is between two semiconductor structures (D1,22A; S1,22A) of the plurality of semiconductor structures (D1,22A; S1,22A; D1,22B; S1,22B) in a first direction (horizontal), wherein the first direction is orthogonal to a second direction (vertical) {¶0014}. Lin does not teach: a plurality of contact structures, an individual contact structure comprising an electrically conductive material and is between a first electrically conductive layer and an individual semiconductor structure of the plurality of semiconductor structures; and wherein the individual semiconductor region is between the first electrically conductive layer and the second electrically conductive layer in a second direction, wherein the plurality of contact structures are connected to the first electrically conductive layer, wherein the first electrically conductive layer is a ground plane, wherein the second electrically conductive layer is a signal plane, and wherein the ground plane and the signal plane are on opposite sides of a substrate. Vaed teaches in Fig. 9 and paragraph [0067] an individual contact structure (215) comprising an electrically conductive material is between a first electrically conductive layer (230) and an individual semiconductor structure (170/{170, 173}); an individual semiconductor region (170/{170, 173}) is between the first electrically conductive layer (230) and a second electrically conductive layer (185) in a second direction (vertical), wherein a plurality of contact structures (215, 225) are connected to the first electrically conductive layer (230), wherein the first electrically conductive layer (230) is a ground plane (see Examiner’s Note below), wherein a second electrically conductive layer (185) is a signal plane (see Examiner’s Note below), and wherein the ground plane (see Examiner’s Note below) and the signal plane (see Examiner’s Note below) are on opposite sides of a substrate (102). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device based on the teachings of Vaed, to acquire the above-identified subject matter, so as to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance . Vaed ¶0068. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Vaed) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Examiner’s Note: With respect to the recited “ground” and “signal,” these labels relate to a manner of employing the claimed device rather than to its structure, and accordingly, do not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim Lin as modified by Vaed does not teach an individual semiconductor structure having a dopant concentration of at least 10 18 dopants per cubic centimeter (cm -3 ). Lin ‘612 teaches a semiconductor material having a dopant concentration of about 1x10 19 atoms/cm to about 9x10 20 atoms/cm . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device as modified by Vaed based on the teachings of Lin ‘612 – such that an individual semiconductor structure having a dopant concentration of at least 10 18 dopants per cubic centimeter (cm -3 ) – to improve[] the mobility of charge carriers that migrate … during operation . Lin ¶0039. Regarding claim 12 , Lin as modified by Vaed and Lin ‘612 teaches the varactor device according to claim 11, but Lin does not teach wherein the substrate between the first electrically conductive layer and the second electrically conductive layer, and wherein at least a portion of the individual contact structure is enclosed in the substrate. Vaed teaches in Fig. 9 and paragraph [0067] a substrate (100) between a first electrically conductive layer (230) and a second electrically conductive layer (185), wherein at least a portion of an individual contact structure (215) is enclosed in a substrate (100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device as modified by Vaed and Lin ‘612 based on the further teachings of Vaed – to include a substrate between the first electrically conductive layer and the second electrically conductive layer, wherein at least a portion of the individual contact structure is enclosed in the substrate – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance . Vaed ¶0068. Regarding claim 14 , Lin as modified by Vaed and Lin ‘612 teaches the varactor device according to claim 11, but Lin does not teach wherein the individual contact structure comprises a metal. Vaed teaches in Fig. 9 and paragraph [0051] the individual contact structure (215) comprises a metal. The motivation for this modification is identified with respect to base claim 11 07-22-aia AIA Claim (s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Lin ‘612 as applied to claim above, and further in view of Lin et al. (US20230411242A1) (Lin ‘242) Regarding claim 6 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, but Lin does not teach wherein a distance from the first surface to the second surface is in a range from 50 nanometers to 70 nanometers. In an analogous art, Lin ‘242 teaches in Fig. 1 and paragraph [0016] a distance from a first surface to a second surface of a substrate (102) is between 15 nm and 80 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Lin ‘612 based on the teachings of Lin ‘242 – such that a distance from the first surface to the second surface is in a range between 15 nm and 80 nm – because all the claimed elements (e.g., substrate, thickness) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lin ‘242) with no change in their respective functions, and the combination yielding nothing more than predictable results (e.g., a substrate) to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists . MPEP §2144.05(I) 07-22-aia AIA Claim (s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Lin ‘612 as applied to claim above, and further in view of Chang et al. (US20160240623A1) and Lu et al. (US20190115342A1) Regarding claim 7 , Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein: the semiconductor material [of the structure (D1 of 22A)] is a first semiconductor material {implicit}, the semiconductor region (region comprising portions of 22s overlapped by G1 and/or G2) comprises a second semiconductor material {implicit}. Lin does not teach a dopant concentration of the second semiconductor material is 10 to 1000 times lower than a dopant concentration of the semiconductor material. In an analogous art, Chang teaches in Fig. 1A and paragraph [0017] a dopant concentration of a second semiconductor material of a semiconductor channel is more than 10 to 10,000 times lower than a dopant concentration of a semiconductor material of an epitaxial region source/drain. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Lin ‘612 based on the teachings of Chang – such that a dopant concentration of the second semiconductor material is more than 10 to 10,000 times lower than a dopant concentration of the semiconductor material – to reduce resistances associated with the source … and the drain . Lu ¶0055. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists . MPEP §2144.05(I). Regarding claim 8 , Lin as modified by Vaed, Lin ‘612, Chang, and Lu teaches the IC device according to claim 7, but Lin does not teach wherein the dopant concentration of the semiconductor material is a concentration of n-type dopants in the semiconductor material. Chang teaches in Fig. 1A and paragraph [0016] the dopant concentration of the semiconductor material is a concentration of n-type dopants in the semiconductor material of the epitaxial region source/drain. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed, Lin ‘612, Chang, and Lu based on the further teachings of Chang – such that the dopant concentration of the semiconductor material is a concentration of n-type dopants in the semiconductor material – to form an NMOS device. Chang ¶0016. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07 07-22-aia AIA Claim (s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Lin ‘612 as applied to claim 11 above, and further in view of Baek et al. (US20250031418A1) Regarding claim 15 , Lin as modified by Vaed and Lin ‘612 teaches the varactor device according to claim 11, but Lin does not teach wherein an individual semiconductor region comprises a plurality of semiconductor ribbons. In an analogous art, Baek teaches in Fig. 1 and paragraphs [0060] and [0061] a semiconductor region (230, N1, N2, N3) comprises a plurality of semiconductor ribbons. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device as modified by Vaed and Lin ‘612 based on the teachings of Baek – such that an individual semiconductor region comprises a plurality of semiconductor ribbons – because all the claimed elements (e.g., semiconductor region, semiconductor ribbons) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Baek) with no change in their respective functions, and the combination yielding nothing more than predictable results (e.g., semiconductor channels) to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07 07-21-aia AIA Claim (s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed Regarding claim 16 , Lin teaches in Fig. 15 an integrated circuit (IC) device, comprising: a first section (1200D, 1200B/1200C) comprising: a first layer (layer of wiring/(electrical node[s]) above gate G3 within 1200D) comprising a first electrically conductive material {Fig. 15}, a second layer (layer of wiring/(electrical node[s]) above gate G2/G1 within 1200B/1200C) comprising a second electrically conductive material {Fig. 15}, a first channel region (channel of 1200D overlapped by gate G3) comprising a first semiconductor material and coupled to the first layer (layer of wiring/(electrical node[s]) above gate G3 within 1200D) {¶0036}, and a second channel region (channel of 1200B/1200C overlapped by gate G2/G1) comprising a second semiconductor material and coupled to the second layer (layer of wiring/(electrical node[s]) above gate G2/G1 within 1200B/1200C) {¶0036}, wherein the first channel region (channel of 1200D overlapped by G3) is separated from the second channel region (channel of 1200B/1200C overlapped by G2/G1) {¶0021}; and a second section (1200A) comprising: a structure (S/D of 1200A) comprising a doped semiconductor material {¶0021}. Lin does not teach: a third layer comprising a third electrically conductive material, and a contact structure comprising an electrically conductive material and being between the third layer and the structure[.], wherein the contact structure is connected ot [ sic ] [to] the third layer, wherein the third layer is a ground plane, and wherein the first layer or the second layer is a signal plane. Vaed teaches in Fig. 9 and paragraph [0067] a third layer (230) comprising a third electrically conductive material, and a contact structure (215) comprising an electrically conductive material and being between the third layer (230) and a structure (170/{170, 173}), wherein the contact structure (215) is connected to the third layer (230), wherein the third layer (230) is a ground plane (see Examiner’s Note below), and wherein a first/second layer (185/165) is a signal plane (see Examiner’s Note below). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device based on the teachings of Vaed, to acquire the above-identified subject matter, so as to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance . Vaed ¶0068. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Vaed) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Examiner’s Note: With respect to the recited “ground” and “signal,” these labels relate to a manner of employing the claimed device rather than to its structure, and accordingly, do not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim Regarding claim 17 , Lin as modified by Vaed teaches the IC device according to claim 16, and Lin further teaches further comprising: a substrate (Fig. 3A, layer disposed beneath 22 & 25) coupled to the first section (1200D, 1200B/1200C) and the second section (1200A). Lin does not teach the substrate is between the first layer and the third layer. Vaed teaches in Fig. 9 and paragraph [0067] a substrate (100) is between a first layer (185) and a third layer (230). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed based on the further teachings of Vaed – such that the substrate is between the first layer and the third layer – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance . Vaed ¶0068 07-22-aia AIA Claim (s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed as applied to claim 17 above, and further in view of Curatola et al. (US20170040312A1) Regarding claim 18 , Lin as modified by Vaed teaches the IC device according to claim 17, but Lin does not teach wherein: the substrate comprises a first portion and a second portion, the first portion comprises a third semiconductor material, the second portion comprises a fourth semiconductor material, and a dopant concentration of the third semiconductor material is two to three times greater than a dopant concentration of the fourth semiconductor material. In an analogous art, Curatola teaches in Fig. 1 and paragraph [0030] a substrate (108) comprises a first portion (132) and a second portion (133), the first portion (132) comprises a third semiconductor material (implicit), the second portion (133) comprises a fourth semiconductor material (implicit), and a dopant concentration of the third semiconductor material is at least two times greater than a dopant concentration of the fourth semiconductor material. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed based on the further teachings of Curatola – such that the substrate comprises a first portion and a second portion, the first portion comprises a third semiconductor material, the second portion comprises a fourth semiconductor material, and a dopant concentration of the third semiconductor material is at least two times greater than a dopant concentration of the fourth semiconductor material – to enhance[] the current spreading capability … and … reduce[] the on-state resistance . Curatola ¶0030 07-22-aia AIA Claim (s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Curatola as applied to claim 18 above, and further in view of Lee et al. (US20200105747A1) Regarding claim 19 , Lin as modified by Vaed and Curatola teaches the IC device according to claim 18, and Lin further teaches further comprising: a first gate (G3) coupled to the first channel region (channel of 1200D overlapped by G3) {Fig. 15}; and a second gate (G2/G1) coupled to the second channel region (channel of 1200B/1200C overlapped by G2/G1) {Fig. 15}. Lin does not teach the first portion of the substrate encloses a portion of the first gate and encloses a portion of the second gate. In an analogous art, Lee teaches in Figs. 1A, 1B, and 3A and paragraph [0036] a first portion (118) of a substrate (104/304) encloses a portion (e.g., bottom portion) of a first gate (one of gates 106/300) and encloses a portion (e.g., bottom portion) of the second gate (another of gates 106/300). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Curatola based on the teachings of Lee – such that the first region encloses a portion of the first gate and encloses a portion of the second gate – to provide higher Q . Lee ¶0031. Regarding claim 20 , Lin as modified by Vaed, Curatola, and Lee teaches the IC device according to claim 19, but Lin does not teach wherein the first portion of the substrate has an opening between the portion of the first gate and the portion of the second gate. Lee teaches in Figs. 1A, 1B, and 3A and paragraph [0036] a first portion (118) of a substrate (104/304) has an opening (308 filled by oxide) between a portion of a first gate (one of gates 106/300) and a portion of a second gate (another of gates 106/300). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed, Curatola, and Lee based on the further teachings of Lee – such that the first portion has an opening between the portion of the first gate and the portion of the second gate – to provide a high-k gate dielectric between the gate and the substrate semiconductor material for increasing the gate capacitance and decreasing leakage current. Lee ¶0028. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness . MPEP §2144.07. Citation of Pertinent Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Coolbaugh et al. (US20060043454A1) teaches a method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a sub-collector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region. A field effect transistor having at least a gate conductor of the first conductivity type is then formed above the inner well region Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.W.W./Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891 Application/Control Number: 17/848,660 Page 2 Art Unit: 2891 Application/Control Number: 17/848,660 Page 3 Art Unit: 2891 Application/Control Number: 17/848,660 Page 4 Art Unit: 2891 Application/Control Number: 17/848,660 Page 5 Art Unit: 2891 Application/Control Number: 17/848,660 Page 6 Art Unit: 2891 Application/Control Number: 17/848,660 Page 7 Art Unit: 2891 Application/Control Number: 17/848,660 Page 8 Art Unit: 2891 Application/Control Number: 17/848,660 Page 9 Art Unit: 2891 Application/Control Number: 17/848,660 Page 10 Art Unit: 2891 Application/Control Number: 17/848,660 Page 11 Art Unit: 2891 Application/Control Number: 17/848,660 Page 12 Art Unit: 2891 Application/Control Number: 17/848,660 Page 13 Art Unit: 2891 Application/Control Number: 17/848,660 Page 14 Art Unit: 2891 Application/Control Number: 17/848,660 Page 15 Art Unit: 2891 Application/Control Number: 17/848,660 Page 16 Art Unit: 2891 Application/Control Number: 17/848,660 Page 17 Art Unit: 2891 Application/Control Number: 17/848,660 Page 18 Art Unit: 2891 Application/Control Number: 17/848,660 Page 19 Art Unit: 2891 Application/Control Number: 17/848,660 Page 20 Art Unit: 2891
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