DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 21 November 2025 of Applicants’ amendments in which claims 1, 10, 11, 16, 18, and 19 are amended. The Office withdraws the drawing objection, claim objection, and indefiniteness rejections identified in the Office Communication dated 25 August 2025 in view of the amendments.
Response to Arguments
Applicants’ arguments in the second paragraph of page 8 with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants argue in the last paragraph of page 8 and with respect to independent claim 16 that this claim has been amended to recite first and second channel regions so as to distinguish these regions from Lin’s source and drain regions. Claim 16 is rejected over the combined teachings of Lin and Vaed and recites, in relevant part, “a first channel region comprising a first semiconductor material and coupled to the first layer, and a second channel region comprising a second semiconductor material and coupled to the second layer.” Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Lin teaches in Fig. 15 a first channel region (channel of 1200D overlapped by gate G3) comprising a first semiconductor material and coupled to the first layer (layer of wiring/(electrical node[s]) above gate G3 within 1200D) {¶0036}, and a second channel region (channel of 1200B/1200C overlapped by gate G2/G1) comprising a second semiconductor material and coupled to the second layer (layer of wiring/(electrical node[s]) above gate G2/G1 within 1200B/1200C) {¶0036}. Accordingly, Applicants’ arguments are not persuasive in view of the new mapping of Lin’s teachings to amended claim 16.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 17, recites “the semiconductor regions,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of claim 1, this recitation will be interpreted as “the semiconductor region.” Claims 2-10 are rejected due to their dependencies from base claim 1.
Claim 19, line 4, recites “the first region,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with intermediate claim 18, this recitation will be interpreted as “the first portion.” Claim 20 is rejected due to its dependency from claim 19.
Claim 20, line 1, recites “the first region,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with intermediate claim 18, this recitation will be interpreted as “the first portion.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 9-12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US20140264628A1) (Lin) in view of Vaed et al. (US20070275533A1) and Lin et al. (US20230063612A1) (Lin ‘612).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Lin teaches in Fig. 3A an integrated circuit (IC) device, comprising:
a structure (D1 of 22A) comprising a semiconductor material {¶0021};
an additional structure (S1 of 22A) comprising an additional semiconductor material {¶0021} {[0021]};
a semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2) {¶0014}
wherein the semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2) is between the structure (D1 of 22A) and the additional structure (S1 of 22A) in a first direction (horizontal), wherein the first direction (horizontal) is orthogonal to a second direction (vertical) {¶0014, 0021}.
Lin does not teach:
a substrate having a first surface and a second surface, the second surface opposite the first surface;
a layer comprising an electrically conductive material, wherein the layer is outside the substrate and is closer to the first surface than the second surface;
wherein at least a portion of the structure is closer to the second surface than to the first surface;
wherein at least a portion of the additional structure is closer to the second surface than to the first surface;
at least of portion of the semiconductor region is closer to the second surface than to the first surface; and
a contact structure at least partially enclosed by the substrate, wherein the contact structure comprises an electrically conductive material, a first end of the contact structure is connected to the layer, and a second end of the contact structure is connected to the structure;
wherein the second surface is opposite the first surface in a second direction.
In an analogous art, Vaed teaches in Fig. 9:
a substrate (100) having a first surface (bottom surface) and a second surface (top surface), the second surface (top surface) opposite the first surface (bottom surface) {¶0065};
a layer (230) comprising an electrically conductive material, wherein the layer (230) is outside the substrate (100) and is closer to the first surface (bottom surface) than the second surface (top surface) {¶0067};
a contact structure (215) at least partially enclosed by the substrate (100), wherein the contact structure (215) comprises an electrically conductive material, a first end of the contact structure (215) is connected to the layer (230), and a second end of the contact structure (215) is connected to a structure (170) {¶0067};
wherein the second surface (top surface) is opposite the first surface (bottom surface) in a second direction (vertical).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device based on the teachings of Vaed – to include a substrate having a first surface and a second surface, the second surface opposite the first surface; a layer comprising an electrically conductive material, wherein the layer is outside the substrate and is closer to the first surface than the second surface; a contact structure at least partially enclosed by the substrate, wherein the contact structure comprises an electrically conductive material, a first end of the contact structure is connected to the layer, and a second end of the contact structure is connected to a structure; wherein the second surface is opposite the first surface in a second direction – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance. Vaed ¶0068. Consequences of this modification are that: (1) at least a portion of Lin’s structure (170) is closer to Vaed’s second surface (top surface) than to Vaed’s first surface (bottom surface), (2) at least a portion of Lin’s additional structure (S1 of 22A) is closer to Vaed’s second surface (top surface) than to Vaed’s first surface (bottom surface); and (3) at least of portion of Lin’s semiconductor region is closer to Vaed’s second surface (top surface) than to Vaed’s first surface (bottom surface).
Lin as modified by Vaed does not teach:
the semiconductor material having a dopant concentration of at least 1018 dopants per cubic centimeter (cm-3), and
the additional semiconductor material having a dopant concentration of at least 1018 cm-3.
In an analogous art, Lin ‘612 teaches a semiconductor material having a dopant concentration of about 1x1019 atoms/cm3 to about 9x1020 atoms/cm3. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed based on the teachings of Lin ‘612 – such that each of the semiconductor material and the additional semiconductor material has a dopant concentration of at least 1018 dopants per cubic centimeter (cm-3) – to improve[] the mobility of charge carriers that migrate … during operation. Lin ¶0039.
Regarding claim 2, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein the semiconductor region (region comprising portions of 22s overlapped by G1 and/or G2) comprises a plurality of semiconductor structures (22s) that are in parallel.
Regarding claim 3, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein:
the layer is a first layer {in the modification of Lin’s IC device discussed with respect to claim 1, Vaed’s layer (230) may be deemed a first layer},
the IC device further comprises a second layer (layer of wiring/(electrical node) above gate G1) comprising another electrically conductive material {Fig. 3A}, and
the second layer (layer of wiring/(electrical node) above gate G1) is coupled to the semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2) {¶0021}.
Regarding claim 4, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 3, and Lin further teaches wherein the second layer (layer of wiring/(electrical node) above gate G1 in Fig. 3A) is outside the substrate (Vaed’s 100 as integrated within Lin’s modified IC device in modification of claim 1) and is closer to the second surface (top surface of Vaed’s 100 as integrated within Lin’s modified IC device in modification of claim 1) than the first surface (bottom surface of Vaed’s 100 as integrated within Lin’s modified IC device in modification of claim 1).
Regarding claim 5, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 3, and Lin further teaches further comprising a gate (G1) coupled to the second layer (layer of wiring/(electrical node) above G1 in Fig. 3A) and to the semiconductor region (region comprising portions of 22s overlapped by gate G1 and/or G2).
Regarding claim 9, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein the IC device is a varactor device {¶0021}.
Regarding claim 10, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, but Lin does not teach further comprising:
an additional contact structure at least partially enclosed by the substrate, wherein a first end of the additional contact structure is connected to the layer, and a second end of the additional contact structure is connected to the additional structure.
Vaed teaches in Fig. 9 an additional contact structure (225) at least partially enclosed by a substrate (100), wherein a first end of the additional contact structure (225) is connected to a layer (230), and a second end of the additional contact structure (225) is connected to an additional structure (145). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Lin ‘612 based on the further teachings of Vaed – to include Vaed’s additional contact structure at least partially enclosed by Vaed’s substrate, wherein a first end of Vaed’s additional contact structure is connected to Vaed’s layer, and a second end of Vaed’s additional contact structure is connected to Lin’s additional structure – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance. Vaed ¶0068.
Regarding claim 11, Lin teaches in Fig. 3A a varactor device, comprising:
a plurality of semiconductor structures (D1,22A; S1,22A; D1,22B; S1,22B), an individual semiconductor structure (D1,22A) comprising a doped semiconductor material {¶0022};
a plurality of semiconductor regions (e.g., regions of fins 22A, 22B overlapped by gate G1) coupled (indirectly) to a second electrically conductive layer (layer of wiring/(electrical node[s]) above gate G1) {¶0014},
wherein an individual semiconductor region (e.g., region of fin 22A overlapped by gate G1) is between two semiconductor structures (D1,22A; S1,22A) of the plurality of semiconductor structures (D1,22A; S1,22A; D1,22B; S1,22B) in a first direction (horizontal), wherein the first direction is orthogonal to a second direction (vertical) {¶0014}.
Lin does not teach:
a plurality of contact structures, an individual contact structure comprising an electrically conductive material and is between a first electrically conductive layer and an individual semiconductor structure of the plurality of semiconductor structures; and
wherein the individual semiconductor region is between the first electrically conductive layer and the second electrically conductive layer in a second direction.
Vaed teaches in Fig. 9 and paragraph [0067] an individual contact structure (215) comprising an electrically conductive material is between a first electrically conductive layer (230) and an individual semiconductor structure (170). Vaed further teaches in Fig. 9 and paragraph [0067] an individual semiconductor region (170) is between the first electrically conductive layer (230) and a second electrically conductive layer (185) in a second direction (vertical). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device based on the teachings of Vaed – to include a plurality of contact structures, wherein an individual contact structure comprises an electrically conductive material and is disposed between a first electrically conductive layer and an individual semiconductor structure of Lin’s plurality of semiconductor structures; and wherein the individual semiconductor region is between the first electrically conductive layer and the second electrically conductive layer in a second direction – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance. Vaed ¶0068.
Lin as modified by Vaed does not teach an individual semiconductor structure having a dopant concentration of at least 1018 dopants per cubic centimeter (cm-3).
Lin ‘612 teaches a semiconductor material having a dopant concentration of about 1x1019 atoms/cm3 to about 9x1020 atoms/cm3. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device as modified by Vaed based on the teachings of Lin ‘612 – such that an individual semiconductor structure having a dopant concentration of at least 1018 dopants per cubic centimeter (cm-3) – to improve[] the mobility of charge carriers that migrate … during operation. Lin ¶0039.
Regarding claim 12, Lin as modified by Vaed and Lin ‘612 teaches the varactor device according to claim 11, but Lin does not teach further comprising:
a substrate between the first electrically conductive layer and the second electrically conductive layer,
wherein at least a portion of the individual contact structure is enclosed in the substrate.
Vaed teaches in Fig. 9 and paragraph [0067] a substrate (100) between a first electrically conductive layer (230) and a second electrically conductive layer (185), wherein at least a portion of an individual contact structure (215) is enclosed in a substrate (100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device as modified by Vaed and Lin ‘612 based on the further teachings of Vaed – to include a substrate between the first electrically conductive layer and the second electrically conductive layer, wherein at least a portion of the individual contact structure is enclosed in the substrate – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance. Vaed ¶0068.
Regarding claim 14, Lin as modified by Vaed and Lin ‘612 teaches the varactor device according to claim 11, but Lin does not teach wherein the individual contact structure comprises a metal.
Vaed teaches in Fig. 9 and paragraph [0051] the individual contact structure (215) comprises a metal. The motivation for this modification is identified with respect to base claim 11.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Lin ‘612 as applied to claim 1 above, and further in view of Lin et al. (US20230411242A1) (Lin ‘242).
Regarding claim 6, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, but Lin does not teach wherein a distance from the first surface to the second surface is in a range from 50 nanometers to 70 nanometers.
In an analogous art, Lin ‘242 teaches in Fig. 1 and paragraph [0016] a distance from a first surface to a second surface of a substrate (102) is between 15 nm and 80 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Lin ‘612 based on the teachings of Lin ‘242 – such that a distance from the first surface to the second surface is in a range between 15 nm and 80 nm – because all the claimed elements (e.g., substrate, thickness) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lin ‘242) with no change in their respective functions, and the combination yielding nothing more than predictable results (e.g., a substrate) to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Lin ‘612 as applied to claim 1 above, and further in view of Chang et al. (US20160240623A1) and Lu et al. (US20190115342A1).
Regarding claim 7, Lin as modified by Vaed and Lin ‘612 teaches the IC device according to claim 1, and Lin further teaches wherein:
the semiconductor material [of the structure (D1 of 22A)] is a first semiconductor material {implicit},
the semiconductor region (region comprising portions of 22s overlapped by G1 and/or G2) comprises a second semiconductor material {implicit}.
Lin does not teach a dopant concentration of the second semiconductor material is 10 to 1000 times lower than a dopant concentration of the semiconductor material.
In an analogous art, Chang teaches in Fig. 1A and paragraph [0017] a dopant concentration of a second semiconductor material of a semiconductor channel is more than 10 to 10,000 times lower than a dopant concentration of a semiconductor material of an epitaxial region source/drain. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Lin ‘612 based on the teachings of Chang – such that a dopant concentration of the second semiconductor material is more than 10 to 10,000 times lower than a dopant concentration of the semiconductor material – to reduce resistances associated with the source … and the drain. Lu ¶0055. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 8, Lin as modified by Vaed, Lin ‘612, Chang, and Lu teaches the IC device according to claim 7, but Lin does not teach wherein the dopant concentration of the semiconductor material is a concentration of n-type dopants in the semiconductor material.
Chang teaches in Fig. 1A and paragraph [0016] the dopant concentration of the semiconductor material is a concentration of n-type dopants in the semiconductor material of the epitaxial region source/drain. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed, Lin ‘612, Chang, and Lu based on the further teachings of Chang – such that the dopant concentration of the semiconductor material is a concentration of n-type dopants in the semiconductor material – to form an NMOS device. Chang ¶0016. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Lin ‘612 as applied to claim 11 above, and further in view of Alping et al. (US6380600B1) and Then et al. (US20220102339A1).
Regarding claim 13, Lin as modified by Vaed and Lin ‘612 teaches the varactor device according to claim 11, but Lin does not teach wherein the first electrically conductive layer is a ground plane.
In an analogous art, Alping teaches in Fig. 14 and lines 50-51 of column 8 an electrically conductive layer (190) is a ground plane. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device as modified by Vaed and Lin ‘612 based on the teachings of Alping – such that the first electrically conductive layer is a ground plane – to reduce inductive effect of long interconnects to ground. Then ¶0178. Additionally, making the conductive layer a ground plane creates a low-impedance return path for current. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Lin ‘612 as applied to claim 11 above, and further in view of Baek et al. (US20250031418A1).
Regarding claim 15, Lin as modified by Vaed and Lin ‘612 teaches the varactor device according to claim 11, but Lin does not teach wherein an individual semiconductor region comprises a plurality of semiconductor ribbons.
In an analogous art, Baek teaches in Fig. 1 and paragraphs [0060] and [0061] a semiconductor region (230, N1, N2, N3) comprises a plurality of semiconductor ribbons. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s varactor device as modified by Vaed and Lin ‘612 based on the teachings of Baek – such that an individual semiconductor region comprises a plurality of semiconductor ribbons – because all the claimed elements (e.g., semiconductor region, semiconductor ribbons) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Baek) with no change in their respective functions, and the combination yielding nothing more than predictable results (e.g., semiconductor channels) to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed.
Regarding claim 16, Lin teaches in Fig. 15 an integrated circuit (IC) device, comprising:
a first section (1200D, 1200B/1200C) comprising:
a first layer (layer of wiring/(electrical node[s]) above gate G3 within 1200D) comprising a first electrically conductive material {Fig. 15},
a second layer (layer of wiring/(electrical node[s]) above gate G2/G1 within 1200B/1200C) comprising a second electrically conductive material {Fig. 15},
a first channel region (channel of 1200D overlapped by gate G3) comprising a first semiconductor material and coupled to the first layer (layer of wiring/(electrical node[s]) above gate G3 within 1200D) {¶0036}, and
a second channel region (channel of 1200B/1200C overlapped by gate G2/G1) comprising a second semiconductor material and coupled to the second layer (layer of wiring/(electrical node[s]) above gate G2/G1 within 1200B/1200C) {¶0036},
wherein the first channel region (channel of 1200D overlapped by G3) is separated from the second channel region (channel of 1200B/1200C overlapped by G2/G1) {¶0021}; and
a second section (1200A) comprising:
a structure (S/D of 1200A) comprising a doped semiconductor material {¶0021}.
Lin does not teach:
a third layer comprising a third electrically conductive material, and
a contact structure comprising an electrically conductive material and being between the third layer and the structure.
Vaed teaches in Fig. 9 and paragraph [0067] a third layer (230) comprising a third electrically conductive material, and a contact structure (215) comprising an electrically conductive material and being between the third layer (230) and a structure (170). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device based on the teachings of Vaed – to include a third layer comprising a third electrically conductive material, and a contact structure comprising an electrically conductive material and being between the third layer and the structure – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance. Vaed ¶0068.
Regarding claim 17, Lin as modified by Vaed teaches the IC device according to claim 16, and Lin further teaches further comprising:
a substrate (Fig. 3A, layer disposed beneath 22 & 25) coupled to the first section (1200D, 1200B/1200C) and the second section (1200A).
Lin does not teach the substrate is between the first layer and the third layer.
Vaed teaches in Fig. 9 and paragraph [0067] a substrate (100) is between a first layer (185) and a third layer (230). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed based on the further teachings of Vaed – such that the substrate is between the first layer and the third layer – to function … as a heat sink for reducing the junction temperature in the … device and/or reduce the parasitic resistance …, thereby improving the device performance. Vaed ¶0068.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed as applied to claim 17 above, and further in view of Curatola et al. (US20170040312A1).
Regarding claim 18, Lin as modified by Vaed teaches the IC device according to claim 17, but Lin does not teach wherein:
the substrate comprises a first portion and a second portion,
the first portion comprises a third semiconductor material,
the second portion comprises a fourth semiconductor material, and
a dopant concentration of the third semiconductor material is two to three times greater than a dopant concentration of the fourth semiconductor material.
In an analogous art, Curatola teaches in Fig. 1 and paragraph [0030] a substrate (108) comprises a first portion (132) and a second portion (133), the first portion (132) comprises a third semiconductor material (implicit), the second portion (133) comprises a fourth semiconductor material (implicit), and a dopant concentration of the third semiconductor material is at least two times greater than a dopant concentration of the fourth semiconductor material. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed based on the further teachings of Curatola – such that the substrate comprises a first portion and a second portion, the first portion comprises a third semiconductor material, the second portion comprises a fourth semiconductor material, and a dopant concentration of the third semiconductor material is at least two times greater than a dopant concentration of the fourth semiconductor material – to enhance[] the current spreading capability … and … reduce[] the on-state resistance. Curatola ¶0030.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Vaed and Curatola as applied to claim 18 above, and further in view of Lee et al. (US20200105747A1).
Regarding claim 19, as interpreted in view of the indefiniteness rejection, Lin as modified by Vaed and Curatola teaches the IC device according to claim 18, and Lin further teaches further comprising:
a first gate (G3) coupled to the first channel region (channel of 1200D overlapped by G3) {Fig. 15}; and
a second gate (G2/G1) coupled to the second channel region (channel of 1200B/1200C overlapped by G2/G1) {Fig. 15}.
Lin does not teach the first portion encloses a portion of the first gate and encloses a portion of the second gate.
In an analogous art, Lee teaches in Figs. 1A, 1B, and 3A and paragraph [0036] a first portion (118) of a substrate (104/304) encloses a portion (e.g., bottom portion) of a first gate (one of gates 106/300) and encloses a portion (e.g., bottom portion) of the second gate (another of gates 106/300). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed and Curatola based on the teachings of Lee – such that the first region encloses a portion of the first gate and encloses a portion of the second gate – to provide higher Q. Lee ¶0031.
Regarding claim 20, as interpreted in view of the indefiniteness rejection, Lin as modified by Vaed, Curatola, and Lee teaches the IC device according to claim 19, but Lin does not teach wherein the first portion has an opening between the portion of the first gate and the portion of the second gate.
Lee teaches in Figs. 1A, 1B, and 3A and paragraph [0036] a first portion (118) of a substrate (104/304) has an opening (308 filled by oxide) between a portion of a first gate (one of gates 106/300) and a portion of a second gate (another of gates 106/300). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s IC device as modified by Vaed, Curatola, and Lee based on the further teachings of Lee – such that the first portion has an opening between the portion of the first gate and the portion of the second gate – to provide a high-k gate dielectric between the gate and the substrate semiconductor material for increasing the gate capacitance and decreasing leakage current. Lee ¶0028. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891