DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 10 and 15.
Pending: 1-3, 5-15, 17, 19-20, 23-25.
Canceled: 4, 16, 18, 21-22.
New: 24-25.
Response to Arguments
Applicant’s arguments with respect to claim(s) 15, 17, 19-20 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15, 17, 19 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Banna et al., US Patent 8609510 B1; in view of Park et al., US 20170345825 A1.
Re: Independent Claim 15, Banna discloses forming a semiconductor fin (108 and 110 as the fin structure, fig. 2 and 3) over a substrate (110 near layer 109, fig. 3);
forming first, second, and third gate structures (102, 102 and 104, fig. 3) crossing the semiconductor fin (108 and 110 as the fin structure, fig. 2 and 3);
forming first epitaxy structures (dotted line within fin 110, fig. 3) in the semiconductor fin (108 and 110 as the fin structure, fig. 2 and 3) and on opposite sides of the first gate structure (102, fig. 3) and forming second epitaxy structures (dotted line within fin 110, fig. 3) in the semiconductor fin (108 and 110 as the fin structure, fig. 2 and 3) and on opposite sides of the second gate structure (102, fig. 3);
removing the third gate structure (104, fig. 7-8) to expose a portion of the semiconductor fin (108 and 110 as the fin structure, fig. 2 and 3).
Banna is silent regarding: performing an implantation process to form region in the exposed portion of the substrate (110 near layer 109, fig. 3), wherein the region has a widest width at a top surface substrate and a width of the region tapers downwardly; and after the implantation process is complete, forming a dielectric structure (134 and 136, fig. 9) over the implantation region in the semiconductor fin (108 and 110 as the fin structure, fig. 2 and 3).
Park teaches forming form an implantation region (122-124, fig. 12C) in the exposed portion of the substrate (133, fig. 12C), wherein the region (122-124) has a widest width at a top surface substrate (113) and a width of the region (122-124) tapers downwardly (fig. 12c); and after the implantation process is complete as shown in figure 12B, forming a dielectric structure (126, fig. 12D) over the implantation region (122-124) in the semiconductor .
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an implantation region and isolation structure in the substrate between source and drain region since the implantation region with isolation layer between source/drain region can prevent the increase of a threshold voltage of the channel region formed adjacent to the sidewall of the trench and the stopper regions prevent surface depletions of the threshold voltage control regions adjacent to the sidewall and bottom face of the trench (column 17, lines 28-32; column 25, lines 59-64).
Re: Claim 17, Banna and Park discloses all the limitations of claim 15 on which this claim depends. Banna further discloses: forming first spacers (118, fig. 9) on opposite sidewalls of the first gate structure (102, fig. 3), second spacers (118, fig. 9) on opposite sidewalls of the second gate structure (102, fig. 3), and third spacers (118, fig. 9) on opposite sidewalls of the third gate structure (104, fig. 7-8), wherein removing the third gate structure (104, fig. 7-8) is performed to form a trench between the third spacers (118, fig. 9), and a widest width of the implantation region is substantially equal to a distance between the third spacers (118, fig. 9).
Re: Claim 19, Banna and Park discloses all the limitations of claim 15 on which this claim depends. Banna further discloses: wherein a height of the dielectric structure (134 and 136, fig. 9, height wherein same level of the gate structure 102) is substantially equal to heights of the first and second gate structure (102, fig. 3)s.
Re: Claim 20, Banna and Park discloses all the limitations of claim 15 on which this claim depends. Banna further discloses: a top surface of the semiconductor fin (in recess 132 a top surface of 110, fig. 8) is level with top surface of dielectric structure (134/136, fig. 10)
Banna is silent regarding: wherein a top surface of the implantation region is level with a top surface of the semiconductor fin (in recess 132 a top surface of 110, fig. 8).
Park discloses the implantation region (122-124) is level with a top surface of the semiconductor fin (133).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an implantation region and isolation structure in the substrate between source and drain region since the implantation region with isolation layer between source/drain region can prevent the increase of a threshold voltage of the channel region formed adjacent to the sidewall of the trench and the stopper regions prevent surface depletions of the threshold voltage control regions adjacent to the sidewall and bottom face of the trench (column 17, lines 28-32; column 25, lines 59-64).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Mo US patent 6316806 B1”) Discloses a trench field-effect transistor with a self-aligned source. At least a portion of the source implantation dose is implanted underneath the gate of a trench transistor by implanting a non-orthogonal angle to the sidewall of the trench. In one embodiment, a slow diffuser, such as arsenic, is implanted to minimize the post-implant diffusion. The resulting structure ensures gate-source overlap, and a consistent, small, gate-source capacitance with a lower thermal budget for the resultant device. The narrow depth of the source, in conjunction with its unique L-shape, improves device ruggedness because the source doping does not compensate the heavy body doping as much as with conventional devices. In one embodiment, the substrate is rotated 180 degrees within the implanter to implant both sidewalls of a trench.
* (“Kim et al., US Patent 5278438 A”) discloses a nonvolatile storage device is provided with at least one stacked poly gate structure formed on the substrate and disposed between a first trench and a second trench. The trenches each having two walls. A first doped area having a first conductivity type extending along the wall of the first trench and a second doped area having a second conductivity type extending along the wall of the second trench. The first doped area and the second doped area having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto. The trench walls are lined with a metal silicide to decrease resistivity.
Allowable Subject Matter
Claims 1-3, 5-14 and 23-25 are allowed.
Re: Independent Claim 1 (and its dependent claim(s) 2, 3, 5-9, 24 and 25), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure, and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first epitaxy structures and bottom of the second epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to form a recess in the semiconductor fin; forming an implantation region in the substrate through the recess, wherein a first conductivity type of the implantation region is different from a second conductivity type of the substrate; and after forming the implantation region, forming an isolation structure in the recess, wherein a bottom of the isolation structure is lower than the bottom of the first epitaxy structures and the bottom of the second epitaxy structures, and wherein once the isolation structure is formed, the isolation structure interfaces with both the implantation region having the first conductivity type and the substrate having the second conductivity type.
Re: Independent Claim 10 (and its dependent claim(s) 11-14 and 23), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: forming first spacers on opposite sidewalls of the first gate structure, second spacers on opposite sidewalls of the second gate structure, and third spacers on opposite sidewalls of the third gate structure; forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure; removing the third gate structure to form a trench between the third spacers to expose a portion of the semiconductor fin; etching the portion of the semiconductor fin exposed by the trench between the third spacers; and forming a dielectric structure filling the trench between the third spacers, wherein the dielectric structure comprises a first dielectric embedded in the semiconductor fin and a second dielectric over a top surface of the first dielectric, the first dielectric having a first material composition interfaces with the semiconductor fin, the second dielectric having a second material composition forms interfaces with sidewalls of the third spacers, and the first material composition is different from the second material composition.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898