Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. This office action is in response to the filing with the office dated 04/01/2026.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on 02/11/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Reply to Applicant’s Arguments
4. Applicant’s arguments and claim amendments filed with the office on 04/01/2026 were fully considered and found to be non-persuasive. Regarding Applicant’s arguments about the newly amended/introduced limitation, wherein the first switch includes a first PMOS and the second switch includes a second PMOS, or the first switch includes a first NMOS and the second switch includes a second NMOS, Please see the 35 U.S.C. 112 rejection below. The instant specification does not have support in the specification. Hence Applicant’s arguments directed to newly amended claims/subject matter which is not part of the instant specification are moot.
Please see the rejection below for claims 1-6 rejected under 35 U.S.C. 103 as being unpatentable over Kinoshita (US 2002/0145442 A1), Wang et al (US 2010/0253382 A1) and in further view of Pan et al (US 2015/0042372 A1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Drawing Objection
5. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first switch includes a first PMOS and the second switch includes a second PMOS, or the first switch includes a first NMOS and the second switch includes a second NMOS” as recited in claims 1, 7, and 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections 35 U.S.C. 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
6. Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “An apparatus, comprising: …………………………….wherein the first switch includes a first PMOS and the second switch includes a second PMOS, or the first switch includes a first NMOS and the second switch includes a second NMOS”. The specification does not give any guidance or details about this first and second switch including a PMOS and NMOS.
Appropriate correction to the claim language is required.
6. Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Appropriate correction to the claim language is required.
7. Claims 2-5, 7 and 8 are rejected under 35 U.S.C. 112 (a) due to their dependency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
8. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “An apparatus, comprising: …………………………….wherein the first switch includes a first PMOS and the second switch includes a second PMOS, or the first switch includes a first NMOS and the second switch includes a second NMOS”. The specification does not give any guidance or details about this first and second switch including a PMOS and NMOS. In the absence of any guidance or details of the about this first and second switch including a PMOS and NMOS, it is not clear to one of the ordinary skill in the art, what is meant by this recitation or how it is implemented.
9. Claims 2-5, 7 and 8 are rejected under 35 U.S.C. 112 (b) due to their dependency.
Claim Rejections – 35 U.S.C. 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kinoshita (US 2002/0145442 A1), Wang et al (US 2010/0253382 A1) in further view of Pan et al (US 2015/0042372 A1).
Regarding independent claim 1, Kinoshita (US 2002/0145442 A1) teaches, an apparatus, comprising: a semiconductor wafer hosting rows and columns of chips (paragraph [0005]), where the rows and columns of chips are separated by scribe lines (paragraph [0005]); and selection circuitry positioned within the scribe lines, the selection circuitry connected to test circuits in the
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scribe lines (paragraph [0028]), the selection circuitry operating to enable voltage control at a single test circuit while disabling all other test circuits (The selection circuit may be a shift register 16 having a plurality (n stages are shown) of shift stages (16S1 to 16Sn), which
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controls the transmission gates 14 at the two ends of the elements 12 so as to sequentially select at least one element 12 at a time [0054]).
Kinoshita is silent about the limitation, wherein the selection circuitry includes at least one of a header switch and a footer switch for each test circuit, the at least one of the header switch and the footer switch including: a first switch that has a first end configured to be connected to a force pad of a source measurement unit and a second end connected to a first end of the test circuit; and a second switch that has a first end configured to be connected to a footer end of the source measurement unit and a second end connected to a second end of the test circuit.
Wang et al (US 2010/0253382 A1) teaches, wherein the selection circuitry includes at least one of a header switch and a footer switch for each test circuit, the at least one of the header switch and the footer switch (paragraphs [0046], [0047]) including : a first switch that has
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a first end configured to be connected to a force pad of a source measurement unit and a second end connected to a first end of the test circuit (figure 5, paragraphs [0046], [0047]); and a second switch that has a first end configured to be connected to a footer end of the source measurement unit and a second end connected to a second end of the test circuit (figure 5, paragraphs [0046], [0047]).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Kinoshita by providing a ring oscillator stage with header and footer circuit as taught by Wang et al (paragraphs [0046], [0047]).
One of the ordinary skill in the art would have been motivated to make such a modification to advantageously enable the observation of device threshold variations in an integrated circuit or wafer by virtue of making simple frequency measurements while enabling individual devices under test within the ring oscillator and the threshold voltages of the devices under test correlating to the observed oscillator frequencies, as taught by Wang et al (paragraph [0011]).
Kinoshita and Wang et al does not teach the amended limitation wherein the at least one of the header and footer switch each including a first and second switch.
Pan et al (US 2015/0042372 A1) teaches, an addressable test circuit used to measure key parameters of transistor (figures 4, paragraphs [0032], and a test method of an addressable test circuit for measuring the key parameters of MOS transistor, characterized in that, selecting one of the MOS transistors as the DUT through addressable circuit, and measuring its I.sub.dsat and I.sub.off respectively (in the present invention, the selected DUT by addressable circuit is abbreviated as SDUT, the unselected DUT is abbreviated as NDUT [0033], also see figure 5, For measuring saturation current I.sub.dsat, closing switch S.sub.DF, S.sub.DL, S.sub.SS, S.sub.SF which connect to SDUT, at the same time, unclosing S.sub.DF, S.sub.DL, S.sub.SS, S.sub.SF which connect to NDUT, the D end of the selected MOS transistor is applied voltage connection, the S end is induced voltage connection, and DF, SF belong to force end, DL, SS belong to sense end,
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giving a voltage to force end, at the same time, the voltage of D/S end can be detected through the sense end to judge whether it meets the measurement conditions, if not, adjusting the applied voltage to eliminate bad effects on the measurement, the effects are arose from the drop voltage of conduction resistance and line resistance, the saturation current I.sub.dsat is measured in DF end [0041]. For measuring subthreshold leakage current I.sub.off, closing switch S.sub.DL, S.sub.SF which connect to the selected MOS transistor and switch S.sub.DF, S.sub.SS which are connected to unselected MOS transistors, in the same time, unclosing S.sub.DF, S.sub.SS which connect to the selected MOS transistor and switch S.sub.DL, S.sub.SF which are connected to unselected MOS transistors, connecting the selected MOS transistor's D end to signal line DL, and the unselected MOS transistors' D end to signal line DF, this will reduce the effect on measurement caused by unselected MOS transistors' electric leakage; at the same time, the supply voltage of DF end is equal to DL end's supply voltage, to make sure the both sides of switch S.sub.DL which connect to signal line DL of unselected MOS transistor have no voltage drop, and reduce the effect caused by switch electric leakage on measurement, the subthreshold leakage current I.sub.off is measured in DL end [0042]. Switch S.sub.SF, like other switches, can use a transmission gate or a single MOS transistor [0043]; and figure 6 and [0044]-[0047]).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Kinoshita and Wang et al by providing an arrangement for testing DUT with two transistors in each header and footer switch as shown in figure 5 of Pan et al (paragraphs [0039], [0044]).
One of the ordinary skill in the art would have been motivated to make such a modification to advantageously enable the observation of device threshold variations in an integrated circuit or wafer by virtue of making simple frequency measurements while enabling individual devices under test within the ring oscillator and the threshold voltages of the devices under test correlating to the observed oscillator frequencies, as taught by Wang et al (paragraph [0011]).
Regarding dependent claim 2, Kinoshita (US 2002/0145442 A1), Wang et al (US 2010/0253382 A1) and Pan et al (US 2015/0042372 A1) teach the apparatus of claim 1.
Kinoshita further teaches, wherein the selection circuitry includes the header switch for each test circuit (The potential across both ends of each elements 122 is then measured by connecting the both ends to a pair of potential difference measurement lines Vi and {overscore (Vi)} (i=1 to 16) by switches (pass-transistors) 124 (paragraph [0046]); a plurality of switches 11; and a selection circuit. Each switch 11 is constructed with a pair of transmission gates 14 connected to the two ends of each element 12. Each transmission gate 14 is constructed with two pas-transistors, i.e., a PMOS transistor and an NMOS transistor. The selection circuit may be a shift register 16 having a plurality (n stages are shown) of shift stages (16S1 to 16Sn), which controls the transmission gates 14 at the two ends of the elements 12 so as to sequentially select at least one element 12 at a time (paragraph [0054]).
Wang also teaches wherein the selection circuitry includes the header switch for each test circuit ([0013] integrated circuitry disposed on a substrate, the integrated circuitry configured to perform defined operations; and at least one ring oscillator disposed on the substrate, the ring oscillator configured to produce a clock signal at a frequency dependent on a configuration of elements in the ring oscillator, the ring oscillator comprising a plurality of inverters serially arranged in a loop, each receiving a virtual positive voltage supply and a virtual ground voltage supply; a plurality of header test circuits corresponding to one of the plurality of inverters, each comprising a bypass transistor receiving an enable signal on a gate terminal and having a channel coupled between a positive voltage supply and the respective virtual voltage supply and each further comprising a header transistor under test having a channel coupled between the positive voltage and the respective virtual voltage supply. A plurality of footer test circuits are also provided, each corresponding to one of the plurality of inverters, each also comprising a bypass transistor receiving an enable signal on a gate terminal and having a channel coupled between a ground voltage supply and the respective virtual ground voltage supply, and each further comprising a footer transistor under test having a channel coupled between the ground voltage supply and the respective virtual ground voltage supply; wherein the frequency of oscillation of the ring oscillator may be affected by one of a header transistor under test and a footer transistor under test, responsive to the respective bypass transistor being disabled by the corresponding one of the enable signals).
Pan et al also teaches a header and footer switch for each test circuit as shown in figures 4-6 and described in paragraphs [0039]-[0047]).
Regarding dependent claim 3, Kinoshita (US 2002/0145442 A1), Wang et al (US 2010/0253382 A1) and Pan et al (US 2015/0042372 A1) teach the apparatus of claim 1.
Kinoshita further teaches wherein the selection circuitry includes the footer switch for each test circuit (The potential across both ends of each elements 122 is then measured by connecting the both ends to a pair of potential difference measurement lines Vi and {overscore (Vi)} (i=1 to 16) by switches (pass-transistors) 124 (paragraph [0046]); a plurality of switches 11; and a selection circuit. Each switch 11 is constructed with a pair of transmission gates 14 connected to the two ends of each element 12. Each transmission gate 14 is constructed with two pas-transistors, i.e., a PMOS transistor and an NMOS transistor. The selection circuit may be a shift register 16 having a plurality (n stages are shown) of shift stages (16S1 to 16Sn), which controls the transmission gates 14 at the two ends of the elements 12 so as to sequentially select at least one element 12 at a time (paragraph [0054]).
Wang also teaches wherein the selection circuitry includes the footer switch for each test circuit ([0013] integrated circuitry disposed on a substrate, the integrated circuitry configured to perform defined operations; and at least one ring oscillator disposed on the substrate, the ring oscillator configured to produce a clock signal at a frequency dependent on a configuration of elements in the ring oscillator, the ring oscillator comprising a plurality of inverters serially arranged in a loop, each receiving a virtual positive voltage supply and a virtual ground voltage supply; a plurality of header test circuits corresponding to one of the plurality of inverters, each comprising a bypass transistor receiving an enable signal on a gate terminal and having a channel coupled between a positive voltage supply and the respective virtual voltage supply and each further comprising a header transistor under test having a channel coupled between the positive voltage and the respective virtual voltage supply. A plurality of footer test circuits are also provided, each corresponding to one of the plurality of inverters, each also comprising a bypass transistor receiving an enable signal on a gate terminal and having a channel coupled between a ground voltage supply and the respective virtual ground voltage supply, and each further comprising a footer transistor under test having a channel coupled between the ground voltage supply and the respective virtual ground voltage supply; wherein the frequency of oscillation of the ring oscillator may be affected by one of a header transistor under test and a footer transistor under test, responsive to the respective bypass transistor being disabled by the corresponding one of the enable signals).
Pan et al also teaches a header and footer switch for each test circuit as shown in figures 4-6 and described in paragraphs [0039]-[0047]).
Regarding dependent claim 4, Kinoshita (US 2002/0145442 A1), Wang et al (US 2010/0253382 A1) and Pan et al (US 2015/0042372 A1) teach the apparatus of claim 1.
Kinoshita further teaches, the source measurement unit force and sense pads for each source management unit utilized in test equipment ([0056] In the test circuit 10 shown in FIG. 1, the elements 12 are connected in series so as to form two rows of chains CHi (i=1, 2), in each of which n elements 12 are connected. The two ends of the chain CHi are connected to a current source pad Ii (i=1, 2) and a current drain pad Iibar, respectively. Also see paragraph [0046]).
Regarding dependent claim 5, Kinoshita (US 2002/0145442 A1), Wang et al (US 2010/0253382 A1) and Pan et al (US 2015/0042372 A1) teach the apparatus of claim 1.
Kinoshita further teaches, a digital select pad to receive a control signal for the selection circuitry operating to enable voltage control at the single test circuit while disabling all other test circuits (The selection circuit may be a shift register 16 having a plurality (n stages are shown) of shift stages (16S1 to 16Sn), which controls the transmission gates 14 at the two ends of the elements 12 so as to sequentially select at least one element 12 at a time (paragraph [0054]. The shift register 16 is connected to a reset signal line RE leading to a reset signal pad RE_IN, so that each stage 16Sj of the shift register 16 can be put into an initial state by a reset signal from the reset signal line RE. As will be explained later, the clock signal and the reset signal are used as control signals to control the operation of the shift register 16 [0059]).
11. Regarding newly introduced claims 7 and 8, please see the 35 U.S.C. 112 rejections and drawing objections above. The 35 U.S.C. 112 issues and drawing objections severely impede the examination of claims 7 and 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURESH RAJAPUTRA whose telephone number is (571) 270-0477. The examiner can normally be reached between 8:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached on 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SURESH K RAJAPUTRA/Examiner, Art Unit 2858
06/13/2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 6/15/2026
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