Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/09/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching (Patent No.: US 9911824) in view of KIM (Pub. No.: US 2017/0092728).
Re claim 1, Ching, FIG. 5 teaches an integrated circuit structure, comprising:
a first fin comprising silicon (108d);
a second fin comprising silicon (108d’);
an insulating structure (110) between the first fin (108d) and the second fin (108d’);
a gate electrode (136) over the first fin (108d) and the second fin (108d’), the gate electrode having a first side opposite the second side;
a first epitaxial source or drain structure (126d) on the first fin (108d) at the first side of the gate electrode;
a second epitaxial source or drain structure (126d’) on the second fin (108d’) at the first side of the gate electrode;
a single dielectric material layer (128, col. 4, lines 23-37) on the insulating structure (110) and continuous between the first epitaxial source or drain structure (126d) and the second epitaxial source or drain structure (126d’), the single dielectric material layer(128) along a portion of a sidewall of the first fin and along a portion of a sidewall of the first epitaxial source or drain structure (126d), wherein the first epitaxial source or drain structure has a portion extending above the single dielectric material layer (128), and the single dielectric material layer along a portion of a sidewall of the second fin and along a portion of a sidewall of the second epitaxial source or drain structure (126d’), wherein the second epitaxial source or drain structure has a portion (top most portion of (126d’)) extending above the single dielectric material layer (128).
Re claim 5, Ching, FIG. 5 teaches an integrated circuit structure, comprising:
a first fin comprising silicon (108d);
a second fin comprising silicon (108d’);
an insulating structure (110) between the first fin and the second fin;
a first epitaxial source or drain structure (126d) on the first fin (108d), the first epitaxial source or drain structure and the first fin meeting at a first interface;
a second epitaxial source or drain structure (126d’) on the second fin (108d’), the second epitaxial source or drain structure and the second fin meeting at a second interface;
a dielectric single material layer (128, col. 4, lines 23-37) extending continuous from above the first interface but below a top of the first epitaxial source or drain structure (108d/108d’), along a portion of a sidewall of the first fin, on the insulating structure (110), along a portion of a sidewall of the second fin, to above the second interface but below a top of the second epitaxial source or drain structure.
Re claim 10, Ching, FIG. 5 teaches an integrated circuit structure, comprising:
a first fin comprising silicon (108d);
a second fin comprising silicon (108d’);
an insulating structure (110) between the first fin and the second fin;
a first source or drain structure (126d) on the first fin (108d), the first source or drain structure and the first fin meeting at a first interface, the first source or drain structure comprising silicon and germanium (col. 4, lines 20-22);
a second source or drain structure (126d’) on the second fin (108d’), the second source or drain structure and the second fin meeting at a second interface, the second source or drain structure comprising silicon and germanium ((col. 4, lines 20-22);
a single dielectric material layer (128, col. 4, lines 23-37) extending continuous from above the first interface but below a top of the first source or drain structure (108d/108d’), along a portion of a sidewall of the first fin, on the insulating structure (110), along a portion of a sidewall of the second fin, to above the second interface but below a top of the second source or drain structure.
In re Claims 1, 5 and 10, Ching fails to teach wherein the single dielectric material layer has a bottommost surface below a bottommost surface of the first epitaxial source or drain structure and below a bottommost surface of the second epitaxial source or drain structure; and the insulating structure having a non-planar top surface.
KIM teaches wherein the single dielectric material layer (40, FIG. 8, ¶ [0152]) has a bottommost surface below a bottommost surface of the first epitaxial source or drain structure (E1-E4, [0112]) and below a bottommost surface of the second epitaxial source or drain structure (E5-E8); and the insulating structure having a non-planar top surface (20, [0146]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of effectively suppress a short channel effect (SCE) in which the electric potential of the channel region is influenced by the drain voltage as taught by KIM, [0004].
Re claim 2, in the combination, KIM, FIG. 4 teaches the integrated circuit structure of claim 1, wherein the single dielectric material layer (20) is in contact with the portion of the sidewall of the first fin (F1) and is in contact with the portion of the sidewall of the second fin (F2).
Re claim 3, in the combination, Ching, FIG. 5 teaches the integrated circuit structure of claim 1, wherein the first epitaxial source or drain structure has a matchstick profile (126d).
Re claim 4, in the combination, Ching, FIG. 5 teaches the integrated circuit structure of claim 1, wherein the second epitaxial source or drain structure has a matchstick profile (126d’).
Re claim 6/11, in the combination, KIM, FIG. 4 teaches the integrated circuit structure of claim 5/10, wherein the single dielectric material layer (20) is directly on the portion of the sidewall of the first fin (F1), and wherein the single dielectric material layer is directly on the portion of the sidewall of the second fin (F2).
Re claim 7/12, in the combination, Ching, FIG. 5 teaches the integrated circuit structure of claim 5/10, wherein the first epitaxial source or drain structure (126d) extends laterally beyond the portion of the single dielectric material layer (128) along the portion of the sidewall of the first fin (108d), and wherein the second epitaxial source or drain structure (126d’) extends laterally beyond the portion of the single dielectric material layer (128) along the portion of the sidewall of the second fin (108d’).
Re claim 8/13, in the combination, Ching, FIG. 5 teaches the integrated circuit structure of claim 5/10, wherein the single dielectric material layer comprises silicon and nitrogen (128, [0031]).
Re claim 9/14, in the combination, Ching, FIG. 5 teaches the integrated circuit structure of claim 5/10, wherein the insulating structure comprises silicon and oxygen (110, [0024]).
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Patent No.: US 9847224) in view of Ching.
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Re claim 1, Kim, FIG. 31 [as shown above] teaches an integrated circuit structure, comprising:
a first fin comprising silicon (left 110/[FF], Fig. 31 [as shown above]);
a second fin comprising silicon (right 110/[SF]);
an insulating structure (120) between the first fin [FF] and the second fin [SF];
a gate electrode (272, Fig. 37) over the first fin [FF] and the second fin [SF], the gate electrode having a first side opposite the second side;
a first epitaxial source or drain structure (left 202/[FE]) on the first fin [FF] at the first side of the gate electrode;
a second epitaxial source or drain structure (right 202/[SE]) on the second fin [SF] at the first side of the gate electrode;
a dielectric material layer (167) on the insulating structure between the first epitaxial source or drain structure and the second epitaxial source or drain structure, the dielectric material layer (167) along a portion of a sidewall of the first fin [FF] and along a portion of a sidewall of the first epitaxial source or drain structure [FE], wherein the first epitaxial source or drain structure has a portion extending above the dielectric material layer (120), and the dielectric material layer along a portion of a sidewall of the second fin [SF] and along a portion of a sidewall of the second epitaxial source or drain structure [SE], wherein the second epitaxial source or drain structure has a portion (top most portion of 202) extending above the dielectric material layer (167); and wherein the dielectric material layer (167) has a bottommost surface below a bottommost surface of the first epitaxial source or drain structure [FE] and below a bottommost surface of the second epitaxial source or drain structure [SE].
Re claim 5, Kim, FIG. 31 [as shown above] teaches an integrated circuit structure, comprising:
a first fin comprising silicon [FF];
a second fin comprising silicon [SF];
an insulating structure (120) between the first fin and the second fin;
a first epitaxial source or drain structure [FE] on the first fin [FF], the first epitaxial source or drain structure and the first fin meeting at a first interface;
a second epitaxial source or drain structure [SE] on the second fin [SF], the second epitaxial source or drain structure and the second fin meeting at a second interface;
a dielectric material layer (167) extending continuous from above the first interface but below a top of the first epitaxial source or drain structure, along a portion of a sidewall of the first fin, on the insulating structure (120), along a portion of a sidewall of the second fin, to above the second interface but below a top of the second epitaxial source or drain structure, wherein the dielectric material layer (167) has a bottommost surface below a bottommost surface of the first epitaxial source or drain structure [FE] and below a bottommost surface of the second epitaxial source or drain structure [SE].
Re claim 10, Kim, FIG. 31 [as shown above] teaches an integrated circuit structure, comprising:
a first fin comprising silicon [FF];
a second fin comprising silicon [SF];
an insulating structure (120) between the first fin and the second fin;
a first source or drain structure [FE] on the first fin [FF], the first source or drain structure and the first fin meeting at a first interface, the first source or drain structure comprising silicon and germanium (refer to source/drain 420, Figs. 61 in different embodiment for silicon germanium material);
a second source or drain structure [SE] on the second fin [SF], the second source or drain structure and the second fin meeting at a second interface, the second source or drain structure comprising silicon and germanium (refer to source/drain 425, Figs. 61 in different embodiment for silicon germanium material);
a dielectric material layer (167) extending continuous from above the first interface but below a top of the first source or drain structure (top most portion of 202), along a portion of a sidewall of the first fin [FF], on the insulating structure (120), along a portion of a sidewall of the second fin [SF], to above the second interface but below a top of the second source or drain structure (top most portion of 202), and
wherein the dielectric material layer (167) has a bottommost surface below a bottommost surface of the first epitaxial source or drain structure [FE] and below a bottommost surface of the second epitaxial source or drain structure [SE].
In re Claims 1, 5 and 10, Kim fails to teach a single dielectric material layer on the insulating structure and continuous between the first epitaxial source or drain structure and the second epitaxial source or drain structure.
Ching teaches a single dielectric material layer (128, FIG. 5, col. 4, lines 23-37) on the insulating structure (110) and continuous between the first epitaxial source or drain structure (126d) and the second epitaxial source or drain structure (126d’).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the manufacturing process by ultilizing just one layer taught by Ching instead of multiple layers as taught by Kim.
Moreover, after the combining of Kim and Ching would teach wherein the single dielectric material layer has a bottommost surface below a bottommost surface of the first epitaxial source or drain structure and below a bottommost surface of the second epitaxial source or drain structure.
Moreover, Kim and Ching fail to teach the insulating structure having a non-planar top surface.
KIM teaches the insulating structure having a non-planar top surface (20, [0146]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of effectively suppress a short channel effect (SCE) in which the electric potential of the channel region is influenced by the drain voltage as taught by KIM, [0004].
Re claim 2, in the combination, Kim, FIG. 31 [as shown above] teaches the integrated circuit structure of claim 1, wherein the single dielectric material layer (167) is in contact with the portion of the sidewall of the first fin [FF] and is in contact with the portion of the sidewall of the second fin [SF].
Re claim 3, FIG. 31 [as shown above] Kim teaches the integrated circuit structure of claim 1, wherein the first epitaxial source or drain structure has a matchstick profile (left 202).
Re claim 4, Kim, FIG. 31 [as shown above] teaches the integrated circuit structure of claim 1, wherein the second epitaxial source or drain structure has a matchstick profile (right 202).
Re claim 6, in the combination, Kim, FIG. 31 [as shown above] teaches the integrated circuit structure of claim 5, wherein the single dielectric material layer (167) is directly on the portion of the sidewall of the first fin [FF], and wherein the single dielectric material layer is directly on the portion of the sidewall of the second fin [SF].
Re claim 7, in the combination, Kim, FIG. 31 [as shown above] teaches the integrated circuit structure of claim 5, wherein the first epitaxial source or drain structure [FE] extends laterally beyond the portion of the single dielectric material layer (167) along the portion of the sidewall of the first fin [FF], and wherein the second epitaxial source or drain structure [SE] extends laterally beyond the portion of the single dielectric material layer along the portion of the sidewall of the second fin [SF].
Re claim 11, Kim, FIG. 31 [as shown above] teaches the integrated circuit structure of claim 10, wherein the dielectric material layer (167) is directly on the portion of the sidewall of the first fin [FF], and wherein the dielectric material layer is directly on the portion of the sidewall of the second fin [SF].
Re claim 12, Kim, FIG. 31 [as shown above] teaches the integrated circuit structure of claim 10, wherein the first source or drain structure [FE] extends laterally beyond the portion of dielectric material layer (167) along the portion of the sidewall of the first fin [FF], and wherein the second source or drain structure [SE] extends laterally beyond the portion of dielectric material layer along the portion of the sidewall of the second fin [SF].
Re claim 8/13, in the combination, Ching, FIG. 5 teaches the integrated circuit structure of claim 5/10, wherein the single dielectric material layer comprises silicon and nitrogen (128, [0031]).
Re claim 9/14, in the combination, Ching, FIG. 5 teaches the integrated circuit structure of claim 5/10, wherein the insulating structure comprises silicon and oxygen (110, [0024]).
Response to Arguments
Applicant's arguments filed 09/09/2026 have been fully considered but they are not persuasive because KIM teaches the insulating structure having a non-planar top surface (20, [0146]).
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893
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