CTFR 17/849,207 CTFR 100612 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Status of the Application Claims 1-25 are pending in this application. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 and 11 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chen et al. (US 20210375627 A1) . Re Claim 1 Chen teaches a microelectronic device (FIG. 23) including: a substrate (2302) [0059]; a first structure (2300 minus 2302) [0059] on the substrate (2302), the first structure corresponding to a front end of line (FEOL) [0059] stack of the device and including a plurality of first transistors (2303) therein; and a second structure (2320 & 2340) [0061] on the substrate (2302), the second structure corresponding to a back end of line (BEOL) [0061] stack of the device, and including a plurality of second transistors (2343) therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material (1706, [0047] “…1706 can be formed using TMDs.”). Re Claim 11 Chen teaches the device of claim 1, wherein the BEOL stack (2320 & 2340) includes a plurality of electrically conductive structures (2324) that extend to individual corresponding ones of the second transistors (2343, FIG. 23) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210375627 A1) as applied to claim 1 above, and further in view of Or-Bach (US 20220181186 A1) . Re Claim 2 Chen teaches the device of claim 1, but does not teach the BEOL stack includes metallization layers, and individual ones of the second transistor are at a level of one or more the metallization layers of the BEOL stack. Or-Bach teaches the BEOL stack (see image below) includes metallization layers (6001-6020) [0366], and individual ones of the second transistor (transistors in 6024) [0366] are at a level of one or more the metallization layers (6010) of the BEOL stack (see image below). Modified FIG. 22 shown below with parts labeled PNG media_image1.png 450 402 media_image1.png Greyscale It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Or-Bach into the structure of Chen since Or-Bach teaches a CMOS semiconductor structure. The ordinary artisan would have been motivated to modify Or-Bach in combination with Chen in the above manner for the motivation of optimally integrating the metal layers to optimize the device’s current levels and in turn help reduce the impact of inter-chip interconnects. [0139] states, “Additionally there is a growing need to reduce the impact of inter-chip interconnects. In fact, interconnects may be now dominating IC performance and power. One solution to shorten interconnect may be to use a 3D IC.” 07-22-aia AIA Claim s 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210375627 A1) as applied to claim 1 above, and further in view of Yeom et al. (KR 20200103372 A) . Re Claim 3 Chen teaches the device of claim 1, but does not teach the TMD material includes a monolayer comprising a top atomic layer, a middle atomic layer and a bottom atomic layer, the top atomic layer and the bottom atomic layer including a chalcogenide, and the middle atomic layer including a transition metal. Yeom teaches the TMD material includes a monolayer (FIG. 3) comprising a top atomic layer, a middle atomic layer and a bottom atomic layer, the top atomic layer and the bottom atomic layer including a chalcogenide (S), and the middle atomic layer including a transition metal (Mo, page 5 last par states, “Referring to FIG. 3, a single MoS .sub.2 molecular layer has a structure in which an Mo atomic layer is disposed between a top S atomic layer and a bottom S atomic layer , and a multilayer MoS .sub.2 thin film has a structure in which such a single molecular layer is stacked.”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yeom into the structure of Chen since Yeom teaches a transistor containing a TMD. The ordinary artisan would have been motivated to modify Yeom in combination with Chen in the above manner for the motivation of forming a TMD layer with a top and bottom chalcogen with a transition metal between the top and bottom chalcogens to help the device exhibit excellent electrical and optical properties. Page 5 par 4 states, “In the photoelectric device according to the present invention, the transition metal dichalcogenide thin film 140 includes a plurality of regions forming a heterojunction by having different number of molecular layers extending in a direction apart from the first and second electrodes, It can exhibit excellent electrical and optical properties.” Re Claim 4 Chen in view of Yeom teaches the device of claim 3, wherein the chalcogenide includes one of S, Se or Te (Chen [0047] states, “In some embodiments, the chalcogen element can be one of sulfur, selenium, or tellurium. ”), and the transition metal includes one of Mo or W (Chen [0047] states, “For example, the transition metal element can be molybdenum or tungsten .”). Re Claim 5 Chen teaches the device of claim 1, the second transistors (2343) including respective channels ([0061] states, “2343 can include a channel region 2345”), wherein: the channels (1706 is part of 1801 in FIG. 23) of individual ones of the second transistors include the TMD material ([0061] states, “Portions of heterostacks 1801 can be used as channel regions for transistors 2343.”); Chen does not explicitly teach the TMD material in individual ones of said channels includes from 1 to 5 monolayers. Chen does teach the TMD material (1710 [0048], 1706 [0047], 1822 [0050]) in individual ones of said channels (2345) [0061] includes 3 monolayers (1810, FIG. 23) It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen into the structure of Chen. The ordinary artisan would have been motivated to modify Chen in combination with Chen in the above manner for the motivation of finding the optimal number of monolayers to use to form the channel region. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the ideal number of monolayers in the channel region. Chen does not teach individual ones of the monolayers comprise a top atomic layer, a middle atomic layer and a bottom atomic layer, the top atomic layer and the bottom atomic layer including a chalcogenide, and the middle atomic layer including a transition metal . Yeom teaches individual ones of the monolayers (FIG. 3) comprise a top atomic layer, a middle atomic layer and a bottom atomic layer, the top atomic layer and the bottom atomic layer including a chalcogenide (S), and the middle atomic layer including a transition metal (Mo, page 5 last par states, “Referring to FIG. 3, a single MoS .sub.2 molecular layer has a structure in which an Mo atomic layer is disposed between a top S atomic layer and a bottom S atomic layer , and a multilayer MoS .sub.2 thin film has a structure in which such a single molecular layer is stacked.”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yeom into the structure of Chen since Yeom teaches a transistor containing a TMD. The ordinary artisan would have been motivated to modify Yeom in combination with Chen in the above manner for the motivation of forming a TMD layer with a top and bottom chalcogen with a transition metal between the top and bottom chalcogens to help the device exhibit excellent electrical and optical properties. Page 5 par 4 states, “In the photoelectric device according to the present invention, the transition metal dichalcogenide thin film 140 includes a plurality of regions forming a heterojunction by having different number of molecular layers extending in a direction apart from the first and second electrodes, It can exhibit excellent electrical and optical properties.” 07-22-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210375627 A1) as applied to claim 1 above, and further in view of Mehandru et al. (US 20200227556 A1) . Re Claim 6 Chen teaches the device of claim 1, but does not teach the second transistors include negative metal oxide semiconductor (NMOS) transistors and positive metal oxide semiconductor (PMOS) transistors. Mehandru teaches the second transistors (330 and 350) [0033] include negative metal oxide semiconductor (NMOS) transistors and positive metal oxide semiconductor (PMOS) transistors ([0002] states, “In semiconductor processing, transistors are typically formed on semiconductor wafers. In CMOS (complimentary metal oxide semiconductor) technology, transistors usually belong to one of two types: NMOS (negative channel metal oxide semiconductor) or PMOS (positive channel metal oxide semiconductor) transistors.” [0012] states, “In various embodiments, apparatuses and methods relating to stressed transistors are described. Briefly, some embodiments variously promote channel stress to enhance the performance of one or more NMOS transistors and/or one or more PMOS transistors.”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Mehandru into the structure of Chen since Mehandru teaches a CMOS semiconductor structure. The ordinary artisan would have been motivated to modify Mehandru in combination with Chen in the above manner for the motivation of forming a CMOS device to allow the structure to obtain both tensile strain and compressive strain and function at a peak level. [0003] states, “Operation of such ICs depends at least in part on the performance of the transistors, which in turn can be improved by an imposition of strain in channel regions. Specifically, performance of a NMOS transistor is improved by providing a tensile strain in its channel region, and performance of a PMOS transistor is improved by providing a compressive strain in its channel region.” 07-22-aia AIA Claim s 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210375627 A1) in view of Mehandru et al. (US 20200227556 A1) as applied to claim 1 above, and further in view of Kim et al. (US 20160047059 A1) . Re Claim 7 Chen in view of Mehandru teaches the device of claim 6, but does not teach the NMOS transistors include Mo and S, and the PMOS transistors include W and Se. Kim teaches the NMOS transistors include Mo and S, and the PMOS transistors include W and Se ([0042] states, “obtaining a complementary metal oxide semiconductor (CMOS)-type structure comprising an N channel (such as MoS.sub.2, MoSe.sub.2 , MoTe.sub.2 etc.) metal oxide semiconductor (NMOS) and a P channel (such as WS.sub.2, WSe.sub.2 , WTe.sub.2 etc.) metal oxide semiconductor (PMOS) …”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Chen in view of Mehandru since Kim teaches a semiconductor structure with NMOS and PMOS transistors. The ordinary artisan would have been motivated to modify Kim in combination with Chen in view of Mehandru in the above manner for the motivation of using NMOS and PMOS formed with chalcogens to achieve a high growth speed. [0010] states, “Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a two-dimensional large-area growth method for a chalcogen compound exhibiting a high growth speed.” 07-22-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210375627 A1) as applied to claim 1 above, and further in view of Or-Bach (US 20220181186 A1) . Re Claim 8 Chen teaches the device of claim 1, but does not teach the second transistors form stacked rows of transistors. Or-Bach teaches the second transistors (6302) [0359] form stacked rows of transistors (FIG. 23A & D). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Or-Bach into the structure of Chen since Or-Bach teaches a CMOS semiconductor structure. The ordinary artisan would have been motivated to modify Or-Bach in combination with Chen in the above manner for the motivation of optimally integrating the second transistors to help reduce the impact of inter-chip interconnects. [0139] states, “Additionally there is a growing need to reduce the impact of inter-chip interconnects. In fact, interconnects may be now dominating IC performance and power. One solution to shorten interconnect may be to use a 3D IC.” 07-22-aia AIA Claim s 9-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210375627 A1) as applied to claim 1 above, and further in view of Chen et al. (US 20210134704 A1, Chen 2 hereafter) Re Claim 9 Chen teaches the device of claim 1, but does not teach including a back end, and a cluster of electrically conductive structures in the BEOL stack, the cluster to conduct an electrical signal a direction between the second transistors and the back end, the electrically conductive structures spaced more closely with respect to one another than a majority of other electrically conductive structures of the device that extend in the direction. Chen2 teaches a back end (170) [0035], and a cluster of electrically conductive structures (138) [0028] in the BEOL stack (140) [0032], the cluster (138) to conduct an electrical signal a direction between the second transistors (132, [0028] states, “The semiconductor substrate 132 may be a silicon substrate including active components (e.g., transistors or the like)…”) and the back end (170), the electrically conductive structures (138) spaced more closely with respect to one another than a majority of other electrically conductive structures (155 in 140) [0042] of the device that extend in the direction (FIG. 13). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen2 into the structure of Chen since Chen2 teaches a semiconductor structure with a back end structure integrated into the device. The ordinary artisan would have been motivated to modify Chen2 in combination with Chen in the above manner for the motivation of building a semiconductor device containing a back end layer to optimize the space within the device as semiconductor device size continues to scale down. [0002] states, “As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.” Re Claim 10 Chen in view of Chen2 teaches the device (Chen2 FIG. 13) of claim 1, wherein the BEOL stack (140) includes metallization layers (cross section of device in line with 140/136a and 140/134a), the device further including: a back end (170) [0035]; a power via (155) [0042] extending through the metallization layers in a direction between the FEOL stack (122/124 cross section) and the back end (170); and an electrically conductive structure (138) [0028] in the BEOL stack (140), the electrically conductive structure to conduct an electrical signal a direction between the second transistors (132) and the back end (170) and being at least as thick as the power via (155, 170 has a greater thickness for a vertical measurement compared to 155 thickness for a horizontal measurement). Modified Chen2 FIG. 13 shown below PNG media_image2.png 821 1275 media_image2.png Greyscale Re Claim 12 Chen in view of Chen2 teaches the device of claim 1, the device (Chen2 FIG. 13) further including a back end (170) [0035], wherein the BEOL stack (140) includes electrically conductive structures (138) [0028] extending directly from the second transistors (132) to the back end (170) of the device (FIG. 13) . 07-21-aia AIA Claim s 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 11073550 B1) and in view of Chen et al. (US 20210375627 A1) . Re Claim 13 Gong teaches a semiconductor package (FIG. 2), comprising: a package substrate (110, col 5 line 52); a die (204, col 5 line 26) on the package substrate (110) and electrically coupled thereto (connected by 114, 128, and 112, col 1 lines 55-67) Gong does not teach the die including: a substrate. a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the die and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the die, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. Chen teaches the die (FIG. 23) including: a substrate (2301) [0059], a first structure (2300 minus 2301 & 2302) [0058] on the substrate (2302), the first structure corresponding to a front end of line (FEOL) [0058] stack of the die and including a plurality of first transistors (2303) [0059] therein; and a second structure (2320 & 2340 [0061]) on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the die [0061], and including a plurality of second transistors (2343) [0061] therein, the plurality of second transistors including a transition metal dichalcogenide (1706) [0047] (TMD) material (FIG. 23). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen into the structure of Gong since Chen teaches a semiconductor structure with FEOL and BEOL structures integrated over the substrate. The ordinary artisan would have been motivated to modify Chen in combination with Gong in the above manner for the motivation of optimally integrating FEOL and BEOL stacks over a substrate to optimize the available space in a semiconductor device as device size continues to scale down. [0002] states, “With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices.” Re Claim 19 Gong teaches an integrated circuit (IC) device assembly (FIG. 2) including: a printed circuit board (col 1 line 59 states, “Solder balls 116 are utilized to mount a bottom surface 126 of the package substrate 110 to a printed circuit board (PCB) or test device not shown.”); a package substrate (110, col 1 line 54) on the printed circuit board and electrically coupled thereto; and a die (204, col 5 line 26) on the package substrate (110) and electrically coupled thereto (connected by 114, 128, and 112, col 1 lines 55-67), Gong does not teach the die including: a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the die and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the die, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. Chen teaches the die (FIG. 23) including: a substrate (2301) [0059], a first structure (2300 minus 2301 & 2302) [0058] on the substrate (2302), the first structure corresponding to a front end of line (FEOL) [0058] stack of the die and including a plurality of first transistors (2303) [0059] therein; and a second structure (2320 & 2340 [0061]) on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the die [0061], and including a plurality of second transistors (2343) [0061] therein, the plurality of second transistors including a transition metal dichalcogenide (1706) [0047] (TMD) material (FIG. 23). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen into the structure of Gong since Chen teaches a semiconductor structure with FEOL and BEOL structures integrated over the substrate. The ordinary artisan would have been motivated to modify Chen in combination with Gong in the above manner for the motivation of optimally integrating FEOL and BEOL stacks over a substrate to optimize the available space in a semiconductor device as device size continues to scale down. [0002] states, “With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices.” 07-22-aia AIA Claim s 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 11073550 B1) in view of Chen et al. (US 20210375627 A1) as applied to claim 13 above, and further in view of Chen et al. (US 20210134704 A1, Chen 2 hereafter) . Re Claim 14 Gong in view of Chen teaches the package of claim 13, but does not teach one or more inductors, the inductors electrically coupled to the second transistors. Chen2 teaches one or more inductors ([0028 states, “The semiconductor substrate 132 may be a silicon substrate including active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors , inductors, or the like) formed therein.”]), the inductors electrically coupled to the second transistors (FIG. 6, transistors and inductors are both in 132 which is silicon, so the inductors and transistors are electrically coupled together). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen2 into the structure of Gong in view of Chen since Chen2 teaches a semiconductor device with integrated transistors and inductors. The ordinary artisan would have been motivated to modify Chen2 in combination with Gong in view of Chen in the above manner for the motivation of integrating inductors to the device coupled to a transistor to optimize the available space in a semiconductor device as device size continues to scale down. [0002] states, “For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.” Re Claim 15 Gong in view of Chen and Chen2 teaches the package of claim 14, wherein the inductors are further coupled to corresponding terminals (Chen2 [0028] teaches inductors and transistors are both in silicon substrate 132, therefore the inductors are at least mechanically coupled to the transistor terminals). Re Claim 16 Gong in view of Chen and Chen2 teaches the package of claim 15, further including a capacitor (Chen2, 112, [0011] states, “The semiconductor substrate 112 may be a silicon substrate including active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors , inductors, or the like) formed therein.”) coupled at a terminal thereof to corresponding terminals of the second transistor (132, [0028] states, “The semiconductor substrate 132 may be a silicon substrate including active components (e.g., transistors or the like)…” The capacitors 112 and terminals of 132 are in the same device in FIG. 8 and are therefore mechanically coupled) . 07-22-aia AIA Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 11073550 B1) in view of Chen et al. (US 20210375627 A1) as applied to claim 13 above, and further in view of Or-Bach (US 20220181186 A1) . Re Claim 17 Gong in view of Chen teaches the package (Chen, FIG. 23) of claim 13, but does not teach the BEOL stack includes metallization layers, and individual ones of the second transistor are at a level of one or more the metallization layers of the BEOL stack. Or-Bach teaches the BEOL stack (see image below claim 2) includes metallization layers (6001-6020) [0366], and individual ones of the second transistor (transistors in 6024) [0366] are at a level of one or more the metallization layers (6010) of the BEOL stack (see image below claim 2). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Or-Bach into the structure of Gong in view of Chen since Or-Bach teaches a CMOS semiconductor structure. The ordinary artisan would have been motivated to modify Or-Bach in combination with Gong in view of Chen in the above manner for the motivation of optimally integrating the metal layers to optimize the device’s current levels and in turn help reduce the impact of inter-chip interconnects. [0139] states, “Additionally there is a growing need to reduce the impact of inter-chip interconnects. In fact, interconnects may be now dominating IC performance and power. One solution to shorten interconnect may be to use a 3D IC.” 07-22-aia AIA Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 11073550 B1) in view of Chen et al. (US 20210375627 A1) as applied to claim 13 above, and further in view of Yeom (KR 20200103372 A) . Re Claim 18 Gong in view of Chen teaches the package of claim 13, but does not teach the TMD material includes a monolayer comprising a top atomic layer, a middle atomic layer and a bottom atomic layer, the top atomic layer and the bottom atomic layer including a chalcogenide, and the middle atomic layer including a transition metal. Yeom teaches the TMD material includes a monolayer (FIG. 3) comprising a top atomic layer, a middle atomic layer and a bottom atomic layer, the top atomic layer and the bottom atomic layer including a chalcogenide (S), and the middle atomic layer including a transition metal (Mo, page 5 last par states, “Referring to FIG. 3, a single MoS .sub.2 molecular layer has a structure in which an Mo atomic layer is disposed between a top S atomic layer and a bottom S atomic layer , and a multilayer MoS .sub.2 thin film has a structure in which such a single molecular layer is stacked.”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yeom into the structure of Gong in view of Chen since Yeom teaches a transistor containing a TMD. The ordinary artisan would have been motivated to modify Yeom in combination with Gong in view of Chen in the above manner for the motivation of forming a TMD layer with a top and bottom chalcogen with a transition metal between the top and bottom chalcogens to help the device exhibit excellent electrical and optical properties. Page 5 par 4 states, “In the photoelectric device according to the present invention, the transition metal dichalcogenide thin film 140 includes a plurality of regions forming a heterojunction by having different number of molecular layers extending in a direction apart from the first and second electrodes, It can exhibit excellent electrical and optical properties.” 07-22-aia AIA Claim s 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 11073550 B1) in view of Chen et al. (US 20210375627 A1) as applied to claim 19 above, and further in view of Chen et al. (US 20210134704 A1, Chen 2 hereafter) . Re Claim 20 Gong in view of Chen teaches the IC device assembly of claim 19, but does not teach one or more inductors, the inductors electrically coupled to the second transistors. Chen2 teaches one or more inductors ([0028 states, “The semiconductor substrate 132 may be a silicon substrate including active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors , inductors, or the like) formed therein.”]), the inductors electrically coupled to the second transistors (FIG. 6, transistors and inductors are both in 132 which is silicon, so the inductors and transistors are electrically coupled together). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen2 into the structure of Gong in view of Chen since Chen2 teaches a semiconductor device with integrated transistors and inductors. The ordinary artisan would have been motivated to modify Chen2 in combination with Gong in view of Chen in the above manner for the motivation of integrating inductors to the device coupled to a transistor to optimize the available space in a semiconductor device as device size continues to scale down. [0002] states, “For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.” Re Claim 21 Gong in view of Chen and Chen2 teaches the IC device assembly of claim 20 wherein the inductors are further coupled to corresponding terminals of the second transistors (Chen2 [0028] teaches inductors and transistors are both in silicon substrate 132, therefore the inductors are at least mechanically coupled to the transistor terminals) . 07-22-aia AIA Claim s 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 11073550 B1) in view of Chen et al. (US 20210375627 A1) as applied to claim 19 above, and further in view of Zhong et al. (CN 114188224 A) . Re Claim 22 Gong in view of Chen teaches the IC device assembly of claim 19, but does not teach the second transistors include metal oxide semiconductor (MOS) transistors including at least one of dual gate transistors, trigate transistors, FinFET transistors, planar FET transistors, Gate All Around cylindrical transistors, tunneling FET (TFET) transistors, Square Wire transistors, or rectangular ribbon transistors. Zhong teaches the second transistors (page 14 last par states, “…a plurality of dual-gate transistor devices 130 may be formed…”) include metal oxide semiconductor (MOS) transistors including at least one of dual gate transistors (130, FIG. 1A), trigate transistors, FinFET transistors, planar FET transistors, Gate All Around cylindrical transistors, tunneling FET (TFET) transistors, Square Wire transistors, or rectangular ribbon transistors. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen2 into the structure of Gong in view of Chen since Chen2 teaches a semiconductor device with integrated transistors. The ordinary artisan would have been motivated to modify Chen2 in combination with Gong in view of Chen in the above manner for the motivation of integrating tri gate transistors to optimize the available space in the semiconductor structure as the industry continues to scale down device size. Page 2 par 1 states, “The semiconductor industry continuously increases the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, which allows the integration of more components into a given area.” Re Claim 23 Gong in view of Chen and Zhong teaches the IC device assembly of claim 22, wherein the second transistors further include dual gate transistors (multiple transistors can be integrated as explained in claim 22), individual ones of the dual gate transistors (130, page 5 par 6) including a top gate (118), a bottom gate (104), a first layer (108, page 10 par 1 states, “… 108 may have a k value greater than about 7.0, and may include Hf , Al, Zr, La, Mg, Ba, Ti, Pb and a metal oxide …”) adjacent the bottom gate (104) and including hafnium and oxygen, a second layer (102, page 9 par 3 states, “…102 is formed by the following materials or comprises the following materials: nitride, such as silicon nitride; oxides, such as silicon oxide …”) adjacent the first layer (108), the second layer (102) including oxygen and at least one of silicon and aluminum (FIG. 1A) . Response to Arguments 07-37 AIA Applicant's arguments filed 6/25/2026 have been fully considered but they are not persuasive. Re Claims 1 and 11 Applicant argues on page 14 line 19, “…the Chen reference fails to at least teach or suggest ‘a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material.’” The examiner respectfully disagrees because 2320 [0058] and 2340 [0061] are stacked directly on one another and can be considered a single structure as shown in FIG. 23. Claim 1 states, “…the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors…” Combining Chen 2320 and 2340 form a single structure containing (corresponding to) BEOL stack 2340 and a plurality of transistors 2343 [0061] satisfying the claim 1 limitations. Applicant argues on page 17 line 1, “Moreover, even under the Examiner's own mapping, vias 2324 in BEOL structure 2320 are described in [0060] of Chen as being "electrically and physically connected to source/drain contacts 2308 of FEOL structures 2300" -- that is, they extend to the silicon transistors 2303 in the FEOL, not to the 2D transistors 2343 in structure 2340. claim 11 therefore would not be anticipated even under the Examiner's reading of the reference.” The examiner respectfully disagrees as FIG. 23 shows parts of conductive structures 2324 [0060] are in direct contact with the bottom surface of the second transistors 2343 [0061]. Re Claim 2 Applicant argues on page 18 line 14, “…Or-Bach does not cure the deficiencies in Chen with respect to the feature of second transistors being at a level of one or more metallization layers of the BEOL stack.” The examiner respectfully disagrees as Or-Bach FIG. 22 (see modified Or-Bach FIG. 22 under claim 2 in 103 rejections) teaches 2 nd transistors at a vertical level with one metallization layer [0366] in what is identified as the BEOL stack. Re Claims 3-5 Applicant argues on page 20 line 2, “Yeom does not supply anything to the combination that is not already inherent in Chen itself.” The examiner respectfully disagrees as Yeom teaches a TMD material that’s a monolayer (FIG. 3) comprising a top atomic layer, a middle atomic layer and a bottom atomic layer. The top and bottom atomic layers include a chalcogenide (S), and the middle atomic layer includes a transition metal (Mo, page 5 last par) Re Claim 6 Applicant argues on page 21 line 13, “There is accordingly no rational basis to combine Mehandru with Chen to arrive at TMD- based NMOS and PMOS second transistors in a BEOL stack, and the proposed combination is based on hindsight.” The examiner respectfully disagrees as Mehandru FIG. 3A teaches second transistors (330 and 350) [0033] are in a structure comparable to what is the BEOL stack of Chen. Re Claim 7 Applicant argues on page 21 line 20 states, “However, Kim cannot cure the combined deficiencies of the Chen/Mehandru combination because, as argued above for claim 6, Mehandru's stressed-silicon FinFET approach cannot be meaningfully combined with Chen's 2D TMD architecture in the first instance.” The examiner respectfully disagrees as Kim teaches the NMOS transistors include Mo and S, and the PMOS transistors include W and Se ([0042] states, “obtaining a complementary metal oxide semiconductor (CMOS)-type structure comprising an N channel (such as MoS.sub.2, MoSe.sub.2, MoTe.sub.2 etc.) metal oxide semiconductor (NMOS) and a P channel (such as WS.sub.2, WSe.sub.2, WTe.sub.2 etc.) metal oxide semiconductor (PMOS)…”). Kim integrates transistors into its structure in a similar way Chen integrates transistors into its structure. Re Claim 8 Applicant argues on page 22 line 10, “…Or-Bach does not cure the deficiency in Chen with respect to the second transistors forming stacked rows.” The examiner respectfully disagrees as Or-Bach teaches second transistors (6302) [0359] form stacked rows of transistors as shown in FIG. 23A & D. Further, optimally integrating the second transistors would help reduce the impact of inter-chip interconnects. [0139] states, “Additionally there is a growing need to reduce the impact of inter-chip interconnects. In fact, interconnects may be now dominating IC performance and power. One solution to shorten interconnect may be to use a 3D IC.” Re Claims 9, 10, and 12 Applicant argues on page 23 line 7, “claim 9 recites a cluster of electrically conductive structures in the BEOL stack that are ‘spaced more closely with respect to one another than a majority of other electrically conductive structures of the device that extend in the direction.’ The Office Action maps this feature to the through-semiconductor vias (TSVs) 138 of Chen2 1[0028]. However, Chen2's TSVs 138 reside in the silicon semiconductor substrate 132 of Chen2's top tier die -- not in a BEOL stack. Chen2 [0028]. More critically, Chen2 nowhere describes any spatial density relationship among those vias.” The examiner respectfully disagrees as Chen2 132 is inside BEOL stack 140 [0032] in FIG. 13. FIG. 13 further shows two 155 [0042] parts in BEOL stack 140 and multiple conductive structures 138 [0028] in between the 155 parts. Therefore, one can conclude the electrically conductive structures (138) spaced more closely with respect to one another than a majority of other electrically conductive structures (155) as shown in FIG. 13. Applicant argues on page 23 line 16, “Claim 10 recites a power via extending through metallization layers with an electrically conductive structure in the BEOL stack that is ‘at least as thick as the power via.’ claim 12 recites electrically conductive structures ‘extending directly from the second transistors to the back end of the device.’ The Office Action maps these features to Chen2's through insulating vias (TIVs) 155 and redistribution circuit structure 170. But TIVs 155 in Chen2 are vias extending through an insulating encapsulation (a molding compound surrounding a semiconductor die), not through metallization layers of a BEOL stack. Chen2 1[0033]. Chen2 teaches no ‘power via’ as such, no thickness-comparison relationship between any conductive structure and a power via, and no conductive structures extending directly from second transistors to a back end -- Chen2's redistribution structure 170 connects to the tops of die 130 and TIVs 150 above the encapsulation, not from transistors in a BEOL stack directly to a backend. Chen2 [[[0035].” The examiner respectfully disagrees as Chen2 teaches 155 extending through a cross-sectional area of 140/134a which includes a metallization layer 134b [0028]. A modified FIG. 13 from Chen2 is shown under claim 10 for clarification. The thickness-comparison relationship between any conductive structure and a power via are based on the sizes as shown in FIG. 13. Using Chen2 FIG. 13 electrically conductive structure 138 [0028] has a larger thickness in a vertical direction than power via 155 [0042] thickness in a horizontal direction. Electrically conductive structure 138 electrically connects transistors in 132 which is silicon (132, [0028] states, “The semiconductor substrate 132 may be a silicon substrate including active components (e.g., transistors or the like)…”) and back end 170 [0035]. Re Claims 13 and 19 Applicant argues on page 24 line 12 “Assuming arguendo that Gong's package context is applicable and that Gong could be combined with Chen in the manner proposed, the combination of Gong and Chen does not teach ‘a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the die, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material.’” The examiner respectfully disagrees as Chen 2320 [0058] and 2340 [0061] are combined to form a single/second structure used as a BEOL stack, and the BEOL stack includes transistors 2343 [0061] including TMD materials [0048]. Applicant argues on page 25 line 9, “Gong has no teaching of, or relevance to, a die having a specific FEOL/BEOL/TMD transistor architecture of the type claimed. Using Gong as a starting point for the package/assembly context while grafting Chen's die architecture onto it requires a level of selective combination driven by hindsight, not by any teaching or suggestion in either reference.” The examiner respectfully disagrees as Gong and Chen both teach semiconductor devices containing multiple transistors and are considered to be analogous in the art. Re Claims 14-16 Applicant argues on page 26 line 4, “However, physical co-location of components within a silicon substrate does not establish electrical coupling between specific components in the manner required by the claim. The claim requires that the inductors be "electrically coupled to the second transistors" -- that is, to the particular second TMD transistors in the BEOL stack. Chen2's general statement that a silicon substrate may contain both transistors and passive components does not teach or suggest the specific electrical connection between inductors and TMD transistors in a BEOL stack that claim 14 requires.” The examiner respectfully disagrees because 132 is made of silicon and physically connecting the inductors inside of 132 and the transistors inside 132 are therefore electrically coupled ([0028 states, “The semiconductor substrate 132 may be a silicon substrate including active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors, inductors, or the like) formed therein.”]). Re Claim 17 Applicant argues on page 26 line 14, “Regarding claim 17, this claim depends from claim 13 and is allowable for at least the same reasons given above for independent claim 13, and further for the same reasons given above for claim 2 with respect to Or-Bach. Or-Bach does not cure the fundamental deficiency of Chen in failing to teach second TMD transistors within a BEOL stack.” The examiner respectfully disagrees because Gong in view of Chen teaches the second TMD transistors (Chen, 2343 [0061]) within a BEOL stack (2320 & 2340 [0061]), and Or-Back teaches metallization layers (6001-6020) [0366] and individual ones of the second transistor (transistors in 6024) [0366] are at a level of one or more the metallization layers (6010) of the BEOL stack. Re Claim 18 Applicant argues on page 26 line 19, “Regarding claim 18, this claim depends from claim 13 and is allowable for at least the same reasons given above for independent claim 13 and for claims 3-5.” The examiner respectfully disagrees because claims 3-5 and 13 remain rejected as explained above. Re Claims 20-21 Applicant argues on page 26 line 22, “Regarding claims 20 and 21, these claims depend from claim 19 and are allowable for at least the same reasons given above for independent claim 19, and further for the same reasons given above for claims 14 and 15 with respect to Chen2. claim 21, as amended, recites "The IC device assembly of claim 20" and is allowable at least for the reasons given for its parent claims.” The examiner respectfully disagrees because claims 14-15 and 19 remain rejected as explained above. Re Claims 22-23 Applicant argues on page27 line 13, “Zhong's teaching of a dual-gate and tri-gate transistor structure with two bottom gate electrodes does not supply this gate stack material configuration -- specifically, hafnium and oxygen in the first layer adjacent the bottom gate, and oxygen and at least one of silicon and aluminum in the second layer adjacent the first layer -- as recited in amended claim 23.” The examiner respectfully disagrees because after claim 23 was amended to no longer mention “a back gate”, claim 23 was remapped to Zhong FIG. 1A. 130 as shown in FIG. 1A comprises hafnium and oxygen in the first layer (108, page 10 par 1 states, “… 108 may have a k value greater than about 7.0, and may include Hf , Al, Zr, La, Mg, Ba, Ti, Pb and a metal oxide …”) which is adjacent to the bottom gate (104, page 5 par 6). The second layer (102, page 9 par 3 states, “…102 is formed by the following materials or comprises the following materials: nitride, such as silicon nitride; oxides, such as silicon oxide …”) is adjacent the first layer (108) and comprises oxygen and silicon . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lajoie et al. (US 20200411525 A1) teaches a microelectronic device comprising an FEOL stack, a BEOL stack, and a plurality of TMD transistors . THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENNETH MARK SIPLING/ Examiner, Art Unit 2818 /DUY T NGUYEN/ Primary Examiner, Art Unit 2818 9/1/26 Application/Control Number: 17/849,207 Page 2 Art Unit: 2818 Application/Control Number: 17/849,207 Page 3 Art Unit: 2818 Application/Control Number: 17/849,207 Page 4 Art Unit: 2818 Application/Control Number: 17/849,207 Page 5 Art Unit: 2818 Application/Control Number: 17/849,207 Page 6 Art Unit: 2818 Application/Control Number: 17/849,207 Page 7 Art Unit: 2818 Application/Control Number: 17/849,207 Page 8 Art Unit: 2818 Application/Control Number: 17/849,207 Page 9 Art Unit: 2818 Application/Control Number: 17/849,207 Page 10 Art Unit: 2818 Application/Control Number: 17/849,207 Page 11 Art Unit: 2818 Application/Control Number: 17/849,207 Page 12 Art Unit: 2818 Application/Control Number: 17/849,207 Page 13 Art Unit: 2818 Application/Control Number: 17/849,207 Page 14 Art Unit: 2818 Application/Control Number: 17/849,207 Page 15 Art Unit: 2818 Application/Control Number: 17/849,207 Page 16 Art Unit: 2818 Application/Control Number: 17/849,207 Page 17 Art Unit: 2818 Application/Control Number: 17/849,207 Page 18 Art Unit: 2818 Application/Control Number: 17/849,207 Page 19 Art Unit: 2818 Application/Control Number: 17/849,207 Page 20 Art Unit: 2818 Application/Control Number: 17/849,207 Page 21 Art Unit: 2818 Application/Control Number: 17/849,207 Page 22 Art Unit: 2818 Application/Control Number: 17/849,207 Page 23 Art Unit: 2818 Application/Control Number: 17/849,207 Page 24 Art Unit: 2818 Application/Control Number: 17/849,207 Page 25 Art Unit: 2818 Application/Control Number: 17/849,207 Page 26 Art Unit: 2818 Application/Control Number: 17/849,207 Page 27 Art Unit: 2818 Application/Control Number: 17/849,207 Page 28 Art Unit: 2818 Application/Control Number: 17/849,207 Page 29 Art Unit: 2818
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