Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,2-4,16,29,32,35,39,40,43 are rejected under U.S.C. 102(a)(1) as being anticipated by Fuergut et al. (U.S. Publication 20220157682)
Regarding Claim 1, Fuergut teaches the semiconductor package comprising;
a housing (Fig. 3 housing 114); a first contact (Fig. 11 first contact can be considered upper or lower conductive layers 106, see drawing below and [0136] disclosing using DCB substrate) within the housing (114) at a top side of the housing (fig. 11 contact carrier substrate 106 located at the top of the housing 114), the first contact (106) included in a thermal transfer path for the top-side cooled semiconductor package ([0106]-[0107], state contact 106 is thermally coupled to the sink 104 as part of the thermal transfer path); a semiconductor die (Fig. 11 semiconductor device die 108) within the housing below the first contact (Fig. 11 die 108 is below the first contact 106), the semiconductor die (108) comprising a contact pad (Fig. 3 pads 170) at a first side of the semiconductor die (108); a second contact within the housing at a bottom side of the housing (Fig. 11, contact 110 part of lead groups 138,140) ; an electrical connector operably connecting the second contact to the contact pad of the semiconductor die (Fig. 11, connector 168 contacts the second contact 110 with, pad 170 from Fig. 3, on die 108 ); and a creepage extension structure that extends into a side of the housing (Fig. 26 and [0161] disclose an indentation 143 as a creepage extender to increase creepage distance), the creepage extension structure comprising one or more trenches (Fig. 26, indentation 143 are trenched into the side of housing 114.)
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Regarding Claim 2, Fuergut teaches the semiconductor package of claim 1, and further discloses wherein: the contact pad is a first contact pad; (Fig. 11 first contact pad would inherently be there to contact to connector 168)
the semiconductor die (Fig. 11 die 108) further comprises a second contact pad at a second side of the semiconductor die;(Fig. 11, die 108 would inherently need a second contact pad to connect to 106 conductive layer)
and the first contact (first contact, bottom conductive layer of 106 based on language of claim 2) is operably connected to the second contact pad of the semiconductor die. (Fig. 11 shows first contact 106 would be connected to the top of the die 108)
Regarding Claim 3, Fuergut teaches the semiconductor package of claim 2, and further discloses wherein: the semiconductor die includes a diode; the first contact pad is a first terminal contact pad operably connected to a first terminal of the diode; and the second contact pad is a second terminal contact pad operably connected to a second terminal of the diode. (Fuergut teaches within [0156] and Fig. 18, the combining a diode with a transistor and K1 is operably connected to the diode through the transistor when it is on.
Regarding Claim 4, Fuergut teaches the semiconductor package of claim 2, and further discloses wherein: the semiconductor die includes a transistor; the first contact pad is a first terminal contact pad operably connected to a first terminal of the transistor; the second contact pad is a second terminal contact pad operably connected to a second terminal of the transistor; and the semiconductor die further comprises a third terminal contact pad at the first side of the semiconductor die, the third terminal contact pad operably connected to a third terminal of the transistor. (Fuergut teaches within [0156] and Fig. 11, the use of a transistor within the circuit package and Fig. 11 the die 108 using three contact leads from the die, a first terminal, second terminal, and a third terminal lead that would inherently be connected to corresponding pads from the die. Refer to Drawing 1 below)
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Drawing 1
Regarding Claim 16, Fuergut teaches the semiconductor package system, comprising: a top-side cooled semiconductor package, the top-side cooled semiconductor package comprising a housing having a top side and a bottom side (Fig. 11, housing 114 having a top and bottom side); a heat sink (Fig. 3 heat sink 160) operably connected to the top side of the housing (Fig. 3 heat sink 160 located on the top side of housing 114); and a circuit board operably connected to the bottom side of the housing (Fig. 3 and [0108], disclose circuit board 102 that contains a semiconductor package 100 that is operably mounted onto circuit board 102), wherein the top-side cooled semiconductor package comprises: a first contact within the housing at the top side of the housing (Fig. 11, first contact 106), the first contact and the heat sink included in a thermal transfer path for the top-side cooled semiconductor package ([0106]-[0107], state contact 106 is thermally coupled to the sink 104 as part of the thermal transfer path); a semiconductor die within the housing below the first contact (Fig. 11 die 108 is below the first contact 106), the semiconductor die comprising a contact pad at a first side of the semiconductor die (Fig. 3 pads 170); a second contact within the housing at a bottom side of the housing (Fig. 11, the second contact 110 facing the bottom side of housing 114); an electrical connector operably connecting the second contact to the contact pad of the semiconductor die (Fig. 3, connector 168 contacts the second contact 110 with pad 170 on die 108); and a creepage extension structure that extends into at least one side of the housing (Fig. 26 and [0161] disclose an indentation 143 as a creepage extender to increase creepage distance), the creepage extension structure comprising one or more trenches (Fig. 26, indentation 143 are trenched into the side of housing 114.)
Regarding Claim 29, Fuergut teaches the semiconductor package claim 16, and further discloses, further comprising an interface material between the heat sink and the top side of the housing. ([0126] and Fig. 9, disclose using a thermal interface material 154 between the heat sink 104 and housing 114)
Regarding Claim 32, Fuergut teaches a semiconductor package, comprising: a housing;
a first contact (Fig. 11 first contact 106 from drawing in claim 1) within the housing (Fig. 11 housing 114) at a top side of the housing (Fig. 11 shows contact 106 at the top of package for the top side of the housing 114);
a semiconductor die (Fig. 11 die component 108) within the housing below the first contact (Fig. 11 die 108 is within housing 114 and is below first contact 106),
the semiconductor die (108) comprising a contact pad (Fig. 11 inherent contact pad between 106 and die 108) at a first side of the semiconductor die (Fig. 11 there would inherently be a contact pad to connect die 108 to contact 106 from claim 1);
a power substrate (Fig. 11 and [0136] disclosing power substrate being the layered DCB substrate structure of 106) within the housing (power substrate 106 in housing 114) between the first contact and a second side of the semiconductor die (Fig. 11 first contact as upper conductive layer of 106 as part of the DCB power substrate is in-between the upper conductor and die 108),
the first contact (upper layer of 106) and the power substrate (combined layers of 106) included in a thermal transfer path of the top-side cooled semiconductor package (Figs. 11 and 12 show the thermal transfer path including the first contact 106 and multi-layer power substrate 106 connecting to heat sink 104);
a second contact (Fig. 11 second contact 110 of lead groups 138,140 below die 108) within the housing at a bottom side of the housing (Fig. 11 second contact 110 below die 108);
and an electrical connector (Fig. 11 connector 168 below die 108) operably connecting the second contact to the contact pad of the semiconductor die (Fig. 11 shows die 108 would inherently need contact pad to be attached to connector 168 connecting second contact lead 110).
Regarding Claim 35, Fuergut teaches a semiconductor package of claim 32, further comprising a creepage extension structure that extends into at least one side of the housing (Fig. 26 and [0161] disclose an indentation 143 as a creepage extender to increase creepage distance), the creepage extension structure comprising one or more trenches. (Fig. 26, indentation 143 are trenched into the side of housing 114.)
Regarding Claim 39, Fuergut teaches a semiconductor package, comprising:
a housing;(Fig. 11 housing 114)
a first contact within the housing at a top side of the housing, (Fig. 11 first contact can be considered upper or lower conductive layers 106, see drawing from claim 1 and [0136] disclosing using DCB substrate)
the first contact (106, bottom conductive layer 106) included in a thermal transfer path of the top-side cooled semiconductor package; ([0106]-[0107], discloses upper conductive contact 106 is thermally coupled to the sink 104 as part of the thermal transfer path)
a semiconductor die (die 108) within the housing (114) below the first contact, (Fig. 11 shows die 108 below first contact 106, bottom layer of 106)
the semiconductor die (die 108) comprising a first contact pad at a first side (top) of the semiconductor die that is operably connected to the first contact and a second contact pad at a second side (bottom) of the semiconductor die; (Fig 11 shows that it would inherently need a top contact pad on die 108 to connect to first contact 106 (bottom conductive layer 106) and die 108 would inherently have a bottom contact pad to connect to connector 168 under die 108)
a second contact within the housing at a bottom side of the housing; . (Fig. 11, second contact 110 of lead group 138,140 below die 108)
and an electrical connector operably connecting the second contact to the second contact pad of the semiconductor die. (Fig. 11, the second contact 110 connected through connector 168 to the bottom contact pad of die 108)
Regarding Claim 40, Fuergut teaches the semiconductor package of claim 39, and further discloses, further comprising a creepage extension structure that extends into at least one side of the housing (Fig. 26 and [0161] disclose an indentation 143 as a creepage extender to increase creepage distance that extends into at least one side of the housing), the creepage extension structure comprising one or more trenches. (Fig. 26, indentation 143 are trenched into the side of housing 114.)
Regarding Claim 43, Fuergut teaches the semiconductor package of claim 39, and further discloses, further comprising a second electrical connector operably connected to the first contact. (Fig. 11, second electrical connector 110 operably connected to first contact 106, bottom conductive layer of 106)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 are rejected under U.S.C. 103 as being unpatentable over Fuergut et al. in view of Kwon (U.S. Publication 20190348340).
Regarding Claim 17, Fuergut teaches the semiconductor package system of claim 16, and further discloses wherein: the top-side cooled semiconductor package (Fig. 11 package 108) is operably connected to a first side of the circuit board; (Fig. 11 shows package 108 operably connected to the first side of circuit board 106)
Fuergut does fails to teach the system further comprises an electronic component operably attached to a second side of the circuit board. However, Kwon does teach the system further comprises an electronic component (Fig. 5A chip component 820) operably attached to a second side of the circuit board (Fig. 5A shows chip component 820 on the second side of circuit board 1000). It would have been obvious to a person of skill in the art at the time of the effective filing date to have a component package under the circuit board from Kwon under the circuit board and be operably connected to improve integration of chip devices within a given surface area.
Claims 5-7,18,21,23,39,40,43 are rejected under U.S.C. 103 as being unpatentable over Fuergut et al. in view of Otremba et al. (U.S. Publication 20130161801).
Regarding Claim 5, Fuergut teaches the semiconductor package of claim 1, but fails to disclose further comprising a power substate between the first contact and the semiconductor die. However, Otremba does teach a power substate between the first contact and the semiconductor die. (Fig. 4 power substrate 21 is between first contact 26 and semiconductor die 100). It would have been obvious to a person of skill in the art at the time of the effective filing date that using a power substrate of Otremba between the first contact and die of Fuergut to a seamless integration of copper layers onto ceramic substrates, enhancing thermal conductivity and mechanical stability of the die package of Fuergut.)
Regarding Claim 6, Fuergut in view of Otremba teaches the semiconductor package of claim 5, but fails to disclose wherein the power substrate comprises an insulating layer between a top conductive layer and a bottom conductive layer. However, Otremba teaches in Fig. 2A that power substrate 21 comprises a ceramic insulator 22 in-between a top conductor 24 and bottom conductor 23. It would have been obvious to a person of skill in the art at the time of the effective filing date that using the DCB power substrate layers with insulator in-between two conductive layers of Otremba with the carrier substrate of Fuergut to electrically insulate between the top and bottom connectors and distribute electrical connection to the semiconductor die package.
Regarding Claim 7, Fuergut in view of Otremba teaches the semiconductor package of claim 6, and further teaches;
wherein the power substrate is a direct bond copper substrate. (Otremba does teach within [0119], a DCB substrate as a power substrate)
Regarding Claim 18, Fuergut teaches the semiconductor package of claim 16, but fails to disclose wherein: the contact pad is a first contact pad; the semiconductor die further comprising a second contact pad at a second side of the semiconductor die; and the first contact is operably connected to the second contact pad of the semiconductor die. However, Otremba teaches the contact pad is a first contact pad (Fig 4, first contact pad 120) ; the semiconductor die further comprises a second contact pad at a second side of the semiconductor die (Fig 4, second contact pad 110); and the first contact is operably connected to the second contact pad of the semiconductor die (Fig. 4, shows the semiconductor device die 100 with second contact pad 120 connected to first contact 160). It would have been obvious to a person of skill in the art at the time of the effective filing date that using a power substrate of Otremba between the first contact and die of Fuergut to a seamless integration of copper layers onto ceramic substrates, enhancing thermal conductivity and mechanical stability of the die package of Fuergut.)
Regarding Claim 21, Fuergut teaches the semiconductor package claim 16, but fails to disclose, wherein the top-side cooled semiconductor package further comprises a power substate positioned between the first contact and the semiconductor die. However, Otremba teaches the top-side cooled semiconductor package further comprises a power substate positioned between the first contact and the semiconductor die . (Fig. 4 power substrate 21 is between first contact 26 and semiconductor die 100). It would have been obvious to a person of skill in the art at the time of the effective filing date that using a power substrate of Otremba between the first contact and die of Fuergut to a seamless integration of copper layers onto ceramic substrates, enhancing thermal conductivity and mechanical stability of the die package of Fuergut.)
Claims 11 are rejected under U.S.C. 103 as being unpatentable over Fuergut et al. in view of Otremba et al. further in view of McPherson (U.S. Publication 20210313243)
Regarding Claim 11, Fuergut in view of Otremba teaches the semiconductor package of claim 10, but fails to disclose further comprising;
a fourth electrical connector operably connecting a kelvin pin on the bottom side of the housing to the source contact pad of the semiconductor die. However, McPherson does disclose within [0100] to use a separate fourth pin assembly K2 and a source-Kelvin pin toward the bottom of the housing in operable conjunction with the source contact to create a true source-kelvin implantation. It would have been obvious to a person of skill in the art at the time of the effective filing date that using the source-kelvin pins K2 from McPherson with the K2 from Fig. 15 of Fuergut to show using separate kelvin pin using a separate source signal path from the power source to improve switching performance [0098] from McPherson)
Claims 15 are rejected under U.S.C. 103 as being unpatentable over Fuergut et al. in view of Otremba et al. further in view of Otremba2 (U.S. Publication 20190080973)
Regarding Claim 15, Fuergut in view of Otremba teaches the semiconductor package of claim 1, but fails to disclose;
wherein the top-side cooled semiconductor package is a leadless top-side cooled semiconductor package. However, Otremba2 discloses using a package of lead-less design within [0048]. Otremba2 also discloses within [0075] to have a creepage extension length for a TSC (Top Side Cooling) SMD package as well. It would have been obvious to a person of skill in the art at the time of the effective filing date that the use of a lead-less SMD-TSC package with creepage extension from Otremba2 to be used instead of a lead frame package of Fuergut to provide a smaller footprint for the chip package and improve integration)
Claims 12-14,27 are rejected under U.S.C. 103 as being unpatentable over Fuergut et al. in view of Cole et al. (U.S. Publication 20170112005)
Regarding Claim 12, Fuergut teaches the package of claim 1 and further teaches: wherein the side of the housing is the top side of the housing; (Fig. 12 shows that the side of housing 114 has a top side of the housing for the cool package). Fuergut fails to teach the creepage extension structure provides a creepage distance between a pin or a lead and the first contact that is in a range from twelve millimeters (mm) to twenty mm. However, Cole teaches based on values being calculated to meet standards based on size and power requirements, wherein the creepage extension structure provides a creepage distance between a pin or a lead and the first contact (Fig. 2 and paragraph [0017]). It would have been obvious to a person of skill in the art at the time of the effective filing date to teach that a person of skill in the art would have a creepage extension in the range from twelve millimeters (mm) to twenty mm through by routine calculation or experimentation to satisfy the creepage distance requirements for various applications and the results effective variable based on power conditions and size of the chip. MPEP 2144.05(II)(A)
Regarding Claim 13, Fuergut teaches the package of package of claim 12, and further discloses wherein the creepage extension structure includes at least one trench that further extends into at least one peripheral side of the housing. (Fig. 9 and paragraph [0117], showing a creepage extension structure steps 130, 132 that are at least has a trench that extends into the side of the peripheral housing 114)
Regarding Claim 14, Fuergut teaches the package of claim 1, but fails to teach wherein the creepage extension structure provides a creepage distance that is in a range from five millimeters (mm) to fifteen mm or in a range from three mm to ten mm. However, Cole teaches based on values being calculated to meet standards based on size and power requirements, wherein the creepage extension structure provides a creepage distance within a certain range. (Fig. 2 and paragraph [0017], ) It would have been obvious to a person of skill in the art at the time of the effective filing date to teach that a person of skill in the art would have a creepage extension in a range from five millimeters (mm) to fifteen mm or in a range from three mm to ten mm through routine calculation or experimentation to satisfy the creepage distance requirements for various applications and the results effective variable based on power conditions and size of the chip. MPEP 2144.05(II)(A)
Regarding Claim 27, Fuergut teaches the package of claim 1 and further teaches: wherein the side of the housing is the top side of the housing; (Fig. 12 shows that the side of housing 114 has a top side of the housing for the cool package). Fuergut fails to teach the creepage extension structure provides a creepage distance between a pin or a lead and the first contact that is in a range from five millimeters (mm) to twenty mm. However, Cole teaches based on values being calculated to meet standards based on size and power requirements, wherein the creepage extension structure provides a creepage distance between a pin or a lead and the first contact (Fig. 2 and paragraph [0017]) It would have been obvious to a person of skill in the art at the time of the effective filing date to teach that a person of skill in the art would have a creepage extension in a range from five millimeters (mm) to twenty mm through routine calculation or experimentation to satisfy the creepage distance requirements for various applications and the results effective variable based on power conditions and size of the chip. MPEP 2144.05(II)(A)
Allowable Subject Matter
Claims 8-11,23,34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art, alone or in combination, fails to teach or suggest: wherein: the electrical connector is a first electrical connector; the contact pad is a first contact pad; the semiconductor die comprises a second contact pad at a second side of the semiconductor die, the second contact pad operably connected to the bottom conductive layer of the power substrate; and the top-side cooled semiconductor package further comprises: a third contact within the housing at the bottom side of the housing; and a second electrical connector operably connecting the third contact to the bottom conductive layer of the power substrate.
Regarding claim 9 is objected to by its dependency upon claim 8
Regarding claim 10 is objected to by its dependency upon claim 8
Regarding claim 11 is objected to by its dependency upon claim 10
Regarding claim 23, the prior art, alone or in combination, fails to teach or suggest: wherein: the electrical connector is a first electrical connector; the contact pad is a first contact pad; the semiconductor die further comprises a second contact pad at a second side of the semiconductor die, the second contact pad operably connected to a second conductive layer of the power substrate; and the top-side cooled semiconductor package further comprises: a third contact within the housing at the bottom side of the housing; and a second electrical connector operably connecting the third contact to the second conductive layer of the power substrate.
Regarding claim 34, the prior art, alone or in combination, fails to teach or suggest: wherein: the electrical connector is a first electrical connector; the contact pad is a first contact pad; the semiconductor die comprises a second contact pad at the second side of the semiconductor die; the second conductive layer is operably connected to the second contact pad; and the top-side cooled semiconductor package further comprises: a third contact within the housing at the bottom side of the housing; and a second electrical connector operably connecting the third contact to a conductive layer such that the third contact is operably connected to the second contact pad of the semiconductor die.
Conclusion
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/STEPHEN MICHAEL VOORHIS/Examiner, Art Unit 2899
/EVAN G CLINTON/Primary Examiner, Art Unit 2899
Prosecution Insights