DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 1/15/2026, has been entered. The Applicant has amended claims 1-6 and 12-20. Claims 7-11 were previously withdrawn per response dated on 10/6/2025 due to restriction requirement. Accordingly, claims 1-6 and 12-20 remain pending in the application.
Applicant’s amendments to the title and claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 11/7/ 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/4/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu (US 2022/0302275 A1).
Regarding claim 1, Yu teaches a semiconductor structure (semiconductor device structure 100, Fig. 31, [0079]) comprising:
a common substrate (substrate 101, Fig. 31, [0091]);
a forksheet complementary metal oxide semiconductor (CMOS) device (comprising fin structures 112b and 112c ([0029]), labeled as forksheet transistor in Illustrative Fig. 1, which is an annotated version of Fig. 31; [0022]: “The semiconductor device structure 100 may include a nanosheet transistor and/or a forksheet transistor. The nanosheet transistors may be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode surrounding the channels.”, and [0016]: “While the embodiments of this disclosure are discussed with respect to nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In cases where gate all around (GAA) transistor structures are adapted, the GAA transistor structures may be patterned by any suitable method.”) that is located on the common substrate (substrate 101, Illustrative Fig. 1), the forksheet CMOS device (forksheet transistor, Illustrative Fig. 1) including:
PNG
media_image1.png
845
1082
media_image1.png
Greyscale
an nFET (n-doped Field Effect Transistor) (comprising fin structure 112b, labeled as nFET in Illustrative Fig. 1, [0055]: “the devices on the fin structures 112a and 112c may be designed for p-channel FETs and the devices on the fin structure 112b may be designed for n-channel FETs, or vice versa.”);
a pFET (p-doped Field Effect Transistor) (comprising fin structure 112c, labeled as pFET in Illustrative Fig. 1, [0055]); and
a dielectric pillar (first dielectric feature 130, Illustrative Fig. 1, [0059]) separating the nFET (nFET, Illustrative Fig. 1) from the pFET (pFET, Illustrative Fig. 1);
a metallic shared gate connector (metal layer 186, Illustrative Fig. 1, [0079]: “In the embodiment shown in FIG. 31, since a portion of the first gate electrode layer 182 is in contact with the second gate electrode layer 184, the signal can be provided to both first and second gate electrode layers 182, 184 via the metal layer 186.”) that bridges gate stacks (first gate electrode layer 182 and second gate electrode layer 184, Illustrative Fig. 1, [0079]) of the nFET (nFET, Illustrative Fig. 1) and pFET (pFET, Illustrative Fig. 1) across the dielectric pillar; and
a gate-all-around (GAA) nanosheet CMOS device (comprising fin structure 11a, labeled as GAA transistor in Illustrative Fig. 1, [0055]) that is located on the common substrate (substrate 101, Illustrative Fig. 1) and is adjacent to the forksheet CMOS device (forksheet transistor, Illustrative Fig. 1).
Regarding claim 2, Yu teaches the structure of claim 1, wherein the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1) is not more than 35 nm thick (Figs. 4-6: the distance D2 is equal to the thickness of the first dielectric feature 130, which is in a range from about 3 nm to about 30 nm ([0033])).
Regarding claim 4, Yu teaches the structure of claim 1, further comprising additional CMOS devices (comprising first, second and third transistor regions 211, 212, and 213 in cell 210 in the layout diagram 200, Fig. 35, [0087]-[0088]), wherein a space (see spaces as labeled in Illustrative Fig. 2, which is an annotated version of Fig. 35) between active regions (active regions 217, 218, 219, Illustrative Fig. 2, [0087]-[0088]) of adjacent pFETs or nFETs of adjacent CMOS devices (transistors in first, second and third transistor regions 211, 212, and 213 in cell 210, Illustrative Fig. 2, [0087]-[0088]) is greater than a thickness of a thickest dielectric pillar (dielectric pillars are as dielectric feature 225, see dielectric pillar in Illustrative Fig. 2, [0087]: “dielectric feature 225, such as the dielectric feature 130 shown in FIG. 31, is formed between and coupled to two adjacent fin structures in the active regions 217, 218, 219 to form forksheet transistors.”) in the CMOS devices (transistors in first, second and third transistor regions 211, 212, and 213 in cell 210, Illustrative Fig. 2: the spaces are larger than the thickness of the dielectric pillars).
PNG
media_image2.png
649
889
media_image2.png
Greyscale
Regarding claim 5, Yu teaches the structure of claim 4, wherein, for a given CMOS device (transistors in first, second and third transistor regions 211, 212, and 213 in cell 210 in the layout diagram 200, Illustrative Fig. 2) with more than 35 nm between the nFET and the pFET (pFET in transistor region 211 and nFET in transistor region 212 of the GAA transistors of Illustrative Fig. 1; in forksheet transistors the distance between the pFET and nFET is less than 30 nm ([0033]: in a range from about 3 nm to about 30 nm)), both the nFET and the pFET of the given CMOS device are gate-all-around transistors (the pFET and nFETs are gate-all-around, [0022]) with a shared gate stack (all the transistors share the same gate 214 connected with the metal potion M, Illustrative Fig. 2, [0087]-[0088]).
Regarding claim 6, Yu teaches the structure of claim 4, wherein for a given CMOS device with less than 35 nm between the nFET and the pFET (forksheet transistor as shown in Illustrative Fig. 1: in forksheet transistors the distance between the nFET and pFET transistors is less than 35 nm ([0033]: in a range from about 3 nm to about 30 nm)), both the nFET (nFET, Illustrative Fig. 1) and the pFET (pFET, Illustrative Fig. 1) of the given CMOS device (forksheet transistor, Illustrative Fig. 1) are tri-gate devices (Illustrative Fig. 1: In both pFET and nFET, one side of the corresponding first semiconductor layers 106 are in contact with the first dielectric feature 130, and remaining sites are surrounded by the gate ([0022]: considering gate-all-around devices); therefore both the nFET and the pFET are tri-gate devices) that include channels (first semiconductor layers 106, Illustrative Fig. 1, [0023]) and the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1) separating the channels (first semiconductor layers 106, Illustrative Fig. 1), wherein proximal edges of the nFET (first semiconductor layers 106 of the nFET, Illustrative Fig. 1) and the pFET channels (first semiconductor layers 106 of the pFET, Illustrative Fig. 1) are attached to the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2022/0302275 A1).
Regarding claim 3, Yu teaches the structure of claim 1, wherein the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1) is not less than 8 nm thick (Figs. 4-6: the distance D2 is equal to the thickness of the first dielectric feature 130, which is in a range from about 3 nm to about 30 nm ([0033]).
Therefore, the range of thickness (between 3 nm and 30nm) provided by the prior art overlaps with the range of thickness (larger or equal to 8nm) provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of thickness of dielectric pillar can be optimized by routine experimentation to achieve desired electrical isolation between nFET and pFET, while a small device size and structural stability (see MPEP 2144.05(II)). Therefore, the range of values provided does not hold an inventive subject matter.
Allowable Subject Matter
Claim 12-20 are allowed, where claim 12 is the independent claim.
Independent claim 12 is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that
“a first forksheet complementary metal oxide semiconductor (CMOS) device that … has a first nFET (n-doped Field Effect Transistor) and a first pFET (p-doped Field Effect Transistor) and has a first β (effective width ratio) between the first nFET and the first pFET; and
a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second β between a second nFET and a second pFET, wherein the second β is different from the first β by at least 5 percent.”
as recited in claim 12, in combination with the remaining structural components of the claim.
Regarding the closest prior art, Chiang (US 2023/0223442 A1) teaches a semiconductor structure with multiple forksheet CMOS devices on a common substrate (Fig. 1I, [0044]), where the forksheet CMOS devices have same widths with width ratios β equal to 1. In one embodiment (Fig. 1N), however, Chiang discloses a semiconductor structure with one of the forksheet CMOS devices having only one FET on one side (left side in Fig. 1N), which can be considered as a forksheet CMOS device with a width ratio β of 0 next to a forksheet CMOS device with a width ratio β of 1, and therefore satisfying the limitation that “the second β is different than the first β by at least 5 percent”. However, the forksheet CMOS device with the width ratio β of 0 does not comprise both an nFET and a pFET as claimed in claim 12, and therefore fails to meet the limitations of claim 12. Another prior art of relevance is Ju (US 2022/0238717 A1) also teaching a semiconductor structure with multiple forksheet CMOS devices on a common substrate (Fig. 37B, [0095]), where forksheet devices have different widths. However, all the forksheet devices in Ju are symmetric, and therefore have width ratios β equal to 1. Therefore, Ju fails to teach the limitation that “the second β is different than the first β by at least 5 percent”. Another relevant prior art is You (US 2023/0317810 A1), which also teaches a semiconductor structure with multiple forksheet CMOS devices on a common substrate (Figs. 1B and 1G, [0012]-[0014]). However, all the forksheet devices in You are identical and they do not differ in their width ratios β. There has been no prior art or motivation identified that can modify Chiang, Ju, or You to make claim 12 obvious or anticipated.
Therefore, claim 12 is allowed as the references of the Prior Art of record considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitations involving two adjacent forksheet devices with different width ratios on a common substrate, and when these limitations are accompanied by the remaining structural limitations of claim 12.
Claims 13-20 are also allowed, because these claims inherit the allowable subject matter from claim 12.
Response to Arguments
It has been acknowledged that the applicant amended claims 1-6 and 12-20 per response dated on 1/15/2026. Applicant's arguments with respect to claims have been fully considered.
Applicant’s amendment to independent claim 1 overcame the rejection made based on Dentoni Litta (US 2021/0193821 A1) in the non-final office action. However, amended independent claims 1 is now rejected under new grounds based on a new prior-art, Yu (US 2022/0302275 A1), in the current office action. Rejections are also made on claim 2-6 based on this new prior-art.
Applicant’s amendments to claims 5-6 and 12-20 overcame all the objections made on these claims in the non-final office action. Accordingly, claims 12-20 are now allowed, as no grounds for rejection have been found for these claims.
For the purpose of compact prosecution, the Examiner notes, however, that incorporating more structural limitations regarding the forksheet CMOS device and GAA nanosheet CMOS device might make independent claim 1 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812