DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/26/2026 has been entered.
Response to Amendment
Applicant's amendments on 05/13/2026 have been reviewed and entered. Applicant has amended claims 1-6, 12, and 18-19. Afterwards, by obtaining authorization from the Applicant (Jake Christensen) on 6/11/2026 via phone, claims 1 and 13-20 have been further amended by the Examiner (see Examiner’s Amendment below). Accordingly, claims 1-20 remain pending in the application.
EXAMINER’S AMENDMENT
An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
Authorization for this examiner’s amendment was given in a phone communication with the attorney Jake Christensen on 6/11/2026.
Please amend claim 1, 13-20 as follows:
Claim 1: A semiconductor structure comprising:
a common substrate;
a forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate, the forksheet CMOS device including:
an nFET (n-doped Field Effect Transistor);
a pFET (p-doped Field Effect Transistor); and
a dielectric pillar separating the nFET from the pFET along a first horizontal direction;
a metallic shared gate connector that bridges gate stacks of the nFET and pFET across the dielectric pillar;
a gate-all-around (GAA) nanosheet CMOS device that is located on the common substrate and is adjacent to the forksheet CMOS device; and
a dielectric isolator separating the GAA nanosheet CMOS device from the forksheet CMOS device along a second horizontal direction orthogonal to the first horizontal direction.
Claim 13: The semiconductor structure of claim 12, wherein the first forksheet CMOS device includes a first dielectric pillar and the second forksheet device includes a second dielectric pillar, wherein the first and second dielectric pillars are of different thicknesses.
Claim 14: The semiconductor structure of claim 13, wherein each of the first dielectric pillar and the second dielectric pillar is not less than 8 nm thick.
Claim 15: The semiconductor structure of claim 13, further comprising a shared gate connector that bridges the first dielectric pillar in the first forksheet CMOS device.
Claim 16: The semiconductor structure of claim 12, wherein each of the first forksheet CMOS device and the second forksheet device includes an nFET structure and a pFET structure and a dielectric pillar that separates the nFET structure from the pFET structure, wherein each of the dielectric pillars is not more than 35 nm thick.
Claim 17: The semiconductor structure of claim 12, further comprising an intervening dielectric that separates the first forksheet CMOS device and the second forksheet device, wherein the intervening dielectric is more than 35 nm thick.
Claim 18: The semiconductor structure of claim 12, further comprising:
a gate-all-around CMOS device that is located on the common substrate and is adjacent to one of the first forksheet CMOS device and the second forksheet device.
Claim 19: The semiconductor structure of claim 18, wherein for a given one of the first forksheet CMOS device and the second forksheet
Claim 20: The semiconductor structure of claim 19, further comprising a dielectric isolator at least 35 nm thick that separates the gate-all-around nanosheet CMOS device from an adjacent one of the first forksheet CMOS device and the second forksheet device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2022/0302275 A1) in view of Yang (US 2021/0336001 A1).
Regarding claim 1, Yu teaches a semiconductor structure (semiconductor device structure 100, Fig. 31, [0079]) comprising:
a common substrate (substrate 101, Fig. 31, [0091]);
a forksheet complementary metal oxide semiconductor (CMOS) device (comprising fin structures 112b and 112c ([0029]), labeled as forksheet CMOS device in Illustrative Fig. 1, which is an annotated versions of Fig. 31 and 35, [0090]: “In the embodiment shown in FIG. 35, each of the transistor regions 211, 212, 213 in the cell 210 employs forksheet transistors formed in accordance with various embodiments of the present disclosure, such as the forksheet transistor shown in the semiconductor device 100 of FIG. 31.” ) that is located on the common substrate (substrate 101, Illustrative Fig. 1), the forksheet CMOS device (forksheet CMOS device, Illustrative Fig. 1) including:
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an nFET (n-doped Field Effect Transistor) (comprising fin structure 112b, labeled as nFET in Illustrative Fig. 1, [0055]: “the devices on the fin structures 112a and 112c may be designed for p-channel FETs and the devices on the fin structure 112b may be designed for n-channel FETs, or vice versa.”);
a pFET (p-doped Field Effect Transistor) (comprising fin structure 112c, labeled as pFET in Illustrative Fig. 1, [0055]); and
a dielectric pillar (first dielectric feature 130/dielectric feature 225, Illustrative Fig. 1, [0087]: “A dielectric feature 225, such as the dielectric feature 130 shown in FIG. 31, is formed between and coupled to two adjacent fin structures in the active regions 217, 218, 219 to form forksheet transistors.”) separating the nFET (nFET, Illustrative Fig. 1) from the pFET (pFET, Illustrative Fig. 1) along a first horizontal direction (Y direction, Illustrative Fig. 1);
a metallic shared gate connector (metal layer 186, Illustrative Fig. 1, [0079]: “In the embodiment shown in FIG. 31, since a portion of the first gate electrode layer 182 is in contact with the second gate electrode layer 184, the signal can be provided to both first and second gate electrode layers 182, 184 via the metal layer 186.”) that bridges gate stacks (first gate electrode layer 182 and second gate electrode layer 184, Illustrative Fig. 1, [0079]) of the nFET (nFET, Illustrative Fig. 1) and pFET (pFET, Illustrative Fig. 1) across the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1);
a gate-all-around (GAA) nanosheet CMOS device (GAA nanosheet CMOS device, Illustrative Fig. 1, [0088]: “first, second, and third transistor regions 251, 252, 253, gates 254, source and drain (S/D) region 256, and active regions 257, 258, 259.“, and [0090]: “In contrast, each of the transistor regions 251, 252, 253 in the cell 250 employ traditional nanosheet transistor which does not require a dielectric isolation between n-type and p-type transistors.”, and also [0022]: “The nanosheet transistors may be referred to as … gate-all-around (GAA) transistors …”) that is located on the common substrate (see [0087]-[0088]: cells 210 and 250 are on the same substrate, Illustrative Fig. 1) and is adjacent to the forksheet CMOS device (forksheet CMOS device, Illustrative Fig. 1: forksheet CMOS device and GAA nanosheet CMOS device are adjacent to each other in the X direction); and
an isolator (isolator, Illustrative Fig. 1) separating the GAA nanosheet CMOS device (GAA nanosheet CMOS device, Illustrative Fig. 1) from the forksheet CMOS device (forksheet CMOS device, Illustrative Fig. 1) along a second horizontal direction (X direction, Illustrative Fig. 1) orthogonal the first horizontal direction (Y direction, Illustrative Fig. 1).
Yu, however, does not disclose the structure and material of the isolator, and therefore, does not teach that the isolator is a dielectric isolator.
Yang, on the other hand, teaches a semiconductor structure (IC layout, Fig. 5A, [0015]) including multiple nanosheet cells (cell C3/structure S3 and cell C5/structure S5, Figs. 5A-B, [0079]-[0081]) wherein the isolation region between cells is filled with a dielectric material (dielectric region DR, Fig. 5A, [0031]) to form a dielectric isolator, which allows forming electrical connections (metal pattern M0R/M0, Figs. 5A-B, [055]) above the transistor level between cells (see Figs. 5A and 5B). Yu, also, discloses that there are connection lines between different cells (track lines 205(1)-205(11), Illustrative Fig. 1, [0089]: “the track lines 205(1)-205(11) are formed in a metal layer at a different level (i.e., above the transistor level) and are used to route signal (interconnect) lines for passing signals between the cells”). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to fill the isolation region with a dielectric material, as taught by Yang, to facilitate electrical connections between the cells, which would provide the benefit of forming integrated circuit devices comprising multiple cells connected to each other.
Thus, the combination of Yu and Yang meets all the limitations of claim 1.
Regarding claim 2, Yu in view of Yang teaches the semiconductor structure of claim 1, wherein
Yu further teaches that the dielectric pillar (first dielectric feature 130/dielectric feature 225, Illustrative Fig. 1) is not more than 35 nm thick (Figs. 4-6: the distance D2 is equal to the thickness of the first dielectric feature 130, which is in a range from about 3 nm to about 30 nm ([0033])).
Regarding claim 4, Yu in view of Yang teaches the semiconductor structure of claim 1, wherein
Yang further teaches additional CMOS devices (comprising transistors in first, second and third transistor regions 211, 212 and 213 in cell 210 in the layout diagram 200, Illustrative Fig. 1, [0087]-[0088]), wherein a space (spaces between first, second and third transistor regions 211, 212 and 213, see spaces labeled in Illustrative Fig. 1) between active regions (active regions 217, 218, and 219, Illustrative Fig. 1, [0087]-[0088]) of adjacent pFETs or nFETs of adjacent CMOS devices (transistors in first, second and third transistor regions 211, 212, and 213 in cell 250, Illustrative Fig. 1, [0087]-[0088]) of the additional CMOS devices (comprising transistors in first, second and third transistor regions 211, 212 and 213 in cell 210 in the layout diagram 200, Illustrative Fig. 1) is greater than a thickness of a thickest dielectric pillar (dielectric pillars are as dielectric feature 225 in Illustrative Fig. 1, [0087]: “dielectric feature 225, such as the dielectric feature 130 shown in FIG. 31, is formed between and coupled to two adjacent fin structures in the active regions 217, 218, 219 to form forksheet transistors.”) in the additional CMOS devices (transistors in first, second and third transistor regions 211, 212, and 213 in cell 210, Illustrative Fig. 1: the spaces are larger than the thickness of the dielectric pillars in transistor regions 211, 212, and 213).
Regarding claim 5, Yu in view of Yang teaches the semiconductor structure of claim 4, wherein
Yu further teaches that, for a given CMOS device (transistors in first, second and third transistor regions 211, 212, and 213 in cell 210 in the layout diagram 200, Illustrative Fig. 2) with more than 35 nm between the nFET and the pFET (pFET in transistor region 211 and nFET in transistor region 212 of the GAA transistors of Illustrative Fig. 1; in forksheet transistors the distance between the pFET and nFET is less than 30 nm ([0033]: in a range from about 3 nm to about 30 nm)), both the nFET and the pFET of the given CMOS device are gate-all-around transistors (the pFET and nFETs are gate-all-around, [0022]) with a shared gate stack (all the transistors share the same gate 214 connected with the metal potion M, Illustrative Fig. 2, [0087]-[0088]).
Regarding claim 6, Yu in view of Yang teaches the semiconductor structure of claim 4, wherein
Yu further teaches that for a given CMOS device with less than 35 nm between the nFET and the pFET (forksheet transistor as shown in Illustrative Fig. 1: in forksheet transistors the distance between the nFET and pFET transistors is less than 35 nm ([0033]: in a range from about 3 nm to about 30 nm)), both the nFET (nFET, Illustrative Fig. 1) and the pFET (pFET, Illustrative Fig. 1) of the given CMOS device (forksheet transistor, Illustrative Fig. 1) are tri-gate devices (Illustrative Fig. 1: In both pFET and nFET, one side of the corresponding first semiconductor layers 106 are in contact with the first dielectric feature 130, and remaining sites are surrounded by the gate ([0022]: considering gate-all-around devices); therefore both the nFET and the pFET are tri-gate devices) that include channels (first semiconductor layers 106, Illustrative Fig. 1, [0023]) and the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1) separating the channels (first semiconductor layers 106, Illustrative Fig. 1), wherein proximal edges of the nFET (first semiconductor layers 106 of the nFET, Illustrative Fig. 1) and the pFET channels (first semiconductor layers 106 of the pFET, Illustrative Fig. 1) are attached to the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2022/0302275 A1) in view of Yang (US 2021/0336001 A1) as applied to claims 1-2 and 4-6 above.
Regarding claim 3, Yu in view of Yang teaches the semiconductor structure of claim 1, wherein
Yu further teaches that the dielectric pillar (first dielectric feature 130, Illustrative Fig. 1) is not less than 8 nm thick (Figs. 4-6: the distance D2 is equal to the thickness of the first dielectric feature 130, which is in a range from about 3 nm to about 30 nm ([0033]).
Therefore, the range of thickness (between 3 nm and 30nm) provided by the prior art overlaps with the range of thickness (larger or equal to 8nm) provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of thickness of dielectric pillar can be optimized by routine experimentation to achieve desired electrical isolation between nFET and pFET, while a small device size and structural stability (see MPEP 2144.05(II)). Therefore, the range of values provided does not hold an inventive subject matter.
Allowable Subject Matter
Claim 12-20 are allowed, where claim 12 is the independent claim.
Independent claim 12 is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that
“a first forksheet complementary metal oxide semiconductor (CMOS) device that … has a first nFET (n-doped Field Effect Transistor) and a first pFET (p-doped Field Effect Transistor) and has a first β (effective width ratio) between the first nFET and the first pFET; and
a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second β between a second nFET and a second pFET, wherein the second β is different from the first β by at least 5 percent.”
as recited in claim 12, in combination with the remaining structural components of the claim.
Regarding the closest prior art, Chiang (US 2023/0223442 A1) teaches a semiconductor structure with multiple forksheet CMOS devices on a common substrate (Fig. 1I, [0044]), where the forksheet CMOS devices have same widths with width ratios β equal to 1. In one embodiment (Fig. 1N), however, Chiang discloses a semiconductor structure with one of the forksheet CMOS devices having only one FET on one side (left side in Fig. 1N), which can be considered as a forksheet CMOS device with a width ratio β of 0 next to a forksheet CMOS device with a width ratio β of 1, and therefore satisfying the limitation that “the second β is different than the first β by at least 5 percent”. However, the forksheet CMOS device with the width ratio β of 0 does not comprise both an nFET and a pFET as claimed in claim 12, and therefore fails to meet the limitations of claim 12. Another prior art of relevance is Ju (US 2022/0238717 A1) also teaching a semiconductor structure with multiple forksheet CMOS devices on a common substrate (Fig. 37B, [0095]), where forksheet devices have different widths. However, all the forksheet devices in Ju are symmetric, and therefore have width ratios β equal to 1. Therefore, Ju fails to teach the limitation that “the second β is different than the first β by at least 5 percent”. Another relevant prior art is You (US 2023/0317810 A1), which also teaches a semiconductor structure with multiple forksheet CMOS devices on a common substrate (Figs. 1B and 1G, [0012]-[0014]). However, all the forksheet devices in You are identical and they do not differ in their width ratios β. There has been no prior art or motivation identified that can modify Chiang, Ju, or You to make claim 12 obvious or anticipated.
Therefore, claim 12 is allowed as the references of the Prior Art of record considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitations involving two adjacent forksheet devices with different width ratios on a common substrate, and when these limitations are accompanied by the remaining structural limitations of claim 12.
Claims 13-20 are also allowed, because these claims inherit the allowable subject matter from claim 12.
Response to Arguments
It has been acknowledged that the applicant amended claims 1-6, 12, and 18-19 per response dated on 5/13/2026. Applicant's arguments with respect to claims have been fully considered. Accordingly, afterwards, by obtaining authorization from the Applicant (Jake Christensen) on 6/11/2026 via phone, claims 1 and 13-20 have been further amended by the Examiner (see Examiner’s Amendment above).
After Examiner’s amendment to independent claim 1, the amended claim 1 overcame the rejection made based on Yu (US 2022/0302275 A1) according to the interpretation of Yu in the final office action. However, amended claims 1 is now rejected under new grounds based again on a new interpretation of Yu in the current office action. This time the rejection is based on another transistor located next to the forksheet transistor of Yu as detailed in the office action above. Rejections are also made on claim 2-6 based on Yu.
For the purpose of compact prosecution, the Examiner notes, however, that incorporating structural limitations regarding the forksheet CMOS device, such as including another forksheet CMOS device with a different dielectric pillar width, or limitations pointing out that the nanosheets of the forksheet CMOS device and GAA nanosheet CMOS device being continuations of each other might make the independent claim 1 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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