Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/27/2022 and 10/29/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, and 11-14, 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seo (US 20210408225 A1).
Regarding claim 1, Seo discloses a method for forming a semiconductor structure, comprising:
providing a base (Fig. 2A: 11/12/13); forming ([0042]: “A mold structure 20 may be formed”) a sacrifice layer (15/17) and a support layer (14/16/18) located on the sacrifice layer on the base;
removing ([0050]: “etching the mold structure 20”) a part of the support layer and a part of the sacrifice layer, to form a plurality of capacitor vias (21) in the support layer and the sacrifice layer;
forming external electrode layers (Fig. 2B: 22, subsequently annotated as MLCS) on sidewall surfaces of the capacitor vias;
forming a dielectric layer (Fig. 2I: 27) on a sidewall surface of each external electrode layer;
removing remaining sacrifice layer (Figs. 2D-2G) between the external electrode layers to form a cavity (15G/17G) at a position where the remaining sacrifice layer has been removed;
forming an internal electrode layer (Fig. 2I: 28; a firstly formed layer of [0101]: “stacking a liner electrode, a gap-fill electrode, and a low-resistance electrode”. Note: this layer corresponds to layer 109 in Fig. 1A) on a surface of the dielectric layer (directly on) and a bottom surface of each capacitor via (indirectly on);
forming a first conductive layer completely filling the cavity (28; a lastly formed layer of [0101]: “stacking a liner electrode, a gap-fill electrode, and a low-resistance electrode”), wherein the first conductive layer is in contact (indirect contact) with a respective one of the external electrode layers;
forming a second conductive layer (Fig. 2C: 107) completely filling a remaining part of each capacitor via on the internal electrode layer (107 is indirectly on the subsequently formed layer 28, as shown in Fig. 2I);
forming an isolation layer (Fig. 2I: a portion of 27 corresponding to a portion of 108, See annotated Fig. 1A. Note: the selected portion of 108 isolates conductive 109 from underlying instances of conductive 107, thus, “an isolation layer”) covering the second conductive layer (directly vertically covering), the dielectric layer (the “isolation layer” portion of 27/108 vertically overlaps the “dielectric layer” portion of 27/108. See annotated Fig. 1A for direction designation), the external electrode layers (the “isolation layer” portion of 27/108 vertically overlaps MLCS), the internal electrode layer (the “isolation layer” portion of 27/108 vertically overlaps 28/109), and the support layer (the “isolation layer” portion of 27/108 vertically overlaps MLCS);
forming a plurality ([0109]: “openings” is plural, and thus teaches pluralization of the illustrated opening) of openings (See annotated Fig. 1A) exposing the first conductive layer (28/109 directly vertically reaches the opening, thus, the opening is “exposing” the cited sub-layer of 28/109) and the external electrode layers (MLCS is directly exposed during the initial deposition of 27/108 and initial creation of the opening. See exposed MLCS in Fig. 2H before initial deposition of 27/108 in Fig. 2I) in the isolation layer;
and forming a connection structure (a portion of 109, See annotated figure) electrically connected with the first conductive layer (integrally connected) and the external electrode layers (capacitively electrically connected through 27/108) on a surface of the isolation layer (directly on) and in the openings (28/109 extends into the opening).
Illustrated below is a marked and annotated figure of Fig. 1A of Seo.
PNG
media_image1.png
507
516
media_image1.png
Greyscale
Regarding claim 2, Seo discloses the method for forming the semiconductor structure according to claim 1 (Fig. 1A), wherein a plurality of electrode contact structures (13/103; [0021]: “contact plugs”) are formed in the base, adjacent electrode contact structures of the plurality of electrode contact structures are isolated from each other by an insulating layer (12/102; [0021]: “inter-layer dielectric layer”), and each of the plurality of capacitor vias exposes a respective one of the plurality of electrode contact structures (Fig. 2A shows contact 13 exposed to via 21).
Regarding claim 3, Seo discloses the method for forming the semiconductor structure according to claim 2 (Fig. 2A), wherein a material of the sacrifice layer ([0043]: “layer 15 may include USG, PSG, BSG, BPSG, FSG, or a combination thereof”) is different from a material of the support layer ([0044]: “layer 16 may include silicon nitride”) and a material of the insulating layer ([0040]: “layer 12 may be formed of silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant”. Note: the cited paragraphs include a plurality of different material configurations arriving at the claim.).
Regarding claim 6, Seo discloses the method for forming the semiconductor structure according to claim 1, wherein forming the external electrode layers comprises: forming an external electrode material layer (Fig. 2B: 22) on the sidewall surfaces and the bottom surfaces of the capacitor vias and a surface of the support layer; and removing the external electrode material layer (Fig. 2H) on the bottom surfaces of the capacitor vias (a portion of 22 indirectly on the bottoms of the vias 21 has been removed) and the surface of the support layer (a portion of 22 indirectly on the layer 14/16/17 has been removed) by a maskless etching process (there is no disclosed separate masking step), wherein a remaining part of the external electrode material layer on the sidewall surfaces of the capacitor vias forms the external electrode layers (MLCS is the remaining portion of 22).
Regarding independent claim 11, Seo discloses a semiconductor structure (Fig. 1A), comprising:
a base (101/102/103);
a plurality of separate ring-shaped external electrode layers (MLCS; [0026]: “a conductive material”; “ring-shaped” is shown in top-down views of Figs. 1B-1D) located on the base (directly on);
a dielectric layer (108) located on an inner sidewall of each external electrode layer (directly on, in at least some direction);
an internal electrode layer (106) located on an inner sidewall of the dielectric layer (directly on) and a surface of the base (indirectly on) in a ring of each external electrode layer (106 is located within each ring of MLCS);
a first conductive layer (a portion of 109, See annotated figure) filling a space outside the ring of each external electrode layer (See top-down views of Figs. 1B-1D), wherein the first conductive layer is in contact (indirect contact) with a respective one of the external electrode layers;
a second conductive layer (107) filling a space inside the ring of the internal electrode layer, wherein the second conductive layer is in contact with the internal electrode layer (direct contact);
an isolation layer (a portion of 108, See annotated figure. Note: the selected portion of 108 isolates conductive 109 from underlying instances of conductive 107, thus, “an isolation layer”) covering the second conductive layer (directly vertically covering), the dielectric layer (the “isolation layer” portion of 108 vertically overlaps the “dielectric layer” portion of 108. See annotated figure for direction designation), the external electrode layers (the “isolation layer” portion of 108 vertically overlaps MLCS), and the internal electrode layer (the “isolation layer” portion of 108 vertically overlaps 106), wherein an opening (See annotated figure) exposing the first conductive layer (109 directly vertically reaches the opening, thus, the opening is “exposing” 109) and the external electrode layers (MLCS is directly exposed during the initial deposition of 108 and initial creation of the opening. See exposed MLCS in Fig. 2H before initial deposition of 108 in Fig. 2I: annotated as 27) is formed in the isolation layer (Note: the opening is a resultant shape formed in 108 during deposition of 108, as shown by the conformal shape);
and a connection structure (a portion of 109, See annotated figure) that is located on a surface of the isolation layer (directly on) and in the opening (109 extends into the opening) and is connected with the first conductive layer (integrally connected) and each external electrode layer (indirectly physically connected).
Regarding claim 12, Seo discloses the semiconductor structure according to claim 11 (Fig. 1A), wherein a plurality of electrode contact structures (103; [0021]: “contact plugs”) are provided in the base, adjacent electrode contact structures of the plurality of electrode contact structures are isolated from each other by an insulating layer (102; [0021]: “inter-layer dielectric layer”), and each of the external electrode layers is connected to a respective one of the plurality of electrode contact structures (MLCS is directly connected to 103).
Regarding claim 13, Seo discloses the semiconductor structure according to claim 11 (Fig. 1A), wherein the external electrode layers (the MLCS material is [0028]: “titanium nitride”), the first conductive layer (the 109 material includes [0101]: “titanium nitride”), and the internal electrode layer (the 106 material is [0029]: “titanium nitride”) are made of the same material.
Regarding claim 14, Seo discloses the semiconductor structure according to claim 13 (Fig. 1A), wherein a material of the external electrode layers, the first conductive layer, and the internal electrode layer is titanium nitride (TiN is cited for each of these layers in the claim 13 rejection).
Regarding claim 16, Seo discloses the semiconductor structure according to claim 11 (Fig. 1A), wherein a support layer (MLDS; [0025]: “a supporter”) is further provided between the external electrode layers, and the support layer is in contact (direct contact) with an outer sidewall of the external electrode layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Cho (US 20210134803 A1).
Regarding claim 15, Seo discloses the semiconductor structure according to claim 11 (Fig. 1A), wherein a material of the second conductive layer is [polycrystalline silicon] ([0057]: “pillar-shaped electrode 24 may be polysilicon” corresponds to 107), and a material of the dielectric layer is a high dielectric constant material ([0098]: “a high-k material” corresponds to 108).
Seo fails to explicitly teach “a material of the second conductive layer is doped polycrystalline silicon”.
Cho teaches a second conductive layer in the same field of endeavor (Fig. 2C: BE), wherein a material of the second conductive layer is doped polycrystalline silicon ([0051]: “an impurity-doped polysilicon layer”). Modifying the material of Seo’s second conductive layer by including the material of Cho’s second conductive layer would arrive at the claimed material configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each case the second conductive layer is performing the function of an electrode (Seo: [0057]: “pillar-shaped electrode”; Cho: [0051]: “bottom electrode…columnar shape”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration because it is substituting one known material for another, both of which are useful for the same purpose. MPEP 214 (I)(B).
Allowable Subject Matter
Claims 4-5, 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 4-5 is the inclusion of the limitation “wherein forming the plurality of capacitor vias in the support layer and the sacrifice layer comprises: removing a part of the support layer and a part of the sacrifice layer by a dry etching process, to form initial capacitor vias in the support layer and the sacrifice layer; thinning the sacrifice layer on sidewalls of the initial capacitor vias by a first wet etching process, to increase a dimension of each of the initial capacitor vias; and removing a part of the support layer and a part of the insulating layer by a second wet etching process, to form the capacitor vias” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “dry etching process”, “first wet etching process”, “second wet etching process”, and the required sequence and functions of these etches in combination with all other limitations in claims 4, 3, 2, and 1.
The primary reason for the allowable subject matter of claim 7 is the inclusion of the limitation “wherein forming the dielectric layer comprises: forming a dielectric material layer on the sidewall surfaces of the external electrode layers, the bottom surfaces of the capacitor vias, and a surface of the support layer; and removing the dielectric material layer on the bottom surfaces of the capacitor vias and the surface of the support layer by a maskless etching process, wherein a remaining part of the dielectric material layer on the sidewall surfaces of the external electrode layers forms the dielectric layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “removing the dielectric material layer”, in combination with all other limitations in claims 7 and 1.
The primary reason for the allowable subject matter of claims 8-9 is the inclusion of the limitation “wherein the operation of forming the internal electrode layer on the surface of the dielectric layer and the bottom surface of each capacitor via and the operation of forming the first conductive layer completely filling the cavity are synchronously performed” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “synchronously performed”, in combination with all other limitations in claims 8 and 1.
The primary reason for the allowable subject matter of claim 10 is the inclusion of the limitation “wherein after the dielectric layer is formed, removing the remaining sacrifice layer between the external electrode layers to form the cavity at the position where the remaining sacrifice layer has been removed comprises: forming a mask layer on a surface of the support layer, a top surface of each external electrode layer, and a top surface of the dielectric layer, and above the capacitor vias, and forming a first opening exposing the surface of a part of the support layer between adjacent capacitor vias in the mask layer; etching the exposed support layer along the first opening by using the mask layer as a mask, to expose a surface of the sacrifice layer at a bottom; removing all the sacrifice layer along the exposed sacrifice layer, to form the cavity at the position where the sacrifice layer has been removed; and removing the mask layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “after the dielectric layer is formed, removing the remaining sacrifice layer”, in combination with all other limitations in claims 10 and 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817