DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 27, 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The amended drawings were received on July 12, 2025. These amended drawings are acceptable.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the providing a semiconductor substrate comprising a memory area and a peripheral area, forming an insulating layer on a surface of the memory area, and forming a first metal layer on a surface of the peripheral area AND the first word line insulating layer is higher than a top surface of the peripheral area in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the patterned first mask layer in claim 9 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amended specification were received on July 12, 2025. These amended specifications are acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 3. Claim 1 recites the limitation “forming a first metal layer on a surface of the peripheral area” at the beginning of the claim language, and further recites “a top surface of the peripheral area” at the end of the claim language and “a peripheral gate” mid claim language.
It is unclear to the examiner if “a surface” and “a top surface” are the same surface or different surfaces of the peripheral region or if the top surface of the peripheral area or a top surface of the peripheral gate.
For the purpose of examination and compact prosecution, examiner shall interpret a top surface of the peripheral region to be a top surface of the substrate of the peripheral region.
Claim 3 is rejected for the same analogous reasons as claim 1 above.
Claims 3-13 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 9. Claim 9 recites the limitation “the patterned first mask layer” in the second line of the claim language.
There is insufficient antecedent basis for this limitation in the claim.
Claim 10-12 are rejected for dependence upon a 112(b) rejected instance claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-13 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et al (U.S. 2015/0111360).
Regarding claim 1. Kim et al discloses a method for forming a semiconductor structure ([0025], FIGS. 4-15), comprising:
providing a semiconductor substrate (FIG. 6, item 100) comprising a memory area (FIG. 5, first region I) and a peripheral area (FIG. 6, second region II), forming an insulating layer (FIG. 5, item 150, 210) on a surface of the memory area (FIG. 6, first region I), and forming a first metal layer (FIG. 6, item 200) on a surface of the peripheral area (FIG. 5, second region II);
etching (FIG. 7, item 250) the insulating layer (FIG. 7, item 150, Section H-H’) and the memory area (FIG. 7, first region I) of the semiconductor substrate (FIG. 7, item 100, Section G-G’) to form a plurality of bit line trenches (FIG. 7, item 250) arranged at intervals along a first direction (FIG. 7, first direction) and etched insulating layer (FIG. 7, item 150), wherein part (FIG. 7, bottom part of item 250) of the bit line trench (FIG. 7, item 250) is located in the memory area (FIG. 7, first region I) of the semiconductor substrate (FIG. 7, item 100, Section G-G’), and other part (FIG. 7, top part of item 250) of the bit line trench (FIG. 7, item 250) is located in the etched insulating layer (FIG. 7, item 150);
forming a second metal layer (FIG. 10, item 270) on a surface of the bit line trench (FIG. 10, item 260), the surface of the memory area (FIG. 10, First Region I), and a surface of the first metal layer (FIG. 10, item 200); and
etching (FIG. 11) the first metal layer (FIG. 11, item 209) and the second metal layer (FIG. 11, item 272) to form a semi-buried bit line structure (FIG 11, item 320) and a peripheral gate (FIG. 11, item 330),
wherein the insulating layer (FIG. 7, item 150, 175, 185) comprises first word line insulating layer (FIG. 7, item 150, section K-K’), and a bit line insulating layer (FIG. 7, item 185) located between (see annotated FIG. 7; FIG. 7 shows items 185 is between and covers items 150 and covers item 175) adjacent first word line insulating layers (FIG. 7, items 150 and 175, section K-K’) and covering the first word line insulating layers (FIG. 7, item 185 covers items 150 and 175);
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the method further comprises:
forming a buried word line structure (FIG. 7, item 160 and item 175) in the memory area (FIG. 7, first region I), wherein the buried word line structure (FIG. 7, item 160 and item 175) at least comprises the first word line insulating layer (FIG. 7, item 150 and 175, section K-K’), and in a third direction (FIG. 7, above the bottom of the substrate item 100, not first direction and not second direction), a top surface (FIG. 7, item 170) of the first word line insulating layer (FIG. 7, item 150 and 175, section K-K’) is higher than a top surface (FIG. 7, top surface of item 120) of the peripheral area (FIG. 7, item second region II).
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Regarding claim 8. The method according to claim 1, wherein the formation of the first metal layer consists of:
Kim et al a further discloses forming a first initial metal layer (FIG. 6, item 200), a first mask layer (FIG. 6, item 230 in second region II) and a first photoresist layer (FIG. 6, item 240 in second region II) on the surface of the peripheral area (FIG. 6, item second region II), the surface of the memory area (FIG. 6, item first region I), and a surface of the first word line insulating layer (FIG. 6, item 150) in sequence, wherein the first photoresist layer (FIG. 6, item 240) has a first preset pattern (FIG. 6, item 240; [0047]) for exposing the memory area (FIG. 6, item first region I);
etching ([0049]) the first mask layer (FIG. 6, item 230) through the first photoresist layer (FIG. 6, item 240) to transfer the first preset pattern (FIG. 6, item 240) to the first mask layer (FIG. 6, item 230); and
etching ([0049]) the first initial metal layer (FIG. 6, item 200) to form the first metal layer (FIG. 7, item 200 in second region II).
Regarding Claim 9. Kim et al discloses all the limitations of The method according to claim 8 above.
Kim et al further discloses further comprising: removing ([0049]) the first photoresist layer (FIG. 6, item 240 in second region II) and the patterned ([0049]) first mask layer (FIG. 6, item 230), after the first metal layer (FIG. 7, item 200) is formed,.
Regarding Claim 10. Kim et al discloses all the limitations of the method according to claim 9 above.
Kim et al further discloses wherein the etching (FIG. 7, item 250) the insulating layer (FIG. 7, item 150, Section H-H’) and the memory area (FIG. 7, first region I) of the semiconductor substrate (FIG. 7, item 100, Section G-G’) to form a plurality of bit line trenches (FIG. 7, item 250) arranged at intervals along a first direction (FIG. 7, first direction) comprises:
forming a bit line insulating layer (FIG. 6, item 220 in first region), a bit line mask layer (FIG. 6, item 230 in first region) and a second photoresist layer (FIG. 6, item 240 in first region) in sequence on a surface of the first metal layer (FIG. 6, item 200), the surface of the memory area (FIG. 6, item first region I) and the surface of the first word line insulating layer (FIG. 6, item 150), wherein the second photoresist layer (FIG. 6, item 240) has a second preset pattern (FIG. 6, item 240) including a plurality of sub-patterns (FIG. 6, item 240) arranged in parallel along the first direction (FIG. 6, first direction), and each of the sub-patterns (FIG. 6, item 240) is used for forming one bit line trench (FIG. 7, item 250);
etching ([0049]) the bit line mask layer (FIG. 6, item 230) through the second photoresist layer (FIG. 6, item 240) to transfer the sub- pattern (FIG. 6, item 240) to the bit line mask layer, to obtain a patterned bit line mask layer (FIG. 6, item 230); and
etching ([0049]) the bit line insulating layer (FIG. 6, item 210), the first word line insulating layer (FIG. 6, item 150) and the memory area (FIG. 7, item first region I) through the patterned bit line mask layer (FIG. 6, item 230) to form the bit line trench (FIG.7, item 250).
Regarding Claim 11. Kim et al further discloses the method according to claim 10 above.
Kim et al further discloses further comprising: removing ([0049]) the second photoresist layer (FIG. 6, item 240), the patterned bit line mask layer (FIG. 6, item 230), and the bit line insulating layer (FIG. 6, item 220) on the surface of the peripheral area (FIG. 7, item first region I), after the bit line trench is formed (FIG. 7, item 250).
Regarding Claim 12. Kim et al further discloses the method according to claim 10 above.
Kim et al further discloses wherein the etching (FIG. 11) the first metal layer (FIG. 11, item 209) and the second metal layer (FIG. 11, item 272) to form a semi-buried bit line structure (FIG 11, item 320) and a peripheral gate (FIG. 11, item 330).
comprises:
forming a second mask layer (FIG. 10, item 300) on a surface (FIG. 3, item 290 and 280) of the second metal layer (FIG. 10, item 270) in the peripheral area (FIG. 10, item second region II);
etching ([0066]) the second metal layer (FIG. 10, item 270) through the second mask layer (FIG. 10, item 300) to form etched second metal layer (FIG. 10, item 272), wherein the etched second metal layer (FIG. 11, item 272) located in the bit line trench (FIG. 7, item 250) constitutes the semi-buried bit line structure (FIG. 11, item 320); and
etching ([0066]) the first metal layer (FIG. 10, item 200) through the etched second metal layer (FIG. 11, item 274) to form etched first metal layer (FIG. 10, item 209), wherein the etched first metal layer (FIG. 11, item 209) and the etched second metal layer (FIG. 11, item 274) located in the peripheral area (FIG. 11, item second region II) together constitute the peripheral gate (FIG. 11, item 330).
Regarding claim 13. Kim et al discloses all the limitations of the method according to claim 1 above.
Kim et al further discloses further comprising: forming a second isolation layer (FIG. 12, item 350) on the surface of the peripheral area (FIG. 13, item second region II), the surface of the memory area (FIG. 12, item first region I) and a surface of the peripheral gate (FIG. 13, item 330), after ([0073]-[0074]) the semi-buried bit line structure (FIG. 12, item 320) and the peripheral gate (FIG. 13, item 330) are formed,.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al(U.S. 2015/0111360) as applied to claim 1 above, and further in view of Park et al (U.S. 2011/0133283).
Regarding claim 3. Kim et al discloses all the limitations of the method according to claim 1 above.
Kim et al further discloses wherein the top surface of the first word line insulating layer is higher than the top surface of the peripheral area in the third direction.
Kim et al fails to explicitly disclose the top surface of the peripheral area by 70 to 90 nm.
However, Park et al teaches ([0082], i.e. the landing plug layer 135 is formed to have the same or similar thickness as that of the buried gate of the cell region, and preferably, the landing plug 135 has a thickness of about 1000 .ANG.)
Since Kim et al and Park et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method for forming a semiconductor structure as disclosed to modify Kim et al with the teachings of extends the top surface of the peripheral area by 70 to 90 nm as disclosed by Park et al. The use of the landing plug layer 135 is formed to have the same or similar thickness as that of the buried gate of the cell region, and preferably, the landing plug 135 has a thickness of about 1000 .ANG. in Park et al provides for other effects in that the substrate of the peripheral region is not etched to obtain the difference in height between the cell region and the peripheral region, and thus the fabrication process of the semiconductor device can be simplified (Park et al, [0082]).
SEE MPEP 2144.05 I Obviousness of Similar and Overlapping ranges, amounts, and proportions
Regarding claim 4. Kim et al discloses all the limitations of the method according to claim 1 above.
Kim et al further discloses wherein the formation of the buried word line structure (FIG. 7, item 160 and item 175) in the memory area (FIG. 7, first region I) comprises:
plurality of word line trenches (FIG. 4, item 160) arranged at intervals (FIG. 6, item 160, section K-K’) along a second direction (FIG 4, item first direction) perpendicular to the first direction (FIG. 4, item second direction)
Kim et al fails to explicitly disclose:
forming a first isolation layer on the surface of the memory area and the surface of the peripheral area;
etching the first isolation layer on the surface of the memory area and the memory area, to form a plurality of word line trenches arranged at intervals along a second direction perpendicular to the first direction; and
forming the buried word line structure in the word line trench.
However, Park et al teaches forming a first isolation layer (FIG. 1a, item 130) on the surface of the memory area (FIG. 1a, Cell Region) and the surface of the peripheral area (FIG. 1b, Peripheral region);
etching the first isolation layer (FIG. 1g, item 132) on the surface of the memory area (FIG. 1g, item Cell region) and the memory area (FIG. 1g, item Cell region), to form a plurality of word line trenches (FIG. 1g, item 142; [0056], i.e. A gate oxide layer (not shown) may be formed on the surface of the trench 142. the gate oxide layer is formed by a low-temperature plasma process, or is formed by a single-wafer-type radical oxidation process or dry oxidation process, so as to prevent deterioration of the characteristics elements); and
forming the buried word line structure (FIG. 1g, item 146) in the word line trench (FIG. 1g, item 142).
Since Kim et al and Park et al teach word lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method for forming a semiconductor structure as disclosed to modify Kim et al with the teachings of forming a first isolation layer on the surface of the memory area and the surface of the peripheral area, etching the first isolation layer on the surface of the memory area and the memory area, to form a plurality of word line trenches arranged at intervals along a second direction perpendicular to the first direction, and forming the buried word line structure in the word line trench as disclosed by Park et al. The use of gate oxide layer (not shown) may be formed on the surface of the trench, the gate oxide layer is formed by a low-temperature plasma process, or is formed by a single-wafer-type radical oxidation process or dry oxidation process in Park et al provides to prevent deterioration of the characteristics elements (Park et al, [0056]).
Regarding claim 5. Kim et al and Park et al discloses all the limitations of the method according to claim 4 above.
Kim et al further discloses wherein the formation of the buried word line structure (FIG. 4, item 160) in the word line trench ([0039]) comprises:
forming a gate oxide layer (FIG. 4, item 130) on an inner wall of the word line trench ([0039]); forming a word line metal layer (FIG. 4, item 140) in the word line trench ([0039]) where the gate oxide layer (FIG. 4, item 130) is formed; and
Park discloses forming a word line insulating layer (FIG. 2g, item 148) on a surface of the word line metal layer (FIG. 2g, item 142), wherein the word line insulating layer (FIG. 2g, item 148) comprises a second word line insulating layer (Fig 2g, bottom half item 148) and the first word line insulating layer (FIG. 2g, top half of item 148) located on the surface (FIG. 2g, top half of item 148 is on the surface of the bottom half of item 148) of the second word line insulating layer (FIG. 2g, bottom half item 148), wherein the first word line insulating layer (FIG. 2g, top half of item 148) is located in the first isolation layer (FIG. 2, item 132).
Regarding claim 6. Kim et al and Park et al discloses all the limitations of the method according to claim 5 above.
Park et al further discloses further comprising: removing part of the first isolation layer (FIG. 2g, items 132 and 280) in the peripheral area (FIG. 2g, item 280 in peripheral region) and the memory area (FIG. 2g, item 132 in cell region) to expose a sidewall (FIG. 2h, sidewall of top half of item 148) of the first word line insulating layer (FIG. 2h, top half of item 148), after the buried word line structure is formed (FIG. 2g, item 146).
Regarding claim 7. Kim et al and Park et al discloses all the limitations of the method according to claim 6 above.
Park et al further discloses further comprising: removing ([0072]-[0073]) the first isolation layer (FIG. 2h, items 132 and 280) remaining on the surface (FIG. 2h item 210 of peripheral region) of the peripheral area (FIG. 2h, item 280 in peripheral region) to expose the surface (FIG. 2j item 210 of peripheral region) of the peripheral area (FIG. 2j, item 280 in peripheral region), after (FIG. 2j is after FIG. 2h) the sidewall (FIG. 2h, sidewall of top half of item 148) of the first word line insulating layer (FIG. 2h, top half of item 148) is exposed.
Response to Arguments
Applicant's arguments filed July 12, 2025 have been fully considered but they are not persuasive.
On page 9 of applicant’s remarks, applicant appears to argue that Kim et al does not disclose a top surface of the first word line is not higher than a top surface of the peripheral area.
Examiner respectfully disagrees.
Examiner points out that FIG. 7 of Kim discloses applicant’s claim 1 language.
Applicant further argues that Kim et al does not disclose the top surface of the first word line is not higher than that of the peripheral area in the third direction.
Examiner respectfully disagrees.
Examiner points out that FIG. 7 of Kim discloses applicant’s claim 1 language.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.B./ Examiner, Art Unit 2815
/MONICA D HARRISON/ Primary Examiner, Art Unit 2815