DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 September 2025 has been entered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 8 - 11, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Ning et al. (US 20150162285 A1, hereinafter Ning), and further in view of Cook et al. (US 6022791 A, hereinafter Cook).
Regarding independent claim 1, Ning discloses a semiconductor chip comprising:
an integrated circuit disposed in a device region;
Ning (Fig 5 ; para [0054]) discloses a device region 201 which includes semiconductor devices that are part of the integrated circuit made in the form of a semiconductor chip (para [0003 – 0005]).
and a chip guard disposed in a chip sealing region that is an outer portion of the device region, wherein the chip guard comprises: a first metal layer disposed over a substrate;
Ning (Fig 5 ; para [0054]) further discloses a first seal ring structure 210 (i.e. part of a “chip guard”) which is disposed in seal ring region 202 (i.e. “chip sealing region”) that surrounds (i.e. is an outer portion) of the device region 201. Fig 8 (para [0067]) and Fig 10 (para [0072]) show a more detailed view of the lowest two connection layers in first seal ring structure 210 in Fig 5, and it is seen from Fig 8 that the first connection layer 204A (i.e. “first metal layer”) is disposed over substrate 200.
a first planarization insulating layer surrounding a side surface of the first metal layer;
Ning discloses (Fig 8 ; para [0065-0067]) a first planarization insulating layer 203a surrounding a side surface of the first metal layer 204A;
an interlayer insulating layer disposed on the first metal layer and the first planarization insulating layer;
Fig 8 (para [0067]) further shows a dielectric 203b (i.e. “interlayer insulating layer”) which is formed on the connection layer 204A (i.e. “first metal layer”) and the first planarization insulating layer 203a ;
a second metal layer disposed on the interlayer insulating layer;
Fig 10 (para [0072]) shows a connection layer 204B (i.e. “second metal layer”) which is formed over dielectric 203b (i.e. “interlayer insulating layer”).
a contact pattern and a barrier pattern laterally adjacent to each other, both extending from the same second metal layer in a direction toward the substrate, wherein the contact pattern is connected to the first metal layer,
Ning discloses the recitation of the preceding claim element in Fig 5 (para [0054-0058]). An annotated Fig 5 is reproduced below that indicates salient features. As seen in the annotated Fig 5 below, Ning discloses :
PNG
media_image1.png
409
708
media_image1.png
Greyscale
a contact pattern (i.e. “Contact Pattern”: multiple 222 shapes between first (1st) and second (2nd) metal layers) and a barrier pattern (i.e. “Barrier Pattern”: multiple 205 shapes connected to 2nd metal layer) laterally adjacent to each other, both extending from the same second metal layer (“same 2nd metal layer” in below Fig 5) in a direction (i.e. vertical) toward the substrate 200, wherein the contact pattern (“Contact Pattern” in below Fig 5) is connected to the first metal layer (“First Metal Layer” in below Fig 5),
wherein the barrier pattern extends through the interlayer insulating layer into the first planarization insulating layer, and is laterally spaced apart from the first metal layer.
Ning further discloses (Fig 10 ; para [0067, 0072] ) wherein the barrier pattern (i.e. multiple 205 shapes each connected to a 2nd metal layer shape 204B) extends through the interlayer insulating layer 203b into the first planarization insulating layer 203a, and is laterally spaced apart from the first metal layer 204A.
Ning does not explicitly disclose the contact pattern and the barrier pattern are physically connected by the same second metal layer.
However, in the same field of endeavor, Cook discloses in Cook FIG. 7C and associated text the contact pattern and the barrier pattern are physically connected by the same second metal layer (M4 and/or V3 in the left portion of interconnected rings 68, corresponding to a contact pattern, is physically connected to the right portion of interconnected rings 68, corresponding to a barrier pattern, through second metal layer V4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor chip of Ning with the physically connected contact and barrier patterns of Cook to provide a semiconductor chip with increased resistance to crack propagation (Cook col 4: lines 66-67).
Regarding dependent claim 3, Ning, as modified by Cook, discloses the semiconductor chip of claim 1, wherein
the barrier pattern is disposed farther from the device region than the contact pattern.
As seen in Fig 5, the “barrier pattern” 205 is disposed farther from device region 201 than the “contact pattern” 220.
Regarding dependent claim 4, Ning, as modified by Cook, discloses the semiconductor chip of claim 1, wherein
a bottom surface of the barrier pattern is disposed closer to the substrate than an upper surface of the first metal layer.
As seen in Fig 10, the bottom surface of contact plug 205 (i.e. “barrier pattern”) extending from the “second metal layer” 204B is disposed closer to the substrate 200 than an upper surface of the “first metal layer” 204A.
Regarding dependent claim 8, Ning, as modified by Cook, discloses the semiconductor chip of claim 1 wherein
the chip guard further comprises:
a second planarization insulating layer surrounding a side surface of the second metal layer.
Fig 10 further shows that dielectric layer 203b (i.e. “second planarization insulating layer”) surrounds a side surface of metal layer 204B (i.e. “second metal layer”).
Regarding dependent claim 9, Ning, as modified by Cook, discloses the semiconductor chip of claim 8 wherein
the barrier pattern extends from the second metal layer to reach inside the first planarization insulating layer.
It is seen in Fig 10 that the conductive plug 205 (i.e. “barrier pattern”) extends from metal layer 204B (i.e. “second metal layer”) to reach inside dielectric layer 203a (i.e. “first planarization insulating layer”).
Regarding dependent claim 10, Ning, as modified by Cook, discloses the semiconductor chip of claim 1 wherein
the first metal layer comprises one of copper (Cu) and tungsten (W), wherein the second metal layer comprises one of copper (Cu) and aluminum (Al), and wherein the barrier pattern comprises one of copper (Cu) and tungsten (W).
Ning, as modified by Cook, (Fig 2 ; para [0036]) discloses the choices of copper, tungsten, and aluminum for fabricating various metallic components of first seal ring structure 210 which includes “first metal layer” 204a, “second metal layer” 204a, and the “barrier pattern” composed of conductive plugs 205.
Regarding dependent claim 11, Ning, as modified by Cook, discloses the semiconductor chip of claim 1, wherein
wherein the chip guard further comprises: a lower metal layer disposed between the first metal layer and the substrate;
Fig 4 shows a specific implementation of first seal ring structure 210 which indicates a connection layer 204 (i.e. “lower metal layer”) that is disposed between substrate 200 and the first connection layer 204a (i.e. “first metal layer”) shown as two horizontally co-planar metal stubs in the figure.
Examiner notes that the specific embodiment of seal ring structure 210 covered by Fig 4 is a slightly different variant of that described by Fig 5 which was referred to in claim 1. The salient difference between the two embodiments is only in the lowest connection layer (i.e. “metal layer”). Hence, the embodiment in Fig 4 also discloses the elements of claim 1 in the instant application with the pertinent difference being the specific references of “a first metal layer” and “a second metal layer” in claim 1. For structure 210 in Fig 5, these referred to the two lowest layers 204a in the four-layer metal stack, where “lowest” is with respect to substrate 200. However, for structure 210 in Fig 4, the four-layer metal stack is labeled differently. The lowest layer 204 closest to substrate 200 is referred to “lower metal layer”; the next higher layer 204a is now the “first metal layer” followed by the “second metal layer” disposed over the “first metal layer”.
a first lower contact pattern connecting the lower metal layer to the substrate;
Fig 4 shows conductive plugs 205 (i.e. “first lower contact pattern”) connecting the “lower metal layer” 204 to substrate 200.
and a second lower contact pattern connecting the first metal layer to the lower metal layer.
Fig 4 further shows conductive plugs 205a (i.e. “second lower contact pattern”) connecting the two horizontally co-planar stubs of “the first metal layer” 204a to “lower metal layer” 204.
Regarding independent claim 21, Ning discloses a semiconductor chip comprising:
an integrated circuit disposed in a device region;
Ning (Fig 3 ; para [0027]) discloses a device region 201 which includes semiconductor devices which are part of the integrated circuit made in the form of a semiconductor chip (para [0003 – 0005]).
and a chip guard disposed in a chip sealing region that is an outer portion of the device region, wherein the chip guard comprises: a plurality of metal layers disposed over a substrate;
Ning (Fig 4 : para [0052] further discloses a first seal ring structure 210 (i.e. part of a “chip guard”) which is disposed in seal ring region 202 (i.e. “chip sealing region”) that surrounds (i.e. is an outer portion) of the device region 201. Fig 4 shows four different connection layers: lowest connection layer 204 and three other connections layers each represented by reference number 204a. The connection layers represent “a plurality of metal layers” disposed over substrate 200.
at least one interlayer insulating layer disposed between the plurality of metal layers;
As seen in Fig 4, there is an “interlayer insulating layer” between each pair of “metal layers”. The insulating layers are generically represented by dielectric layer 203.
and a contact pattern and a barrier pattern laterally adjacent to each other, both extending from the same metal layer among the plurality of metal layers in a direction toward the substrate, wherein the contact pattern is connected to another metal layer among the plurality of metal layers, wherein the barrier pattern is laterally spaced apart from the another metal layer.
The preceding claim element is similar to that recited by claim 1 except that the contact pattern and barrier pattern are described across multiple layers. Ning discloses this precise structure in the below annotated Fig 5: It is evident from the below figure that the contact pattern and barrier pattern extend across multiple metal layers. Specifically, the below figure shows a total of four metal layers each of which include the contact and barrier patterns recited by the preceding claim element.
PNG
media_image1.png
409
708
media_image1.png
Greyscale
Ning does not explicitly disclose the contact pattern and the barrier pattern are physically connected by the same metal layer.
However, in the same field of endeavor, Cook discloses in Cook FIG. 7C and associated text the contact pattern and the barrier pattern are physically connected by the same metal layer (M4 and/or V3 in the left portion of interconnected rings 68, corresponding to a contact pattern, is physically connected to the right portion of interconnected rings 68, corresponding to a barrier pattern, through second metal layer V4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor chip of Ning with the physically connected contact and barrier patterns of Cook to provide a semiconductor chip with increased resistance to crack propagation (Cook col 4: lines 66-67).
Regarding dependent claim 22, Ning, as modified by Cook, discloses the semiconductor chip of claim 21, wherein the barrier pattern is disposed to penetrate the at least one interlayer insulating layer to extend in the substrate direction.
As seen in Ning FIG. 4, conductive plug 205 (i.e. “barrier pattern”) penetrates the interlayer dielectric 203 (i.e. “interlayer insulating layer”) between the top two metal layers 204a in a manner which extends toward substrate 200.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ning, and further in view of Cook and Pan et al. (US 6412786 B1, hereinafter Pan).
Regarding dependent claim 5, Ning, as modified by Cook, discloses the semiconductor chip of claim 1. Ning, as modified by Cook, does not expressly teach: wherein the bottom surface of the barrier pattern is disposed closer to the substrate than a bottom surface of the first metal layer.
However, in the same field of endeavor, Pan discloses the structure (Fig 3 ; col 3: lines 7 – 53) recited by this dependent claim. For example, the bottom surface of metal structure 39 (i.e. “barrier pattern”) associated with metal ring 37 is disposed closer to substrate 30 than a bottom surface of metal ring 36 (i.e. “first metal layer”).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that modifying Ning and Cook’s “barrier pattern” implementation to extend its bottom surface closer to substrate, in a manner similar to the structure taught by Pan, would be beneficial for the purpose of increased mechanical strength (Ning: para [0026]) and improved protection of functional circuits from the propagation of stress resulting from dicing the wafer (Pan: col 1: lines 57 – 59).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Ning, and further in view of Cook and Werking et al. (US 6709954 B1, hereinafter Werking).
Regarding dependent claim 6, Ning, as modified by Cook, discloses the semiconductor chip of claim 1. Ning, as modified by Cook, does not expressly teach:
wherein the interlayer insulating layer comprises: a metal capping layer covering the upper surface of the first metal layer;
However, in the same field of endeavor, Werking discloses details of metal and dielectric layers for a semiconductor component that includes a crack arrest structure (i.e. “barrier pattern”) similar to that taught by Ning, as modified by Cook. Werking’s Fig 11 (col 6: lines 1 – 19) further discloses an “interlayer insulating layer” comprising a capping layer 74 (“metal capping layer”) covering the upper surface of metal layer 67 (i.e. “first metal layer”);
and an intermetallic insulating layer disposed on the metal capping layer.
Dielectric 76 (i.e. “an intermetallic insulating layer”) is disposed on capping layer 74 (“metal capping layer”).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to modify Ning and Cook’s “barrier pattern” implementation to include metal capping layers, in a manner similar to the structure taught by Werking, for the purpose of reducing copper contamination during fabrication (Werking: col 3: lines 10 – 18).
Regarding dependent claim 7, Ning, as modified by Cook and Werking, discloses the semiconductor chip of claim 6 wherein
the metal capping layer and the intermetallic insulating layer are made of different materials from each other.
Werking (col 6: lines 16 – 19) discloses that the “metal capping layer” 74 uses a different dielectric material compared to the “intermetallic insulating layer” 76.
Claims 12 – 18 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ning, and further in view of Cook, Chang et al. (US 20220262743 A1, hereinafter Chang), and Sinha et al. (US 20200373250 A1, hereinafter Sinha).
Regarding dependent claim 12, Ning, as modified by Cook, discloses the semiconductor chip of claim 1, however, Ning, as modified by Cook, does not expressly teach any of these recited elements of claim 12:
wherein the chip guard further comprises: an insulating protection structure disposed over the second metal layer;
a barrier trench passing through the insulating protection structure and formed in a lateral direction of the second metal layer;
and a metal barrier layer disposed on at least a sidewall surface and bottom surface of the barrier trench.
However, in the same field of endeavor, Chang’s semiconductor chip in Fig 6 discloses an “insulation protection structure” comprising dielectric layers 170, 160, and 150 that is disposed on 110 (para [0031]), which represents the total vertical extent of circuits 120. This “insulation protection structure” is disposed over the entire chip including the scribe region (i.e. encompasses “chip guard”). Note that the highest metal layer (“second metal layer”) in Ning’s seal region 202 (Ning: Fig 10) is interpreted as corresponding to the highest metal layer used in circuits 120 of Chang’s semiconductor chip (Chang: Fig 6). Hence, the “insulation protection structure” represented by Chang’s dielectric layers 170, 160, and 150 is seen to be disposed on the “second metal layer”.
Chang (Fig 6) further discloses a trench 172 (i.e. “barrier trench”) passing through dielectric layers 170, 160, and 150 (“the insulation protection structure”) and underlying structures (i.e. metal layers, etc.) that exist as part of the vertical extent 110 for Chang’s semiconductor chip. The trench 172 exists in the scribe region, which is outside the circuits region 120. Chang does not provide details on the underlying structures penetrated by trench 172 (i.e. “barrier trench”).
However, in the same field of endeavor, Sinha (Fig 5) discloses three trenches 114 (i.e. “barrier trenches”) each of which penetrate metal interconnects 102, which can be interpreted as the three highest interconnect levels in the chip. For example, the highest metal layer in metal interconnects 102 can be interpreted as “second metal layer” while the middle metal layer in metal interconnects 102 can be interpreted as the “first metal layer” thus staying consistent with Ning’s interpretation of metal layers in Fig 10 as described for claim 1. As seen in Sinha’s Fig 5, the leftmost trench 114 (i.e. “barrier trench”) is formed in a lateral direction of the highest metal layer (“second metal layer”) in metal interconnects 102.
Chang (Fig 6 ; para [0058]) further discloses a crack-blocking layer 182 (“barrier layer”) that is formed on the sidewall surface and bottom surface of trench 172 (i.e. “barrier trench”). Chang further discloses (para [0047], [0037]) that the crack-blocking layer 182 can be a conductive layer (i.e. “metal barrier layer”) such as Aluminum.
Ning and Cook’s “barrier pattern” is a clearly separate structure from the “barrier trench” as taught by Chang and Sinha. The cited prior art presents both of these approaches as viably preventing the propagation of cracks from the sawing region to the device region. There is no apparent indication in the cited prior art which would prevent these two approaches from being used together assuming the customary compliance with layout rules for a given technology node. The predictable outcome to combining these two schemes is the likelihood of an even more robust crack-blocking solution.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that Ning and Cook’s “barrier pattern” crack-blocking approach could be seamlessly combined with the “barrier trench” crack-blocking scheme taught by Chang and Sinha for the purpose of achieving an even more robust solution for further scaling of process technology; for example, Sinha (para[0003]) discloses that the issue of crack propagation gets worse for low-k dielectric materials used in advanced semiconductor processes.
Regarding dependent claim 13, Ning, as modified by Cook, Chang, and Sinha, discloses the semiconductor chip of claim 12, wherein the bottom surface of the barrier trench is disposed to be spaced apart from an upper surface of the second metal layer.
As seen in Sinha’s Fig 5, the bottom surface of the leftmost trench 114 (i.e. “barrier trench”) is spaced apart from an upper surface of the highest metal layer (i.e. “second metal layer”) in metal interconnects 102.
Regarding dependent claim 14, Ning, as modified by Cook, Chang, and Sinha, discloses the semiconductor chip of claim 13, wherein the bottom surface of the barrier trench is positioned closer to the substrate than the upper surface of the second metal layer.
It is seen from Sinha’s Fig 5 that the bottom surface of “barrier trench” 114 is positioned closer to substrate 108 than the upper surface of the “second metal layer” (highest metal layer in metal interconnects 102).
Regarding dependent claim 15, Ning, as modified by Cook, Chang, and Sinha, discloses the semiconductor chip of claim 12, wherein the barrier trench is positioned farther from the device region than the second metal layer.
The relative location of the “barrier trench” can be seen in Sinha’s Fig 5. The figure does not explicitly label the scribe or device regions. However, Sinha’s Fig 1A explaining crack propagation provides context. As taught by Sinha in para [0003], the cracks originate during the wafer dicing process which physically occurs in the scribe region between die. As seen in Fig 1A, the initial crack 152 originates on the right side of chip (i.e. note “Initial Crack Length”). Hence, it is reasonable to interpret Fig 5 as portraying the scribe region on the rightmost portion of the figure and the device region on the leftmost portion of the figure. It is thus seen that the leftmost “barrier trench” 114 is positioned farther from the device region than metal interconnects 102, which includes the “second metal layer”.
Regarding independent claim 16, Ning discloses a semiconductor chip comprising:
an integrated circuit disposed in a device region;
Ning (Fig 5 ; para [0054]) discloses a device region 201 which includes semiconductor devices that are part of the integrated circuit made in the form of a semiconductor chip (para [0003 – 0005]).
and a chip guard disposed in a chip sealing region that is an outer portion of the device region, wherein the chip guard comprises: a first metal layer disposed over a substrate;
Ning (Fig 5 ; para [0054]) further discloses a first seal ring structure 210 (i.e. part of a “chip guard”) which is disposed in seal ring region 202 (i.e. “chip sealing region”) that surrounds (i.e. is an outer portion) of the device region 201. Fig 8 (para [0067]) and Fig 10 (para [0072]) show a more detailed view of the lowest two connection layers in first seal ring structure 210 in Fig 5, and it is seen from Fig 8 that the first connection layer 204A (i.e. “first metal layer”) is disposed over substrate 200.
a planarization insulating layer surrounding a side surface of the first metal layer;
Ning discloses (Fig 8 ; para [0065-0067]) a planarization insulating layer 203a surrounding a side surface of the first metal layer 204A;
an interlayer insulating layer disposed on the first metal layer and the planarization insulating layer;
Ning FIG. 8 (para [0067]) further shows a dielectric 203b (i.e. “interlayer insulating layer”) which is formed on the connection layer 204A (i.e. “first metal layer”) and the planarization insulating layer 203a ;
a second metal layer disposed on the interlayer insulating layer;
Ning FIG. 10 (para [0072]) shows a connection layer 204B (i.e. “second metal layer”) which is formed over dielectric 203b (i.e. “interlayer insulating layer”).
a contact pattern and a barrier pattern laterally adjacent to each other, both extending from the same second metal layer in a direction toward the substrate;
Ning discloses the recitation of the preceding claim element in Fig 5 (para [0054-0058]). An annotated Fig 5 is reproduced below that indicates salient features. As seen in the annotated Fig 5 below, Ning discloses:
PNG
media_image1.png
409
708
media_image1.png
Greyscale
a contact pattern (i.e. “Contact Pattern”: multiple 222 shapes between first (1st) and second (2nd) metal layers) and a barrier pattern (i.e. “Barrier Pattern”: multiple 205 shapes connected to 2nd metal layer) laterally adjacent to each other, both extending from the same second metal layer (“same 2nd metal layer” in below Fig 5) in a direction (i.e. vertical) toward the substrate 200 ;
Ning does not explicitly teach:
an insulating protection disposed on the second metal layer.
However, in the same field of endeavor, Chang’s semiconductor chip in Fig 6 discloses an “insulation protection structure” comprising dielectric layers 170, 160, and 150 that is disposed on 110 (Chang: para [0031]), which represents the total vertical extent of circuits 120. Note that the “second metal layer” recited by the claim can be interpreted as corresponding to the highest metal layer used in circuits 120 of Chang’s semiconductor chip (Chang: Fig 6). Hence, the “insulation protection structure” represented by Chang’s dielectric layers 170, 160, and 150 is seen to be disposed on the “second metal layer”.
a barrier trench penetrating the insulating protection structure and formed in a lateral direction of the second metal layer;
Chang (Fig 6) discloses a trench 172 (i.e. “barrier trench”) penetrating dielectric layers 170, 160, and 150 (“the insulation protection structure”) and underlying structures (i.e. metal layers, etc.) that exist as part of the vertical extent 110 for Chang’s semiconductor chip. The trench 172 exists in the scribe region, which is outside the circuits region 120. Note that Chang uses the term “substrate” to describe 110, however, this is much broader than the narrow definition of “substrate” which only refers to the underlying silicon substrate. More context on Chang’s substrate 110 can be found in para [0027 – 0028, 0031] and details on trench 172 can be found in para [0040 – 0041].
Chang does not explicitly teach the barrier trench as being formed in a lateral direction of the second metal layer;
However, in the same field of endeavor, Sinha discloses (Fig 5 ; para [0038,0049]) the leftmost trench 114 (i.e. “barrier trench”) is formed in a lateral direction of the highest metal layer (“second metal layer”) in metal interconnects 102.
and a metal barrier layer disposed on at least a sidewall surface and bottom surface of the barrier trench,
Chang (Fig 6 ; para [0058]) discloses a crack-blocking layer 182 (“barrier layer”) that is formed on the sidewall surface and bottom surface of trench 172 (i.e. “barrier trench”). Chang further discloses (para [0047], [0037]) that the crack-blocking layer 182 can be a conductive layer (i.e. “metal barrier layer”) such as Aluminum.
wherein a bottom surface of the barrier trench is disposed to be spaced apart from an upper surface of the second metal layer,
As seen in Sinha’s Fig 5, the bottom surface of the leftmost trench 114 (i.e. “barrier trench”) is spaced apart from an upper surface of the highest metal layer (i.e. “second metal layer”) in metal interconnects 102.
wherein the contact pattern is connected to the first metal layer,
Ning discloses (annotated Fig 5 below ; para [0054-0058]) wherein the contact pattern (“Contact Pattern” in below Fig 5) is connected to the first metal layer (“First Metal Layer” in below Fig 5),
PNG
media_image1.png
409
708
media_image1.png
Greyscale
wherein the barrier pattern extends through the interlayer insulating layer into the planarization insulating layer, and is laterally spaced apart from the first metal layer,
Ning further discloses (Fig 10 ; para [0067, 0072] ) wherein the barrier pattern (i.e. multiple 205 shapes each connected to a 2nd metal layer shape 204B) extends through the interlayer insulating layer 203b into the first planarization insulating layer 203a, and is laterally spaced apart from the first metal layer 204A.
wherein the barrier trench is positioned farther from the device region than the second metal layer.
The relative location of the “barrier trench” can be seen in Sinha’s Fig 5. The figure does not explicitly label the scribe or device regions. However, Sinha’s Fig 1A explaining crack propagation provides context. As taught by Sinha in para [0003], the cracks originate during the wafer dicing process which physically occurs in the scribe region between die. As seen in Fig 1A, the initial crack 152 originates on the right side of chip (i.e. note “Initial Crack Length”). Hence, it is reasonable to interpret Fig 5 as portraying the scribe region on the rightmost portion of the figure and the device region on the leftmost portion of the figure. It is thus seen that the leftmost “barrier trench” 114 is positioned farther from the device region than metal interconnects 102, which includes the “second metal layer”.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that Ning and Cook’s “barrier pattern” crack-blocking approach could be seamlessly combined with the “barrier trench” crack-blocking scheme taught by Chang and Sinha for the purpose of achieving an even more robust solution for further scaling of process technology; for example, Sinha (para[0003]) discloses that the issue of crack propagation gets worse for low-k dielectric materials used in advanced semiconductor processes.
Ning does not explicitly disclose the contact pattern and the barrier pattern are physically connected by the same second metal layer.
However, in the same field of endeavor, Cook discloses in Cook FIG. 7C and associated text the contact pattern and the barrier pattern are physically connected by the same second metal layer (M4 and/or V3 in the left portion of interconnected rings 68, corresponding to a contact pattern, is physically connected to the right portion of interconnected rings 68, corresponding to a barrier pattern, through second metal layer V4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor chip of Ning with the physically connected contact and barrier patterns of Cook to provide a semiconductor chip with increased resistance to crack propagation (Cook col 4: lines 66-67).
Regarding dependent claim 17, Ning, as modified by Cook, Chang, and Sinha, discloses the semiconductor chip of claim 16 wherein the barrier trench is positioned farther from the device region than the second metal layer.
The relative location of the “barrier trench” can be seen in Sinha’s Fig 5. The figure does not explicitly label the scribe or device regions. However, Sinha’s Fig 1A explaining crack propagation provides context. As taught by Sinha in para [0003], the cracks originate during the wafer dicing process which physically occurs in the scribe region between die. As seen in Fig 1A, the initial crack 152 originates on the right side of chip (i.e. note “Initial Crack Length”). Hence, it is reasonable to interpret Fig 5 as portraying the scribe region on the rightmost portion of the figure and the device region on the leftmost portion of the figure. It is thus seen that the leftmost “barrier trench” 114 is positioned farther from the device region than metal interconnects 102, which includes the “second metal layer”.
Regarding dependent claim 18, Ning, as modified by Cook, Chang, and Sinha, discloses the semiconductor chip of claim 16, wherein
the bottom surface of the barrier trench is positioned closer to the substrate than the upper surface of the second metal layer.
It is seen from Sinha’s Fig 5 that the bottom surface of “barrier trench” 114 is positioned closer to substrate 108 than the upper surface of the “second metal layer” (highest metal layer in metal interconnects 102).
Regarding dependent claim 23, Ning, as modified by Cook, discloses the semiconductor chip of claim 21 but does not expressly teach any of these recited elements:
wherein the chip guard further comprises: an insulating protection structure disposed over the plurality of metal layers;
a barrier trench penetrating the insulating protection structure to be formed in a lateral direction of the plurality of metal layers;
and a metal barrier layer disposed along at least a sidewall surface of the barrier trench.
However, in the same field of endeavor, Chang’s semiconductor chip in Fig 6 discloses an “insulation protection structure” comprising dielectric layers 170, 160, and 150 that is disposed on 110 (para [0031]), which represents the total vertical extent of circuits 120. This “insulation protection structure” is disposed over the entire chip including the scribe region (i.e. encompasses “chip guard”). Note that the highest metal layer (“second metal layer”) in Ning’s seal region 202 (Ning: Fig 10) is interpreted as corresponding to the highest metal layer used in circuits 120 of Chang’s semiconductor chip (Chang: Fig 6). Hence, the “insulation protection structure” represented by Chang’s dielectric layers 170, 160, and 150 is seen to be disposed on “the plurality of metal layers”, which specifically includes Ning’s “second metal layer” as the highest metal layer.
Chang (Fig 6) further discloses a trench 172 (i.e. “barrier trench”) penetrating through dielectric layers 170, 160, and 150 (“the insulation protection structure”) and underlying structures (i.e. metal layers, etc.) that exist as part of the vertical extent 110 for Chang’s semiconductor chip. The trench 172 exists in the scribe region, which is outside the circuits region 120. Chang does not provide details on the underlying structures penetrated by trench 172 (i.e. “barrier trench”).
However, in the same field of endeavor, Sinha (Fig 5) discloses three trenches 114 (i.e. “barrier trenches”) each of which penetrate metal interconnects 102, which can be interpreted as the three highest interconnect levels in the chip. For example, the highest metal layer in metal interconnects 102 can be interpreted as “second metal layer” while the middle metal layer in metal interconnects 102 can be interpreted as the “first metal layer” thus staying consistent with Ning’s interpretation of metal layers in Fig 10 as described for claim 1. As seen in Sinha’s Fig 5, the leftmost trench 114 (i.e. “barrier trench”) is formed in a lateral direction of the plurality of metal layers encompassed by metal interconnects 102.
Chang (Fig 6 ; para [0058]) further discloses a crack-blocking layer 182 (“barrier layer”) that is formed along at least a sidewall surface of trench 172 (i.e. “barrier trench”). Chang further discloses (para [0047], [0037]) that the crack-blocking layer 182 can be a conductive layer (i.e. “metal barrier layer”) such as Aluminum.
Ning and Cook’s “barrier pattern” is a clearly separate structure from the “barrier trench” as taught by Chang and Sinha. The cited prior art presents both of these approaches as viably preventing the propagation of cracks from the sawing region to the device region. There is no apparent indication in the cited prior art which would prevent these two approaches from being used together assuming the customary compliance with layout rules for a given technology node. The predictable outcome to combining these two schemes is the likelihood of an even more robust crack-blocking solution.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that Ning and Cook’s “barrier pattern” crack-blocking approach could be seamlessly combined with the “barrier trench” crack-blocking scheme taught by Chang and Sinha for the purpose of achieving an even more robust solution for further scaling of process technology; for example, Sinha (para[0003]) discloses that the issue of crack propagation gets worse for low-k dielectric materials used in advanced semiconductor processes.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
Stamper (US5851903), another version of a trench-based crack-stop structure.
Narayan (US6486526), a crack-stop structure for preventing fuse blow damage.
Daubenspeck (US2005/0026397), another version of a trench-based crack-stop structure.
Inohara (US2008/0099884), another version of a crack-stop structure similar to the applicant’s “barrier pattern”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights