DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/3/2026 have been fully considered but they are not persuasive.
Applicant states that Gardner fails to teach the limitation of newly amended claim 1, specifically “a channel structure comprising a single crystal transition metal dichalcogenide (TMD) material,” and “a dielectric layer on a top of the channel structure, wherein the dielectric laver includes high-k dielectric material, the high-k dielectric material having ends in vertical alignment with ends of the single crystal TMD material”.
As Applicant states on page 6 of Remarks, it is their “understanding that Gardner discloses a TMD material layer 112/115 with includes a doped region 112 and an undoped region 115. A high-k dielectric layer 114a is on the undoped region 115 but not on the doped region of the TMD material layer 112/115”. Examiner respectfully disagrees with this reading. Though the Applicant correctly describes the high-k dielectric on the layer 115 but not the layer 112, the statement of the TMD material layer comprising both 112 and 115 is where the Examiner disagrees. Gardner teaches the channel 115 and the S/D 112 to be two separate features. More specifically, in [0083] Gardner teaches the etching of the semiconductor channel 315 to create indentations for the formation of S/D regions 112 in said indentations. The remaining 315 after the etching step is the TMD channel 115. This channel and the high-k dielectric material (layer 114a) have their ends in vertical alignment, as required in the newly amended independent claim 1. So while layer 315 extended beyond the ends of where the high-k dielectric 114a is formed, it is incorrect to assert the final combination of 112/115 is the TMD material layer, as 112 is a different feature (the source/drain regions).
Applicant states on page 7 of Remarks that they understand Gardner to disclose the TMD material layer 112/115 as extending laterally beyond ends of the high-k dielectric layer 114a, but that Gardner fails to disclose the high-k dielectric layer 114a being in vertical alignment with ends of the TMD material layer 112/115. With the clarification on the distinction above between the TMD material layer 115 and the S/D 112, Examiner argues that Gardner in fact teaches the high-k dielectric layer 114a being in vertical alignment with ends of the TMD material layer 115, as will be further stated in the rejection to follow.
Applicant has not responded to pending specification objections and drawing objections, as such they will be reiterated below. With the lack of correction, the rejection under U.S.C. 112(a) still stands and is repeated below.
As applicant has cancelled claims 16-25, the previous rejections of claims 19 and 24 under U.S.C. 112(b) are moot and are thus withdrawn.
Status of the Claims
Claims 1-4, 6-7, and 9-15 are pending in the application and are currently being examined. Claims 1-3, 6-7, 9, 11-13, and 15 have been amended. Claims 5, 8, and 16-25 have been canceled. No new claims have been added.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because they do not clearly depict the physical possibility of the steps to create the device. In particular, it is unknown how element 320 in Figs. 3B-3D can be formed on element 312 then etched as shown. If 320a and 320b are etched away, it is unclear how element 326 directly on the wafer is now in contact with element 312, or how the edges of the leftmost 326, 320, and 312 are all in line with each other in Fig. 3E. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The use of the terms “GPS”, “Wi-Fi”, “Bluetooth”, “LTE”, which are each a trade name or a mark used in commerce, has been noted in this application, this is not an exhaustive list. The terms should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 6-7, and 9-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for the final semiconductor device, does not reasonably provide enablement for the channels being coupled to the seed material. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims. The intermediate steps described in Figs. 3B-3E ([0031]-[0035] in the written specification) are unclear. One of ordinary skill in the art would not be able to make the device as described, as if 320a and 320b are etched away, it is unclear how element 326 directly on the wafer is now in contact with element 312, or how the edges of the leftmost 326, 320, and 312 are all in line with each other in Fig. 3E. The specification does not clear up this confusion in the related paragraphs.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “The transistor structure of claim 5”. This appears to be in error as claim 5 has been canceled in the amendment of 3/3/2026. For the purposes of examination, claim 6 will be interpreted to read “The transistor structure of claim 1”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6, 9-11, and 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gardner et al. (US 2023/0207397 A1, hereafter Gardner).
Regarding claim 1, in Fig. 1A of Gardner discloses a transistor structure comprising:
a channel structure (115, [0057]) comprising a single crystal transition metal dichalcogenide (TMD) material [0063]; and
a dielectric layer (114a, [0065]) on a top of the channel structure (115), wherein the dielectric layer (114a) includes a high-k dielectric material [0065], the high-k dielectric material (114a) having ends in vertical alignment with ends of the single crystal TMD material (115) (as depicted in Fig. 1A, layers 115 and 114a are in vertical alignment).
Regarding claim 6, Gardner teaches the transistor structure of claim 1. Gardner further discloses the single crystal TMD material does not include a growth boundary. This is the case because the TMD channel (115, [0057]) is single crystalline [0064]. As such, current flows through the channel uninhibited by any forms of discontinuity in the channel, making it have no bounds of growth as it exists throughout the channel length.
Regarding claim 9, Gardner teaches the transistor structure of claim 1. Fig. 1A of Gardner further discloses the dielectric layer (114a on top of 115, [0065]) is a first dielectric layer, and further comprising a second dielectric layer (114a on bottom of 115, [0065]) on a bottom of the channel structure (115, [0057]).
Regarding claim 10, Gardner teaches the transistor structure of claim 1. Fig. 1A of Gardner further discloses a metal layer (114b, [0065]) on top of the dielectric layer (114a, [0065]).
Regarding claim 11, Gardner teaches the transistor structure of claim 10. Fig. 1A of Gardner further discloses the dielectric layer (114a on top of 115, [0065]) is a first dielectric layer and wherein the channel structure (115, [0057]) is a first channel structure; and further comprising:
a second dielectric layer (131, [0058]) on top of the metal layer (114b, [0065]); and
a second channel structure (125, [0057]) on top of the second dielectric layer (131), wherein the second channel structure (125) is a single crystal material [0064].
Regarding claim 13, Gardner teaches the transistor structure of claim 1. Fig. 1A of Gardner further discloses a source (112 left side of channel 115, [0057]) coupled with a first edge of the channel structure (115, [0057]); and
a drain (112 right side of channel 115, [0057]) coupled with a second edge of the channel structure (115) opposite the first edge of the channel structure (115), wherein the first edge of the channel structure (115) and the second edge of the channel structure (115) are substantially perpendicular to the top of the channel structure (115).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 7, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Chueh et al. (US 2017/0088945 A1, hereafter Chueh).
Regarding claim 2, Gardner teaches the transistor structure of claim 1. Gardner is silent on an edge of the channel structure substantially perpendicular to the top of the channel structure, wherein a region of the channel structure proximate to the edge of the channel structure includes one or more particles of a seed material.
However, Chueh teaches a method of growing TMD layers from seeds. In Chueh, the efficiency of growing the TMD layer from a molybdenum transition metal, where Gardner is silent on the S/D material. The efficiency of growing the layer is below 100% [0058]. Therefore, one of ordinary skill in the art would know that when growing the TMD layer in Gardner, they would expect some of the seed material particles to exist throughout the layer, including at the edges as described in the present application.
Regarding claim 7, Gardner teaches the transistor structure of claim 1. Gardner is silent on the thickness of the TMD channel structures. However, Chueh teaches a method of growing TMD layers from seeds. These layers can be as thin as 1nm [0052], less than the 2.5nm required in the present application. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner to include the thickness as taught by Chueh in order to get a functioning device.
Regarding claim 12, Gardner teaches the transistor structure of claim 11. Gardner is silent on a region of the second channel structure proximate to an edge of the second channel structure substantially perpendicular to the top of the channel structure includes one or more particles of a seed material.
However, Chueh teaches a method of growing TMD layers from seeds. In Chueh, the efficiency of growing the TMD layer from molybdenum, where Gardner is silent on the S/D material. The efficiency of growing the layer is below 100% [0058]. Therefore, one of ordinary skill in the art would know that when growing the TMD layer in Gardner, they would expect some of the seed material particles to exist throughout the layer, including at the edges as described in the present application.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Jhan et al. (US 2023/0317852 A1, hereafter Jhan) and in further view of Farquhar et al. (US 2018/0230590 A1, hereafter Farquhar).
Regarding claim 3, Gardner teaches the transistor structure of claim 1. Gardner fails to disclose a bottom of the channel structure opposite the top of the channel structure includes one or more particles of a growth promoter material.
However, Jhan teaches a similar transistor structure in which the channel layer (2-D material layer, 110, [0022] can be multilayered and contain one or more particles of graphene (carbon) and TMDs [0022]. The graphene layer is also taught as being deposited on the seed layer, making it at the bottom of the TMD layer [0079] of the multilayered channel. The inclusion of the multilayering of the channel allows the semiconductor to have high electron mobility [0022]. Gardner in view of Jhan fails to explicitly teach the carbon (graphene) is a growth promoter.
Farquhar teaches a similar stack including graphene being used to promote the growth of a TMD layer [0109]-[0110]. As graphene is known to be conductive [0063], the TMD layer is able to be grown specifically with conductive properties as opposed to insulative [0109]-[0110]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner to have a multilayered channel, with graphene at the bottom as taught by Jhan to get the expected result of promoted TMD growth as taught by Farquhar [0109]-[0110].
Regarding claim 4, Gardner in view of Farquhar teach the transistor structure of claim 3. Gardner in view of Farquhar further disclose the growth promoter material includes a selected one or more of. carbon rings or sodium. In particular, Farquhar teaches the growth promoter to be graphene [0110].
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Chueh, and further in view of Sekiguchi (US 6,128,050).
Regarding claim 14, Gardner teaches the transistor structure of claim 13. Gardner is silent on the source includes a seed material.
However, Chueh teaches a method of growing TMD layers from seeds. In Chueh, the seed can comprise molybdenum [0049], which is known to be a source material, as taught by Sekiguchi (column 36 lines 14-17). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the source/seed material of Gardner to comprise molybdenum in order to have a functional device that allows for TMD layer growth.
Regarding claim 15, Gardner in view of Chueh and in further view of Sekiguchi teach the transistor structure of claim 14. Gardner in view of Chueh and in further view of Sekiguchi further teach the channel structure is grown from the seed material (as is the topic of Chueh).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892