DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 20 March 2026 is acknowledged. Claims 19 and 20 have been canceled. Claims 1, 5, 9, 11, and 16 have been amended. Claims 1-18, 21, and 22 are pending.
Examiner notes that Applicant has failed to properly identify amendments to the claims as required by 37 C.F.R. 1.121(c). For example, Applicant has underlined the limitation, “first U-shape,” in claim 1 despite this amendment not being an addition. See MPEP 714.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claims 7, 10-12, 17, and 21, “further comprising one or more interconnect structures electrically coupling one of the second epitaxial structures to one of the fourth epitaxial structures,” “wherein the second gate region is electrically isolated from the channel region with a first pair of the plurality of isolation regions, and the channel region is electrically isolated from the first gate region with a second pair of the plurality of isolation regions,” “wherein the first channel region is [ ] separated from isolation regions,” and, “wherein the second channel region has a lower boundary surrounded by the third gate region,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendments to the title were received on 20 March 2026. These amendments to the title are acceptable.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the subject matter of claims 3, 7, 10-12, 17, 21, and 22, “the second doping concentration being higher by at least 10% than the first doping concentration,” “further comprising one or more interconnect structures electrically coupling one of the second epitaxial structures to one of the fourth epitaxial structures,” “wherein the second gate region is electrically isolated from the channel region with a first pair of the plurality of isolation regions, and the channel region is electrically isolated from the first gate region with a second pair of the plurality of isolation regions,” “wherein the first channel region is [ ] separated from isolation regions,” “wherein the second channel region has a lower boundary surrounded by the third gate region,” and, “the second doping concentration being higher than the first doping concentration by at least 10%,” must find support in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 11-18, 21, and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 3 and 22 recite the limitations, “the second doping concentration being higher by at least 10% than the first doping concentration,” and, “the second doping concentration being higher than the first doping concentration by at least 10%,” respectively. These limitations are not supported by the disclosure as originally filed. The original disclosure is silent to any specific teaching providing support for the 10% value.
Claims 11 and 21 recite the limitation, “wherein the first channel region is [ ] separated from isolation regions.” This limitation is not supported by the disclosure as originally filed. As best understood by Examiner, the channel region (402) is in direct contact with isolation region (204).
Claims 12-18 are rejected for merely containing the flaws of the parent claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 10-18, 21, and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 17 recites the limitation, “further comprising one or more interconnect structures electrically coupling one of the second epitaxial structures to one of the fourth epitaxial structures.” It is unclear how one or more interconnect structures (1002, 1004, 1006, 1008, and 1010) electrically couple one of the second epitaxial structures (704) to one of the fourth epitaxial structures (714) when said fourth epitaxial structures are instead coupled to another epitaxial structure (710).
Claim 10 recites the limitation, “wherein the second gate region is electrically isolated from the channel region with a first pair of the plurality of isolation regions, and the channel region is electrically isolated from the first gate region with a second pair of the plurality of isolation regions.” It is unclear how the second gate region (802) is electrically isolated from the channel region (402) with a first pair of the plurality of isolation regions (204), and the channel region is electrically isolated from the first gate region (302) with a second pair of the plurality of isolation regions (204) when said second gate region is in direct physical and electrical contact with said channel region, and said channel region is in direct physical and electrical contact with said first gate region.
Claims 11 and 21 recite the limitation, “wherein the first channel region is [ ] separated from isolation regions.” It is unclear how the channel region (402) is separated from isolation regions (204) when said channel region is in direct contact with said isolation regions.
Claim 12 recites the limitation, “wherein the second channel region has a lower boundary surrounded by the third gate region.” It is unclear how the second channel region (406) has a lower boundary surrounded by the third gate region (404) when said third gate region only covers side surfaces of said second channel region.
Claims 13-16, 18, and 22 are rejected for merely containing the flaws of the parent claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 21 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 21 recites the limitation, “wherein the first channel region is buried within the substrate and separated from isolation regions to reduce flicker noise.” This recitation is identical to the recitation of claim 11, “wherein the first channel region is buried within the substrate and separated from isolation regions to reduce flicker noise,” from which the claim directly depends. Thus, claim 21, dependent from claim 11, fails to further limit independent claim 11.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-11, 13, 14, 18, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent Application Publication 2010/0207173, hereinafter Anderson ‘173) of record in view of Arthur et al. (US Patent Application Publication 2020/0105944, hereinafter Arthur ‘944).
With respect to claim 1, Anderson ‘173 teaches (FIG. 8) a semiconductor device substantially as claimed, comprising:
a substrate (8) ([0016]);
a first gate region (31 and 34) extending into the substrate (8) and having at least a portion of a first U-shape ([0025, 0028]);
a channel region (40 and 44) extending into the substrate (8) and having a second U-shape ([0021, 0025]); and
a second gate region (50 and 52) extending into the substrate (8) and having a well shape ([0021, 0029]);
wherein the first U-shape of the first gate region (31 and 34) surrounds the second U-shape of the channel region (40 and 44), the second U-shape surrounds the well shape of the second gate region (50 and 52) ([0016, 0019, 0021, 0025, 0028-0029]).
Thus, Anderson ‘173 is shown to teach all the features of the claim with the exception of the first gate region and the second gate region are applied with a common voltage.
However, Arthur ‘944 teaches (FIG. 3B) a JFET (80A) wherein a common voltage is applied to a first gate region (62A) and a second gate region (62B) to produce specific on-state operation conditions ([0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first gate region and the second gate region of Anderson ‘173 applied with a common voltage as taught by Arthur ‘944 to produce specific on-state operation conditions.
Further, applying a common voltage to the first gate region and the second gate region is a mere recitation of intended use. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. A claim containing a, “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus,” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 II.
With respect to claim 2, Anderson ‘173 teaches wherein the first gate region (31 and 34) has a first conductive type, the channel region (40 and 44) has a second conductive type opposite to the first conductive type, and the second gate region (50 and 52) has the first conductive type, thereby forming a junction field-effect-transistor ([0021, 0025, 0028-0029]).
With respect to claims 3 and 22, Anderson ‘173 and Arthur ‘944 teach the device as described in claims 2 and 11, but do not explicitly teach the additional limitations wherein the first gate region has a first doping concentration and the second gate region has a second doping concentration, the second doping concentration being higher by at least 10% than the first doping concentration; and wherein the first gate region has a first doping concentration and the second gate region has a second doping concentration, the second doping concentration being higher than the first doping concentration by at least 10%.
However, Anderson ‘173 teaches (FIG. 8) a first gate region (31 and 34) having a first doping concentration (e.g. 3×1015/cm-3; [0024]) and a second gate region (50 and 52) having a second doping concentration (e.g. 1×1021/cm-3; [0029]), the second doping concentration being higher by at least 10% than the first doping concentration ([0024, 0029]) as art-recognized dopant region concentrations for a JFET having a reduced on-resistance and an increased on-current ([0008]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05 I.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Anderson ‘173 and Arthur ‘944 wherein the first gate region has a first doping concentration and the second gate region has a second doping concentration, the second doping concentration being higher by at least 10% than the first doping concentration; and wherein the first gate region has a first doping concentration and the second gate region has a second doping concentration, the second doping concentration being higher than the first doping concentration by at least 10% as taught by Anderson ‘173 as art-recognized dopant region concentrations for a JFET having a reduced on-resistance and an increased on-current and because Anderson ‘173 teaches an obvious overlap in ranges.
With respect to claim 4, Anderson ‘173 teaches further comprising: a pair of first epitaxial structures (38) coupled to end portions of the first U-shape, respectively; a pair of second epitaxial structures (48) coupled to end portions of the second U-shape, respectively; and a third epitaxial structure (56 and 60) coupled to an end portion of the well shape ([0032-0036, 0040]).
With respect to claim 8, Anderson ‘173 teaches wherein the first gate region (31 and 34) and second gate region (50 and 52) are configured to collectively cause a depletion region along the channel region (40 and 44) ([0021, 0025, 0028-0029]).
With respect to claim 9, Anderson ‘173 teaches wherein the channel region (40 and 44) comprises a pair of first portions disposed on sides of the second gate region (50 and 52), and a second portion disposed below the second gate region ([0021, 0025, 0029]).
With respect to claim 10, Anderson ‘173 teaches further comprising a plurality of isolation regions (20A-20D) extending into the substrate (8), wherein the second gate region (50 and 52) is electrically isolated from the channel region (40 and 44) with a first pair (20A and 20B) of the plurality of isolation regions, and the channel region is electrically isolated from the first gate region (31 and 34) with a second pair (20C) of the plurality of isolation regions ([0019]).
With respect to claim 11, Anderson ‘173 teaches (FIG. 8) a semiconductor device substantially as claimed, comprising:
a first junction field-effect-transistor comprising:
a first gate region (31 and 34) extending into a substrate (8) and having a first conductive type ([0016, 0025, 0028]);
a first channel region (40 and 44) extending into the substrate (8) and having a second conductive type opposite to the first conductive type, wherein the first channel region has a lower boundary surrounded by the first gate region (31 and 34), wherein the first channel region is buried within the substrate and separated from isolation regions (20A-20D) to reduce flicker noise ([0016, 0019, 0021, 0025, 0028-0029]); and
a second gate region (50 and 52) extending into the substrate (8) and having the first conductive type, wherein the second gate region has a lower boundary surrounded by the first channel region (40 and 44) ([0021, 0029]).
Thus, Anderson ‘173 is shown to teach all the features of the claim with the exception of wherein the first gate region and the second gate region are applied with a common voltage.
However, Arthur ‘944 teaches (FIG. 3B) a JFET (80A) wherein a common voltage is applied to a first gate region (62A) and a second gate region (62B) to produce specific on-state operation conditions ([0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first gate region and the second gate region of Anderson ‘173 applied with a common voltage as taught by Arthur ‘944 to produce specific on-state operation conditions.
Further, applying a common voltage to the first gate region and the second gate region is a mere recitation of intended use. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. A claim containing a, “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus,” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 II.
With respect to claim 13, Anderson ‘173 teaches wherein the first gate region (31 and 34) and the first channel region (40 and 44) each have a U-shaped cross-section ([0021, 0025, 0028]).
With respect to claim 14, Anderson ‘173 teaches the device as described in claim 11 above, including the additional limitation further comprising: a pair of first epitaxial structures (38) coupled to end portions of the first gate region (31 and 34), respectively; a pair of second epitaxial structures (48) coupled to end portions of the first channel region (40 and 44), respectively; and a third epitaxial structure (56 and 60) coupled to an end portion of the second gate region (50 and 52) ([0032-0036, 0040]).
With respect to claim 18, Anderson ‘173 teaches wherein the first gate region (31 and 34) and second gate region (50 and 52) are configured to collectively cause a depletion region along the first channel region (40 and 44) ([0021, 0025, 0028-0029]).
With respect to claim 21, Anderson ‘173 teaches wherein the first channel region (40 and 44) is buried within the substrate (8) and separated from isolation regions (20A-20D) to reduce flicker noise ([0016, 0019, 0021, 0025]).
Claims 5, 6, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson ‘173 and Arthur ‘944 as applied to claims 1 and 14 above, and further in view of Reznicek et al. (US Patent Application Publication 2021/0288187, hereinafter Reznicek ‘187) of record.
With respect to claims 5 and 15, Anderson ‘173 and Arthur ‘944 teach the device as described in claims 1 and 14 above with the exception of the additional limitation further comprising: a plurality of nanostructures vertically spaced apart from one another; a gate structure wrapping around each of the plurality of nanostructures; and a pair of fourth epitaxial structures coupled to ends of each of the plurality of nanostructures, respectively, wherein the plurality of nanostructures are configured to be separated from isolation regions to reduce flicker noise.
However, Reznicek ‘187 teaches (FIG. 10) a gate-all-around (GAA) device comprising a plurality of nanostructures (130, 132, and 134) vertically spaced apart from one another; a gate structure (810, 820, 822, and 824) wrapping around each of the plurality of nanostructures; and a pair of fourth epitaxial structures (550) coupled to ends of each of the plurality of nanostructures ([0043, 0068, 0079]) that can be integrated into a circuit ([0026]) and controlled with less voltage and therefore less power consumption ([0009]). When the GAA device of Reznicek ‘187 is applied to the semiconductor device of Anderson ‘173, the plurality of nanostructures (130, 132, and 134 of Reznicek ‘187) would be configured to be separated from isolation regions (20A-20D of Anderson ‘173).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Anderson ‘173 and Arthur ‘944 further comprising: a plurality of nanostructures vertically spaced apart from one another; a gate structure wrapping around each of the plurality of nanostructures; and a pair of fourth epitaxial structures coupled to ends of each of the plurality of nanostructures, respectively, wherein the plurality of nanostructures are configured to be separated from isolation regions to reduce flicker noise as taught by Reznicek ‘187 to integrate into a circuit a GAA device that can be controlled with less voltage and therefore less power consumption.
With respect to claims 6 and 16, Anderson ‘173, Arthur ‘944, and Reznicek ‘187 teach wherein the first epitaxial structures (38 of Anderson ‘173), the second epitaxial structures (48 of Anderson ‘173), the third epitaxial structure (56 and 60 of Anderson ‘173), and the fourth epitaxial structures (550 of Reznicek ‘187) are concurrently formed in one or more epitaxial processes (Anderson ‘173, [0040]).
The expression, “concurrently formed in one or more epitaxial processes,” is taken to be a product-by-process limitation and is given limited patentable weight. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson ‘173, Arthur ‘944, and Reznicek ‘187 as applied to claims 5 and 15 above, and further in view of Or-Bach et al. (US Patent Application Publication 2021/0043607, hereinafter Or-Bach ‘607) of record.
With respect to claims 7 and 17, Anderson ‘173, Arthur ‘944, and Reznicek ‘187 teach the device as described in claims 5 and 15 above with the exception of the additional limitation further comprising one or more interconnect structures electrically coupling one of the second epitaxial structures to one of the fourth epitaxial structures.
However, Or-Bach ‘607 teaches an interconnect structure (2092) electrically coupling two devices (2022 and 2032) so that said devices may be interconnected in an integrated circuit ([0254]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Anderson ‘173, Arthur ‘944, and Reznicek ‘187 further comprising one or more interconnect structures electrically coupling one of the second epitaxial structures to one of the fourth epitaxial structures as taught by Or-Bach ‘607 so that a JFET(s) and a gate-all-around (GAA) device may be interconnected in an integrated circuit.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Anderson ‘173 and Arthur ‘944 as applied to claim 11 above, and further in view of Beasom (US Patent 4,729,008, hereinafter Beasom ‘008) of record.
With respect to claim 12, Anderson ‘173 and Arthur ‘944 teach the device as described in claim 11 above with the exception of the additional limitation further comprising: a second junction field-effect-transistor comprising: a third gate region extending into the substrate and having the second conductive type; a second channel region extending into the substrate and having the first conductive type, wherein the second channel region has a lower boundary surrounded by the third gate region; and a fourth gate region extending into the substrate and having the second conductive type, wherein the fourth gate region has a lower boundary surrounded by the second channel region.
However, Beasom ‘008 teaches (FIG. 11) a plurality of JFETs including a pJFET and an nJFET formed in a common substrate (100), wherein one such JFET (pJFET) comprises a third gate region (119 and 148) extending into the substrate and having the second conductive type; a second channel region (143) extending into the substrate and having the first conductive type, wherein the second channel region has a lower boundary surrounded by the third gate region; and a fourth gate region (146) extending into the substrate and having the second conductive type, wherein the fourth gate region has a lower boundary surrounded by the second channel region (col. 5, ln. 39 – col. 6, ln. 20) to form, for example, a high voltage integrated circuit (col. 1, ln. 10-11, 49-51) or any other circuit that may benefit from, for example, CMOS architecture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Anderson ‘173 and Arthur ‘944 further comprising: a second junction field-effect-transistor comprising: a third gate region extending into the substrate and having the second conductive type; a second channel region extending into the substrate and having the first conductive type, wherein the second channel region has a lower boundary surrounded by the third gate region; and a fourth gate region extending into the substrate and having the second conductive type, wherein the fourth gate region has a lower boundary surrounded by the second channel region as taught by Beasom ‘008 to form, for example, a high voltage integrated circuit or any other circuit that may benefit from, for example, CMOS architecture.
Response to Arguments
Applicant’s amendments to the claims are sufficient to overcome some of the objections to the drawings and the specification made in the non-final rejection filed 22 December 2025. Some of the objections to the drawings and the specification have been withdrawn. However, other objections to the drawings and the specification were unaddressed and are maintained as set forth in the above rejection.
Applicant’s amendments to the title are sufficient to overcome the objection to the title made in the non-final rejection filed 22 December 2025. The objection to the title has been withdrawn.
Applicant’s amendments to claim 9 are sufficient to overcome the objection to claim 9 made in the non-final rejection filed 22 December 2025. The objection to claim 9 has been withdrawn.
Applicant’s amendments to the claims are sufficient to overcome some of the 35 U.S.C. 112(a)&(b) rejections of claims 1-18, 20, and 21 made in the non-final rejection filed 22 December 2025. Some of the 35 U.S.C. 112(a)&(b) rejections of claims 1-18, 20, and 21 have been withdrawn. However, other 35 U.S.C. 112(a)&(b) rejections were unaddressed and are maintained as set forth in the above rejection.
Applicant's arguments filed 20 March 2026 with respect to the 35 U.S.C. 102(a)(1) rejection of claims 1 and 11 have been fully considered but they are not persuasive.
Applicant argues (remarks, p. 10) that no teaching or suggestion of such a U-shaped first gate region surrounding a U-shaped channel region which further surrounds a well region in Anderson ‘173 is found. Examiner respectfully disagrees.
Anderson ‘173 teaches (FIG. 8) a U-shaped first gate region (31 and 34) surrounding a U-shaped channel region (40 and 44) which further surrounds a well region (50 and 52) ([0016, 0019, 0021, 0025, 0028-0029]) as set forth in the above rejection.
Applicant’s arguments with respect to amended claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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