Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 3/13/2026 has been entered. Claims 1, 6, 11, 16 are amended. Claims 1 – 20 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 6, 11, 16 ( Currently Amended ) are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claims 1, 6, 11, 16, the original specification did not disclose “ … a single P-type conductive layer with a thickness, … the single P-type conductive layer with the thickness, … ”. Therefore, this limitation is new matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (Pub. No. 20210210388 A1), hereinafter Zhang, in view of Hsu (Pub. No. 20220093472 A1), hereinafter Hsu.
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Regarding Independent Claim 1 ( Currently Amended ), Zhang teaches an integrated circuit structure, comprising:
a first vertical arrangement ( Zhang, FIG. 9, 5; [0028], Structure 5 will represent a work function gate stack where more dipole diffusion takes place ) of horizontal nanowires ( Zhang, FIG. 9, 24; [0027], The nanosheet stack 20 can include, e.g., alternating layers of a first semiconductor material 22 and a second semiconductor material 24 );
a second vertical arrangement ( Zhang, FIG. 9, 5′; [0028], Structure 5′ will represent a work function gate stack where less dipole diffusion takes place ) of horizontal nanowires ( Zhang, FIG. 9, 24; [0027] );
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer ( Zhang, FIG. 9, 50; [0056] The third WFM layer 50 is thus deposited on the IL 30 and HK 32 (in structures 5), … and includes, for example, titanium nitride (TiN) ) on a first gate dielectric comprising a first N-type dipole material layer ( Zhang, FIG. 9, 60; [0062] The dipole material 60 wraps around the WFM layers 50, 52, 54. In one example, the dipole material 60 can be, e.g., lanthanum oxide (LaO). One skilled in the art can contemplate other earth elements employed to be diffused into HK layers, such, but not limited to, dysprosium (Dy) ); and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer ( Zhang, FIG. 9, 52; [0058], This deposition results in the third WFM layer 50 formed in the structure 5 (more dipole diffusion). Structure 5′ includes second WFM layer 42 and third WFM layer 50, thus forming combined WFM layer 52. WFM layer 52 is thicker than third WFM layer 50 ) on a second gate dielectric comprising the first N-type dipole material layer and a second N- type dipole material layer ( Zhang, [0065], dipole deposition and anneal such that the dipole material 60 diffuses through the HK 32, and into the IL 30, where there is more dipole diffusion in structure 5 (thinner WFM), less dipole diffusion in structure 5′ (thicker WFM), and no dipole diffusion in structure 5″ (thickest WFM). Thus, different threshold voltages (Vt) can be provided. In other words, a dipole material 60 and different thicknesses for WFM layers 50, 52, 54 are employed to modulate Vt to construct WFM gate structures with multiple threshold voltages; [0066], The dipole deposition in structure 5 results in IL 60′ and the dipole deposition in structure 5′ results in IL 60″. The dipole deposition in structure 5″ results in the original IL 30, which remains unmodified as the dipole material 60 does not penetrate into the IL 30 ).
Zhang fails to disclose:
the first gate stack a PMOS gate stack having a single P-type conductive layer with a thickness,
the second gate stack an NMOS gate stack having the single P-type conductive layer with the thickness,
a second gate dielectric comprising the first N-type dipole material layer and a second N- type dipole material layer, the second N-type dipole material layer having a different chemical composition than the first N-type dipole material layer, and the second N-type dipole material layer not included in the first gate stack.
However, Hsu teaches:
the first gate stack a PMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types. For example, the transistors 200A and 200B may both be n-type transistors, both be p-type transistors, or be one n-type transistor and one p-type transistor ) having a single P-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with a thickness ( Hsu, [0042], In the present embodiment, the difference in the threshold voltages of the transistors 200A and 200B can be completely tuned by the dipole incorporation discussed above (such as incorporating the dipole elements 216′ and 220′ into the gate dielectric layers of the transistor 200B) so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
the second gate stack an NMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types ) having the single P-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with the thickness ( Hsu, [0042], so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
a second gate dielectric comprising the first N-type dipole material layer ( Hsu, FIG. 8, 220; [0036], dipole layer 220 over the high-k dielectric layer 282, such as shown in FIG. 8. The dipole layer 220 includes a dielectric material for dipole formation in the gate dielectric layers; … the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials. The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process. Once driven into the high-k dielectric layer 282, particularly in the inner portion of the high-k dielectric layer 282 near the interfacial dielectric layer 280, the n-dipole material can reduce the threshold voltage of the transistor 200B when it is an n-type transistor or increase the threshold voltage of the transistor 200B when it is a p-type transistor ) and a second N- type dipole material layer (Hsu, FIG. 15, 220’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], FIG. 15 illustrates an enlarged view of a block 300 which is part of the transistor 200B. Referring to FIG. 15, the transistor 200B in the depicted embodiment includes both p-dipole elements 216′ and n-dipole elements 220′), the second N-type dipole material layer having a different ( Hsu, FIG. 8, 220; [0036], dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials ) chemical composition than the first N-type dipole material layer, and the second N-type dipole material layer not included in the first gate stack ( Hsu, FIG. 15, 220’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], n-dipole elements 220′ ).
Zhang and Hsu are both considered to be analogous to the claimed invention because they are forming integrated circuit structures and gate-all-around transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang ( different threshold voltages (Vt) can be provided by different levels of dipole diffusion ), to incorporate the teachings of Hsu ( [0042], a common work function metal layer 288 can be used for both transistors 200A and 200B; [0019], may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages ), to implement an example that the first gate stack a PMOS gate stack having a single P-type conductive layer with a thickness, the second gate stack an NMOS gate stack having the single P-type conductive layer with the thickness; and a gate dielectric comprising the first N-type dipole material layer and a second N- type dipole material layer which has a different chemical composition than the first N-type dipole material layer, and is not included in the first gate stack. Doing so would provide a specific example of simplifying the manufacturing process of work function layer by using a single thickness, controlling dipole layers, and therefore tunning different threshold voltages (Vt) by controlling the dipole layers can be implemented.
Regarding Claim 2 ( Original ), Zhang and Hsu teach the integrated circuit structure as claimed in claim 1, on which this claim is dependent, Zhang further teaches:
wherein the P-type conductive layer (Zhang, FIG. 9, 50; [0056], third WFM layer 50) comprises titanium and nitrogen, or comprises tungsten, or comprises molybdenum and nitrogen ( Zhang, [0056], third WFM layer 50 is …, and includes, for example, titanium nitride (TiN), tantalum nitride (TaN), …, tantalum aluminum carbon nitride (TaAlCN) or lanthanum (La) doped TiN or TaN ).
Regarding Claim 3 ( Original ), Zhang and Hsu teach the integrated circuit structure as claimed in claim 1, on which this claim is dependent, Zhang further teaches:
wherein the first N-type dipole material layer (Zhang, FIG. 9, 60; [0062] The dipole material 60) comprises lanthanum and oxygen (Zhang, [0062], The dipole material 60 wraps around the WFM layers 50, 52, 54. In one example, the dipole material 60 can be, e.g., lanthanum oxide (LaO) ) .
Regarding Claim 4 ( Original ), Zhang and Hsu teach the integrated circuit structure as claimed in claim 1, on which this claim is dependent, Zhang further teaches:
wherein the second N-type dipole material layer comprises magnesium and oxygen ( Hsu, [0036], In the present embodiment, the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials ).
Regarding Claim 5 ( Original ), Zhang and Hsu teach the integrated circuit structure as claimed in claim 1, on which this claim is dependent, Zhang and Hsu further teach:
wherein a high-k dielectric layer ( Hsu, [0035], The high-k dielectric layer 282 includes a high-k dielectric material, such as HfO2 … hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric material, or combinations thereof ) is between the first vertical arrangement ( Zhang, FIG. 9, 5; [0028] ) of horizontal nanowires ( Zhang, FIG. 9, 24; [0027] ) and the first N-type dipole material layer ( Zhang, FIG. 9, 60; [0062] ), and between the second vertical arrangement ( Zhang, FIG. 9, 5′; [0028] ) of horizontal nanowires ( Zhang, FIG. 9, 24; [0027] ) and the first N-type dipole material layer ( Zhang, FIG. 9, 60; [0062] ), the high-k dielectric layer comprising hafnium and oxygen ( Hsu, [0035], HfO2 ).
Regarding Independent Claim 6 ( Currently Amended ), Zhang teaches an integrated circuit structure, comprising:
a first vertical arrangement (Zhang, FIG. 9, 5; [0028], Structure 5 will represent a work function gate stack where more dipole diffusion takes place) of horizontal nanowires (Zhang, FIG. 9, 24; [0027], The nanosheet stack 20 can include, e.g., alternating layers of a first semiconductor material 22 and a second semiconductor material 24);
a second vertical arrangement (Zhang, FIG. 9, 5′; [0028], Structure 5′ will represent a work function gate stack where less dipole diffusion takes place) of horizontal nanowires (Zhang, FIG. 9, 24; [0027]);
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having an N-type conductive layer ( Zhang, FIG. 9, 52; [0058], This deposition results in the third WFM layer 50 formed in the structure 5 (more dipole diffusion). Structure 5′ includes second WFM layer 42 and third WFM layer 50, thus forming combined WFM layer 52. WFM layer 52 is thicker than third WFM layer 50 ) on a first gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer (Zhang, [0065], dipole deposition and anneal such that the dipole material 60 diffuses through the HK 32, and into the IL 30, where there is more dipole diffusion in structure 5 (thinner WFM), less dipole diffusion in structure 5′ (thicker WFM), and no dipole diffusion in structure 5″ (thickest WFM). Thus, different threshold voltages (Vt) can be provided. In other words, a dipole material 60 and different thicknesses for WFM layers 50, 52, 54 are employed to modulate Vt to construct WFM gate structures with multiple threshold voltages; [0066], The dipole deposition in structure 5 results in IL 60′ and the dipole deposition in structure 5′ results in IL 60″. The dipole deposition in structure 5″ results in the original IL 30, which remains unmodified as the dipole material 60 does not penetrate into the IL 30), and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the N-type conductive layer ( Zhang, FIG. 9, 50; [0056] The third WFM layer 50 is thus deposited on the IL 30 and HK 32 (in structures 5), … and includes, for example, titanium nitride (TiN) ) on a second gate dielectric comprising the first P-type dipole material layer ( Zhang, FIG. 9, 60; [0062] The dipole material 60 wraps around the WFM layers 50, 52, 54. In one example, the dipole material 60 can be, e.g., lanthanum oxide (LaO). One skilled in the art can contemplate other earth elements employed to be diffused into HK layers, such, but not limited to, dysprosium (Dy) ), wherein the second P-type dipole material layer is not included in the second gate stack.
Zhang fails to disclose:
the first gate stack a PMOS gate stack having a single N-type conductive layer with a thickness,
the second gate stack an NMOS gate stack having the single N-type conductive layer with the thickness,
a first gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer, the second P-type dipole material layer having a different chemical composition than the first P-type dipole material layer;
wherein the second P-type dipole material layer is not included in the second gate stack.
However, Hsu teaches:
the first gate stack a PMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types. For example, the transistors 200A and 200B may both be n-type transistors, both be p-type transistors, or be one n-type transistor and one p-type transistor ) having a single N-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with a thickness ( Hsu, [0042], In the present embodiment, the difference in the threshold voltages of the transistors 200A and 200B can be completely tuned by the dipole incorporation discussed above (such as incorporating the dipole elements 216′ and 220′ into the gate dielectric layers of the transistor 200B) so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
the second gate stack an NMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types ) having the single N-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with the thickness ( Hsu, [0042], so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
a first gate dielectric comprising a first P-type dipole material layer (Hsu, FIG. 8, 220; [0036], dipole layer 220 over the high-k dielectric layer 282, such as shown in FIG. 8. The dipole layer 220 includes a dielectric material for dipole formation in the gate dielectric layers; … the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials. The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process. Once driven into the high-k dielectric layer 282, particularly in the inner portion of the high-k dielectric layer 282 near the interfacial dielectric layer 280, the n-dipole material can reduce the threshold voltage of the transistor 200B when it is an n-type transistor or increase the threshold voltage of the transistor 200B when it is a p-type transistor) and a second P-type dipole material layer (Hsu, FIG. 15, 216’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], FIG. 15 illustrates an enlarged view of a block 300 which is part of the transistor 200B. Referring to FIG. 15, the transistor 200B in the depicted embodiment includes both p-dipole elements 216′ ), the second P-type dipole material layer having a different ( Hsu, [0028], For example … when the cladding layer 216 is germanium; [0030], the cladding layer 216 provides a p-dipole material or a precursor of a p-dipole material. For example, the p-dipole material may include germanium oxide, aluminum oxide, gallium oxide, or zinc oxide ) chemical composition than the first P-type dipole material layer;
wherein the second P-type dipole material layer is not included in the second gate stack ( Hsu, FIG. 15, 216’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], p-dipole elements 216′ ).
Zhang and Hsu are both considered to be analogous to the claimed invention because they are forming integrated circuit structures and gate-all-around transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang ( different threshold voltages (Vt) can be provided by different levels of dipole diffusion ), to incorporate the teachings of Hsu ( [0042], a common work function metal layer 288 can be used for both transistors 200A and 200B; [0019], may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages ), to implement an example that the first gate stack a PMOS gate stack having a single N-type conductive layer with a thickness, the second gate stack an NMOS gate stack having the single N -type conductive layer with the thickness; and a gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer which has a different chemical composition than the first P-type dipole material layer, and is not included in the second gate stack. Doing so would provide a specific example of simplifying the manufacturing process of work function layer by using a single thickness, controlling dipole layers, and therefore tunning different threshold voltages (Vt) by controlling the dipole layers can be implemented.
Regarding Claim 7 ( Original ), Zhang and Hsu teaches the integrated circuit structure as claimed in claim 6, on which this claim is dependent, Zhang further teaches:
wherein the N-type conductive layer (Zhang, FIG. 9, 50; [0056], third WFM layer 50) comprises titanium, aluminum and carbon (Zhang, [0056], third WFM layer 50 is …, and includes, for example, titanium nitride (TiN), tantalum nitride (TaN), …, tantalum aluminum carbon nitride (TaAlCN) or lanthanum (La) doped TiN or TaN).
Regarding Claim 8 ( Original ), Zhang and Hsu teaches the integrated circuit structure as claimed in claim 6, on which this claim is dependent, Hsu further teaches:
wherein the first P-type dipole material layer comprises aluminum and oxygen
( Hsu, [0030], In the present embodiment, the cladding layer 216 provides a p-dipole material or a precursor of a p-dipole material. For example, the p-dipole material may include germanium oxide, aluminum oxide, gallium oxide, or zinc oxide ).
Regarding Claim 9 ( Original ), Zhang and Hsu teaches the integrated circuit structure as claimed in claim 6, on which this claim is dependent, Hsu further teaches:
wherein the second P-type dipole material layer comprises titanium and oxygen (Hsu, [0019], may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0036], In the present embodiment, the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials).
Regarding Claim 10 ( Original ), Zhang and Hsu teaches the integrated circuit structure as claimed in claim 6, on which this claim is dependent, Zhang and Hsu further teach:
wherein a high-k dielectric layer ( Hsu, [0035], The high-k dielectric layer 282 includes a high-k dielectric material, such as HfO2 … hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric material, or combinations thereof ) is between the first vertical arrangement ( Zhang, FIG. 9, 5; [0028] ) of horizontal nanowires ( Zhang, FIG. 9, 24; [0027] ) and the first P-type dipole material layer ( Zhang, FIG. 9, 60; [0062] ), and between the second vertical arrangement ( Zhang, FIG. 9, 5′; [0028] ) of horizontal nanowires ( Zhang, FIG. 9, 24; [0027] ) and the first P-type dipole material layer ( Zhang, FIG. 9, 60; [0062] ), the high-k dielectric layer comprising hafnium and oxygen ( Hsu, [0035], HfO2 ).
Regarding Independent Claim 11 ( Currently Amended ), Zhang teaches a computing device, comprising:
a board ( Zhang, [0078], motherboard ); and
a component coupled to the board, the component including an integrated circuit ( Zhang, [0078], integrated circuit chips ) structure, comprising:
a first vertical arrangement (Zhang, FIG. 9, 5; [0028], Structure 5 will represent a work function gate stack where more dipole diffusion takes place) of horizontal nanowires (Zhang, FIG. 9, 24; [0027], The nanosheet stack 20 can include, e.g., alternating layers of a first semiconductor material 22 and a second semiconductor material 24);
a second vertical arrangement (Zhang, FIG. 9, 5′; [0028], Structure 5′ will represent a work function gate stack where less dipole diffusion takes place) of horizontal nanowires (Zhang, FIG. 9, 24; [0027]);
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer (Zhang, FIG. 9, 50; [0056] The third WFM layer 50 is thus deposited on the IL 30 and HK 32 (in structures 5), … and includes, for example, titanium nitride (TiN)) on a first gate dielectric comprising a first N-type dipole material layer (Zhang, FIG. 9, 60; [0062] The dipole material 60 wraps around the WFM layers 50, 52, 54. In one example, the dipole material 60 can be, e.g., lanthanum oxide (LaO). One skilled in the art can contemplate other earth elements employed to be diffused into HK layers, such, but not limited to, dysprosium (Dy)); and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer (Zhang, FIG. 9, 52; [0058], This deposition results in the third WFM layer 50 formed in the structure 5 (more dipole diffusion). Structure 5′ includes second WFM layer 42 and third WFM layer 50, thus forming combined WFM layer 52. WFM layer 52 is thicker than third WFM layer 50) on a second gate dielectric comprising the first N-type dipole material layer and a second N-type dipole material layer (Zhang, [0065], dipole deposition and anneal such that the dipole material 60 diffuses through the HK 32, and into the IL 30, where there is more dipole diffusion in structure 5 (thinner WFM), less dipole diffusion in structure 5′ (thicker WFM), and no dipole diffusion in structure 5″ (thickest WFM). Thus, different threshold voltages (Vt) can be provided. In other words, a dipole material 60 and different thicknesses for WFM layers 50, 52, 54 are employed to modulate Vt to construct WFM gate structures with multiple threshold voltages; [0066], The dipole deposition in structure 5 results in IL 60′ and the dipole deposition in structure 5′ results in IL 60″. The dipole deposition in structure 5″ results in the original IL 30, which remains unmodified as the dipole material 60 does not penetrate into the IL 30).
Zhang fails to disclose:
the first gate stack a PMOS gate stack having a single P-type conductive layer with a thickness,
the second gate stack an NMOS gate stack having the single P-type conductive layer with the thickness,
a second gate dielectric comprising the first N-type dipole material layer and a second N- type dipole material layer, the second N-type dipole material layer having a different chemical composition than the first N-type dipole material layer, and the second N-type dipole material layer not included in the first gate stack.
However, Hsu teaches:
the first gate stack a PMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types. For example, the transistors 200A and 200B may both be n-type transistors, both be p-type transistors, or be one n-type transistor and one p-type transistor ) having a single P-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with a thickness ( Hsu, [0042], In the present embodiment, the difference in the threshold voltages of the transistors 200A and 200B can be completely tuned by the dipole incorporation discussed above (such as incorporating the dipole elements 216′ and 220′ into the gate dielectric layers of the transistor 200B) so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
the second gate stack an NMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types ) having the single P-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with the thickness ( Hsu, [0042], so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
a second gate dielectric comprising the first N-type dipole material layer ( Hsu, FIG. 8, 220; [0036], dipole layer 220 over the high-k dielectric layer 282, such as shown in FIG. 8. The dipole layer 220 includes a dielectric material for dipole formation in the gate dielectric layers; … the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials. The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process. Once driven into the high-k dielectric layer 282, particularly in the inner portion of the high-k dielectric layer 282 near the interfacial dielectric layer 280, the n-dipole material can reduce the threshold voltage of the transistor 200B when it is an n-type transistor or increase the threshold voltage of the transistor 200B when it is a p-type transistor ) and a second N- type dipole material layer (Hsu, FIG. 15, 220’, 216’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], FIG. 15 illustrates an enlarged view of a block 300 which is part of the transistor 200B. Referring to FIG. 15, the transistor 200B in the depicted embodiment includes both p-dipole elements 216′ and n-dipole elements 220′), the second N-type dipole material layer having a different ( Hsu, FIG. 8, 220; [0036], dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials ) chemical composition than the first N-type dipole material layer, and the second N-type dipole material layer not included in the first gate stack ( Hsu, FIG. 15, 220’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], n-dipole elements 220′ ).
Zhang and Hsu are both considered to be analogous to the claimed invention because they are forming integrated circuit structures and gate-all-around transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang ( different threshold voltages (Vt) can be provided by different levels of dipole diffusion ), to incorporate the teachings of Hsu ( [0042], a common work function metal layer 288 can be used for both transistors 200A and 200B; [0019], may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages ), to implement an example that the first gate stack a PMOS gate stack having a single P-type conductive layer with a thickness, the second gate stack an NMOS gate stack having the single P-type conductive layer with the thickness; and a gate dielectric comprising the first N-type dipole material layer and a second N- type dipole material layer which has a different chemical composition than the first N-type dipole material layer, and is not included in the first gate stack. Doing so would provide a specific example of simplifying the manufacturing process of work function layer by using a single thickness, controlling dipole layers, and therefore tunning different threshold voltages (Vt) by controlling the dipole layers can be implemented.
Regarding Claim 12 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 11, on which this claim is dependent, Zhang further teaches:
a memory ( Zhang, [0021], Thin gate dielectric nanosheet transistors can be used, e.g., for logic and static random access memory (SRAM) applications ) coupled to the board.
Regarding Claim 13 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 11, on which this claim is dependent, Zhang further teaches:
a communication chip ( Zhang, [0077], the designer can transmit the resulting design by physical mechanisms (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly ) coupled to the board.
Regarding Claim 14 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 11, on which this claim is dependent, Zhang further teaches:
wherein the component is a packaged integrated circuit die (Zhang, [0078], Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form).
Regarding Claim 15 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 11, on which this claim is dependent, Zhang further teaches:
wherein the component is selected from the group consisting of a processor ( Zhang, [0078], central processor ), a communications chip ( Zhang, [0077], internet ), and a digital signal processor ( Zhang, [0078], signal processing devices ).
Regarding Independent Claim 16 ( Currently Amended ), Zhang teaches a computing device, comprising:
a board ( Zhang, [0078], motherboard ); and
a component coupled to the board, the component including an integrated circuit ( Zhang, [0078], integrated circuit chips ) structure, comprising:
a first vertical arrangement (Zhang, FIG. 9, 5; [0028], Structure 5 will represent a work function gate stack where more dipole diffusion takes place) of horizontal nanowires (Zhang, FIG. 9, 24; [0027], The nanosheet stack 20 can include, e.g., alternating layers of a first semiconductor material 22 and a second semiconductor material 24);
a second vertical arrangement (Zhang, FIG. 9, 5′; [0028], Structure 5′ will represent a work function gate stack where less dipole diffusion takes place) of horizontal nanowires (Zhang, FIG. 9, 24; [0027]);
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having an N-type conductive layer (Zhang, FIG. 9, 52; [0058], This deposition results in the third WFM layer 50 formed in the structure 5 (more dipole diffusion). Structure 5′ includes second WFM layer 42 and third WFM layer 50, thus forming combined WFM layer 52. WFM layer 52 is thicker than third WFM layer 50) on a first gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer (Zhang, [0065], dipole deposition and anneal such that the dipole material 60 diffuses through the HK 32, and into the IL 30, where there is more dipole diffusion in structure 5 (thinner WFM), less dipole diffusion in structure 5′ (thicker WFM), and no dipole diffusion in structure 5″ (thickest WFM). Thus, different threshold voltages (Vt) can be provided. In other words, a dipole material 60 and different thicknesses for WFM layers 50, 52, 54 are employed to modulate Vt to construct WFM gate structures with multiple threshold voltages; [0066], The dipole deposition in structure 5 results in IL 60′ and the dipole deposition in structure 5′ results in IL 60″. The dipole deposition in structure 5″ results in the original IL 30, which remains unmodified as the dipole material 60 does not penetrate into the IL 30); and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the N-type conductive layer ( Zhang, FIG. 9, 50; [0056] The third WFM layer 50 is thus deposited on the IL 30 and HK 32 (in structures 5), … and includes, for example, titanium nitride (TiN) ) on a second gate dielectric comprising the first P-type dipole material layer ( Zhang, FIG. 9, 60; [0062] The dipole material 60 wraps around the WFM layers 50, 52, 54. In one example, the dipole material 60 can be, e.g., lanthanum oxide (LaO). One skilled in the art can contemplate other earth elements employed to be diffused into HK layers, such, but not limited to, dysprosium (Dy) ).
Zhang fails to disclose:
the first gate stack a PMOS gate stack having a single N-type conductive layer with a thickness,
the second gate stack an NMOS gate stack having the single N-type conductive layer with the thickness,
a first gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer;
wherein the second P-type dipole material layer is not included in the second gate stack.
However, Hsu teaches:
the first gate stack a PMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types. For example, the transistors 200A and 200B may both be n-type transistors, both be p-type transistors, or be one n-type transistor and one p-type transistor ) having a single N-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with a thickness ( Hsu, [0042], In the present embodiment, the difference in the threshold voltages of the transistors 200A and 200B can be completely tuned by the dipole incorporation discussed above (such as incorporating the dipole elements 216′ and 220′ into the gate dielectric layers of the transistor 200B) so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
the second gate stack an NMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types ) having the single N-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with the thickness ( Hsu, [0042], so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
a first gate dielectric comprising a first P-type dipole material layer (Hsu, FIG. 8, 220; [0036], dipole layer 220 over the high-k dielectric layer 282, such as shown in FIG. 8. The dipole layer 220 includes a dielectric material for dipole formation in the gate dielectric layers; … the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), or other suitable n-dipole materials. The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process. Once driven into the high-k dielectric layer 282, particularly in the inner portion of the high-k dielectric layer 282 near the interfacial dielectric layer 280, the n-dipole material can reduce the threshold voltage of the transistor 200B when it is an n-type transistor or increase the threshold voltage of the transistor 200B when it is a p-type transistor) and a second P-type dipole material layer (Hsu, FIG. 15, 220’, 216’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], FIG. 15 illustrates an enlarged view of a block 300 which is part of the transistor 200B. Referring to FIG. 15, the transistor 200B in the depicted embodiment includes both p-dipole elements 216′ and n-dipole elements 220′);
wherein the second P-type dipole material layer is not included in the second gate stack ( Hsu, FIG. 15, 216’; [0019], In various embodiment, either the transistor 200A or the transistor 200B or both the transistors 200A and 200B may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages thereof; [0046], p-dipole elements 216′ ).
Zhang and Hsu are both considered to be analogous to the claimed invention because they are forming integrated circuit structures and gate-all-around transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang ( different threshold voltages (Vt) can be provided by different levels of dipole diffusion ), to incorporate the teachings of Hsu ( [0042], a common work function metal layer 288 can be used for both transistors 200A and 200B; [0019], may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages ), to implement an example that the first gate stack a PMOS gate stack having a single N-type conductive layer with a thickness, the second gate stack an NMOS gate stack having the single N-type conductive layer with the thickness; and a gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer which has a different chemical composition than the first P-type dipole material layer, and is not included in the second gate stack. Doing so would provide a specific example of simplifying the manufacturing process of work function layer by using a single thickness, controlling dipole layers, and therefore tunning different threshold voltages (Vt) by controlling the dipole layers can be implemented.
Regarding Claim 17 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 16, on which this claim is dependent, Zhang further teaches:
a memory ( Zhang, [0021], Thin gate dielectric nanosheet transistors can be used, e.g., for logic and static random access memory (SRAM) applications ) coupled to the board.
Regarding Claim 18 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 16, on which this claim is dependent, Zhang further teaches:
a communication chip ( Zhang, [0077], the designer can transmit the resulting design by physical mechanisms (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly ) coupled to the board.
Regarding Claim 19 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 16, on which this claim is dependent, Zhang further teaches:
wherein the component is a packaged integrated circuit die (Zhang, [0078], Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form).
Regarding Claim 20 ( Original ), Zhang and Hsu teach the computing device as claimed in claim 16, on which this claim is dependent, Zhang further teaches:
wherein the component is selected from the group consisting of a processor ( Zhang, [0078], central processor ), a communications chip ( Zhang, [0077], internet ), and a digital signal processor ( Zhang, [0078], signal processing devices ).
Response to Arguments
Applicant's remarks filed 3/13/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding ( Currently Amended ) Claims 1, 6, 11, 16: on page 8, line 7 from bottom, cited “ Amended independent claim 1 is directed to an integrated circuit structure including the features, "a first vertical arrangement of horizontal nanowires," "a second vertical arrangement of horizontal nanowires," "a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a single P-type conductive layer with a thickness, the single P-type conductive layer on a first gate dielectric comprising a first N- type dipole material layer," and "a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the single P-type conductive layer with the thickness, the single P-type conductive layer on a second gate dielectric comprising the first N-type dipole material layer and a second N-type dipole material layer, the second N-type dipole material layer having a different chemical composition than the first N-type dipole material layer, and the second N-type dipole material layer not included in the first gate stack." (Emphasis added.) ”; on page 11, line 2, cited “ As such, with respect to amended independent claims 1, 6, 11 and 16, Zhang fails to disclose each and every feature of Applicant's claims. ”.
Examiner’s response: please refer to claim 1, 6, 11, 16 in Claim Rejections - 35 USC § 103 of this office action, for instance, claim 1, cited “
However, Hsu teaches:
the first gate stack a PMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types. For example, the transistors 200A and 200B may both be n-type transistors, both be p-type transistors, or be one n-type transistor and one p-type transistor ) having a single P-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with a thickness ( Hsu, [0042], In the present embodiment, the difference in the threshold voltages of the transistors 200A and 200B can be completely tuned by the dipole incorporation discussed above (such as incorporating the dipole elements 216′ and 220′ into the gate dielectric layers of the transistor 200B) so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
the second gate stack an NMOS gate stack ( Hsu, gate stack on 200A or 200B; [0019], two transistors 200A and 200B, which may be of the same conductivity-type or opposite conductivity-types ) having the single P-type conductive layer ( Hsu, FIG. 15, 288; [0042], work function metal layer 288 ) with the thickness ( Hsu, [0042], so that a common work function metal layer 288 can be used for both transistors 200A and 200B ),
…
Zhang and Hsu are both considered to be analogous to the claimed invention because they are forming integrated circuit structures and gate-all-around transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang ( different threshold voltages (Vt) can be provided by different levels of dipole diffusion ), to incorporate the teachings of Hsu ( [0042], a common work function metal layer 288 can be used for both transistors 200A and 200B; [0019], may incorporate no dipole material, p-dipole material(s) only, n-dipole material(s) only, or both p-dipole material(s) and n-dipole material(s) for tuning the threshold voltages ), to implement an example that the first gate stack a PMOS gate stack having a single P-type conductive layer with a thickness, the second gate stack an NMOS gate stack having the single P-type conductive layer with the thickness; and a gate dielectric comprising the first N-type dipole material layer and a second N- type dipole material layer which has a different chemical composition than the first N-type dipole material layer, and is not included in the first gate stack. Doing so would provide a specific example of simplifying the manufacturing process of work function layer by using a single thickness, controlling dipole layers, and therefore tunning different threshold voltages (Vt) by controlling the dipole layers can be implemented. ”. Hsu disclosed the added limitations in amended claims 1, 6, 11, 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817