DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of layout A, with feedthrough architecture II, and modification IIB in the reply filed on 10/15/2025 is acknowledged. Claims 4, 6-10, 16-20 have been withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2020/0303551 A1) in view of Lilak et al. (US 2020/0294998 A1).
Regarding claim 1, Chen teaches an integrated circuit structure (1500 in Fig. 15 of Chen which is built up from 1400 in Figs. 1-14), comprising:
a plurality of gate lines (1216, as shown in Fig. 14) extending over a plurality of channel structures (1204);
a plurality of trench contacts (1218, as shown in Fig. 13) extending over a plurality of source or drain structures (802A/B in Fig. 8), individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines (as shown in Fig. 12 of Chen);
a front-side metal routing layer (1324-1328 in Fig. 15) extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts (as described in [0090] of Chen);
a backside metal routing layer (1524 in Fig. 15) extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer (as shown in Fig. 15); and
a conductive feedthrough structure (1522, 1404, 1208, V0, V1 in Figs. 7, 8 and 15) coupling the backside metal routing layer to the front-side metal routing layer.
But Chen does not teach that the plurality of channel structures are semiconductor nanowire stacks.
Lilak teaches a semiconductor device. The channel structures of the device are stacks of nanowires (116A/B in Fig. 1A of Lilak) and the gate structures (120A/B) wrap around the stacks of nanowire channel structures.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel structures from nanowire stacks in order to have improved the device performance (avoid short-channel effects, increase gate-channel interface…).
Regarding claim 2, Chen in view of Lilak teaches all limitations of the integrated circuit structure of claim 1, and also teaches wherein the backside metal routing layer is a backside power delivery line (as stated in [0095] of Chen, 1524 are power grid conductors).
Regarding claim 3, Chen in view of Lilak teaches all limitations of the integrated circuit structure of claim 1, and also teaches wherein the conductive feedthrough structure is in an isolation location (dielectric layer 1320 in Fig. 13 of Chen).
Regarding claim 5, Chen in view of Lilak teaches all limitations of the integrated circuit structure of claim 1, and also teaches wherein the conductive feedthrough structure is a boundary deep via segment (1522 in Fig. 15 of Chen).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak in view of Chen.
Regarding claim 11, Lilak teaches a computing device (1000 in Fig. 10 of Lilak), comprising:
a board (motherboard 1002); and
a component (processor 1004) coupled to the board, the component including an integrated circuit structure (IC structure shown in Fig. 1A), comprising:
a plurality of gate lines (120A/B in Fig. 1A) extending over a plurality of semiconductor nanowire stack channel structures (116A/B);
But Lilak does not teach that the IC structure comprising: a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines; a front-side metal routing layer extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts; a backside metal routing layer extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer; and a conductive feedthrough structure coupling the backside metal routing layer to the front-side metal routing layer.
Chen teaches an integrated circuit structure (1500 in Fig. 15 of Chen which is built up from 1400 in Figs. 1-14), comprising:
a plurality of gate lines (1216, as shown in Fig. 14) extending over a plurality of semiconductor nanowire stack channel structures (1204);
a plurality of trench contacts (1218, as shown in Fig. 13) extending over a plurality of source or drain structures (802A/B in Fig. 8), individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines (as shown in Fig. 12 of Chen);
a front-side metal routing layer (1324-1328 in Fig. 15) extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts (as described in [0090] of Chen);
a backside metal routing layer (1524 in Fig. 15) extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer (as shown in Fig. 15); and
a conductive feedthrough structure (1522, 1404, 1208, V0, V1 in Figs. 7, 8 and 15) coupling the backside metal routing layer to the front-side metal routing layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the front and backside contact structures of Chen in Lilak’s device in order to decrease the interconnection density which helps with interference problem, thus, allowing scaling down of the IC structure.
Regarding claim 12, Lilak in view of Chen teaches all limitations of the computing device of claim 11, and further comprising: a memory (DRAM/ROM in Fig. 10 of Lilak) coupled to the board.
Regarding claim 13, Lilak in view of Chen teaches all limitations of the computing device of claim 11, and further comprising: a communication chip (1006 in Fig. 10 of Lilak) coupled to the board.
Regarding claim 14, Lilak in view of Chen teaches all limitations of the computing device of claim 11, and further comprising: a camera (camera in Fig. 10 of Lilak) coupled to the board.
Regarding claim 15, Lilak in view of Chen teaches all limitations of the computing device of claim 11, and wherein the component is a packaged integrated circuit die (as described in [0065] of Lilak).
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898