DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, 9, 11-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Solomko et al. (US 2023/0343531 A1; hereinafter Solomko) in view of Choi et al. (US 2006/0092694 A1; hereinafter Choi) in view of Li et al. (US 2022/0285614 A1; hereinafter Li).
Regarding Independent Claim 1, Solomko (Figs.6A-B) discloses a semiconductor structure comprising: a first electrode (13A; [0034]);
a second electrode (13B; [0034]);
a phase-change material (PCM) line (11; [0034]) in contact with and positioned between the first electrode (13A) and the second electrode (13B);
at least two heater lines (multiple lines of 62; Fig.6A-B) positioned between the first electrode (13A) and the second electrode (13B); wherein the at least two heater lines are individually corresponding portion of the PCM line ([0084]-[0087] and [0110]-[0116] discloses multiple heaters that are coupled to equalization device to provide varying impedance to the heaters); and
an isolation layer (21; [0069]) positioned between the PCM line (11) and the at least two heater lines (multiple lines of 62).
Solomko does not particularly disclose wherein the at least two heater lines are individually addressable through separate electrical connections, wherein each heater line of the at least two heater lines is configured to selectively activate a corresponding overlapping portion of the PCM line, wherein the PCM line exhibits at least four resistance states based upon the activated portion of the PCM by the at least two heater lines.
Choi (Figs.3-4) in a related art discloses a semiconductor structure comprising: a PCM array with selectively addressable unit cells. In each unit cell (C), an individual heater (85; [0040]) is applied to the PC resistor (80; [0043]) when the proper combination of selection transistors (60, 65, 70, 75; [0059]). Fig. 4 details a unit cell scheme layout.
Therefore, it would have been obvious in the art before the effective filing of the application to have a PCM array with selectively addressable unit cells to have an integrated device that has a phase change memory device which have high reliability and high integrity.
Solomko in view of Choi does not particularly disclose wherein the PCM line has a first end portion and a second end portion opposite the first end portion, and wherein the first end portion is encapsulated by the first electrode and the second end portion is encapsulated by the second electrode.
Li (Fig.10A/B) in a related art discloses a semiconductor structure wherein the PCM line (43; [0063]) has a first end portion (right side end) and a second end portion (left side end) opposite the first end portion, and wherein the first end portion is encapsulated by the first electrode (80A/B) and the second end portion is encapsulated by the second electrode (80A/B).
Therefore it would have been obvious in the art before the effective filing date of the application to have first and second electrodes encapsulating the first and second sides of the PCM line to achieve unprecedented thermal efficiency and confinement, which drastically reduces the programming current required to flip the material between its amorphous and crystalline states.
Regarding Claim 2. The semiconductor structure of claim 1, Solomko (Figs.6A-B) discloses wherein the at least two heater lines (multiple lines of 62) comprise: a first heater line (first 62) positioned in a first vertical plane as the PCM line in a vertical cross-sectional view (Fig.6B); and
a second heater line (second 62) positioned in a second vertical plane as the PCM line in the vertical cross-sectional view, wherein the first heater line (first 62) and the second heater line (second 62) are in a same horizontal plane in the vertical cross-sectional view (see Fig.6B).
Regarding Claim 3. The semiconductor structure of claim 2, Solomko (Figs.6A-B) discloses wherein the first heater line (first 62) is a same width as the second heater line (second 62) in a first horizontal direction.
Regarding Claim 5. The semiconductor structure of claim 2, Solomko (Figs.6A-B) discloses wherein the first heater line (first 62) is a same material ([0005]) as the second heater line (second 62).
Regarding Claim 7. The semiconductor structure of claim 3, Solomko (Figs.6A-B) discloses wherein: the at least two heater lines further comprise a third heater line (third 62), and a width of the third heater line (third 62) is the same in the first horizontal direction as a first heater line width and a second heater line width (shown).
Regarding Claim 9. The semiconductor structure of claim 5, Solomko (Figs.6A-B) discloses wherein: the at least two heater lines further comprise a third heater line (third 62), and the third heater line (third 62) is a same material as the first heater line or the second heater line ([0005]).
Regarding Claim 11. The semiconductor structure of claim 1, Solomko (Figs.6A-B) discloses wherein the at least two heater lines comprise tungsten (W), tungsten titanium (TiW), copper (Cu), aluminum (Al), gold (Au), molybdenum (Mo), or a combination thereof ([0005] discloses tungsten).
Regarding Independent Claim 12. Solomko (Figs.6A-B) discloses a switch structure comprising: a first electrode (13A);
a second electrode (13B);
a first heater line (first 62);
a second heater line (second 62); and
a first phase-change material (PCM) line (11) electrically connecting the first electrode (13A) and the second electrode (13B), wherein: the first PCM line (11) has a channel length in a first horizontal direction equal to a distance between proximate sidewalls of the first electrode and the second electrode (see length of 11 in fig.6A);
the first PCM line (11) is formed over the first heater line (first 62) and wherein a first overlap area between the first heater line (first 62) and the first PCM line (11) in a plan view (Fig.6A) is a first PCM cell (shown);
the first PCM line (11) is formed over the second heater line (second 62) and wherein a second overlap area between the second heater line (second 62) and the first PCM line (11) in the plan view is a second PCM cell (second intersection between the heater 11 and heater lines 62),
wherein a resistance of the first PCM line (11) is a function of the channel length, the first PCM cell, and the second PCM cell (see [0009], [0037], [0091]).
Solomko does not particularly disclose wherein the first heater line and the second heater line are individually addressable through separate electrical connections, wherein each heater line of the first heater line and the second heater line is configured to selectively activate a corresponding overlapping portion of the first PCM line, wherein the first PCM line to exhibit at least four resistance states based upon the activated portion of the PCM by the first heater line and the second heater line.
Choi (Figs.3-4) in a related art discloses a semiconductor structure comprising: a PCM array with selectively addressable unit cells. In each unit cell (C), an individual heater (85; [0040]) is applied to the PC resistor (80; [0043]) when the proper combination of selection transistors (60, 65, 70, 75; [0059]). Fig. 4 details a unit cell scheme layout wherein the first heater line and the second heater line (85) are individually addressable through separate electrical connections, wherein each heater line of the first heater line and the second heater line (85) is configured to selectively activate a corresponding overlapping portion of the first PCM line, wherein the first PCM line to exhibit at least four resistance states based upon the activated portion of the PCM by the first heater line and the second heater line ([0059]).
Therefore, it would have been obvious in the art before the effective filing of the application to have a PCM array with selectively addressable unit cells to have an integrated device that has a phase change memory device which have high reliability and high integrity.
Solomko in view of Choi does not particularly disclose wherein the PCM line has a first end portion and a second end portion opposite the first end portion, and wherein the first end portion is encapsulated by the first electrode and the second end portion is encapsulated by the second electrode.
Li (Fig.10A/B) in a related art discloses a semiconductor structure wherein the PCM line (43; [0063]) has a first end portion (right side end) and a second end portion (left side end) opposite the first end portion, and wherein the first end portion is encapsulated by the first electrode (80A/B) and the second end portion is encapsulated by the second electrode (80A/B).
Therefore it would have been obvious in the art before the effective filing date of the application to have first and second electrodes encapsulating the first and second sides of the PCM line to achieve unprecedented thermal efficiency and confinement, which drastically reduces the programming current required to flip the material between its amorphous and crystalline states.
Regarding Claim 13. The switch structure of claim 12, Solomko (Figs.6A-B) discloses wherein activation of at least one of the first PCM cell (see Fig.15-18) and the second PCM cell via a short pulse width signal conveyed across the first heater line and the second heater line respectively increases the resistance of the PCM line ([0003], [0037], [0079]).
Regarding Claim 15. The switch structure of claim 12, Solomko (Figs.6A-B; Fig.15-18) discloses further comprising: a third electrode; a fourth electrode (Figs.15-18 shows multiple PCM cells having two electrodes); and a second PCM line (second cell 11) electrically connecting the third electrode (second 13A) and the fourth electrode (second 13B), wherein: the second PCM line has a channel length in the first horizontal direction equal to a distance between proximate sidewalls of the third electrode and the fourth electrode, the second PCM line extends in a direction parallel to the first PCM line, and the second PCM line overlies the first heater line (first 62) and the second heater line (second 62).
Claim(s) 4, 6, 8, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Solomko in view of Choi in view of Ok et al. (US 2023/0093604 A1; hereinafter Ok).
Regarding Claim 4. The semiconductor structure of claim 2, Solomko and Choi do not particularly disclose wherein the first heater line is a different width than the second heater line in a first horizontal direction.
Ok (Fig.2) in a related art discloses a semiconductor structure comprising heater lines (202/204/206) wherein the first heater line is a different width than the second heater line in a first horizontal direction ([0049]).
Therefore, it would have been obvious in the art before the effective filing date of the application to have the heaters with different width to enclose insulator gaps and therefore enhance the characteristics of the whole structure.
Regarding Claim 6. The semiconductor structure of claim 2, Solomko does not particularly disclose wherein the first heater line is a different material than the second heater line.
Ok (Fig.2) in a related art discloses a semiconductor structure comprising heater lines (202/204/206) wherein the first heater line is a different material than the second heater line ([0042]).
Therefore, it would have been obvious in the art before the effective filing date of the application to have the heaters with different material to have different effects on PCM layer in different positions.
Regarding Claim 8. The semiconductor structure of claim 3, Solomko (Figs.6A-B) discloses wherein: the at least two heater lines further comprise a third heater line (third 62).
Solomko does not particularly disclose wherein a width of the third heater line is different in the first horizontal direction than a first heater line width and a second heater line width.
Ok (Fig.2) in a related art discloses a semiconductor structure comprising heater lines (202/204/206) wherein the first heater line is a different width than the second heater line in a first horizontal direction ([0049]).
Therefore, it would have been obvious in the art before the effective filing date of the application to have the heaters with different width to enclose insulator gaps and therefore enhance the characteristics of the whole structure.
Regarding Claim 10. The semiconductor structure of claim 5, Solomko (Figs.6A-B) discloses wherein: the at least two heater lines further comprise a third heater line (third 62).
Solomko does not particularly disclose wherein the third heater line is a different material than the first heater line and the second heater line.
Ok (Fig.2) in a related art discloses a semiconductor structure comprising heater lines (202/204/206) wherein the first heater line is a different material than the second heater line ([0042]).
Therefore, it would have been obvious in the art before the effective filing date of the application to have the heaters with different material to have different effects on PCM layer in different positions.
Regarding Claim 14. The switch structure of claim 12, Solomko (Figs.6A-B) discloses wherein: a first end portion of the first PCM line (11) contacts a sidewall (indirectly contacts) and a bottom surface of the first electrode (13A), a second end portion of the first PCM line contacts a sidewall (indirectly contacts) and a bottom surface of the second electrode (13B), the bottom surface of the first electrode (13A) is in a same vertical plane as the first heater line (first 62), and the bottom surface of the second electrode (13B) is in a same vertical plane as the second heater line (second 62).
Claim(s) 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Solomko in view of Ok in view of Kordus et al. (US 2007/0096071 A1; hereinafter Kordus) and Choi in view of Li.
Regarding Claim 16. Solomko (Figs.6A-B) discloses a method of forming a semiconductor structure, the method comprising:
forming a dielectric isolation layer (21) having a planar top surface over a substrate ([0033]);
forming at least two heater lines (multiple 62 lines) over the planar top surface;
forming a phase-change material (PCM) line (11), forming a first electrode (13A) and a second electrode (13B), wherein a first end portion of the PCM line (11) contacts the first electrode (13A) and a second end portion of the PCM line (11) contacts the second electrode (13B), wherein the at least two heater lines are corresponding portion of the PCM line ([0084]-[0087] and [0110]-[0116] discloses multiple heaters that are coupled to equalization device to provide varying impedance to the heaters);
Solomko does not particularly disclose forming at least one heater-capping dielectric plate over the at least two heater lines; forming a phase-change material (PCM) line (11) over the at least one heater-capping dielectric plate, and forming a PCM-capping dielectric plate over the PCM line.
Kordus (Fig.15L) discloses in a related art a phase change device having heate-capping dielectric plate (207; [0079]) over the at least two heater lines (206); forming a phase-change material (PCM) line (208a; [0081]) over the at least one heater-capping dielectric plate (207), and forming a PCM-capping dielectric plate (209) over the PCM line (208a).
Solomko does not particularly disclose wherein the at least two heater lines are individually controllable to activate a addressable through separate electrical connections, wherein each heater line of the at least two heater lines is configured to selectively activate a corresponding overlapping portion of the PCM line, wherein the PCM line exhibits at least four resistance states based upon the activated portion of the PCM by the at least two heater lines.
Therefore, it would have been obvious in the art before the effective filing date of the application to have heater-capping dielectric plate over the at least two heater lines; forming a phase-change material (PCM) line (11) over the at least one heater-capping dielectric plate, and forming a PCM-capping dielectric plate over the PCM line to be able to make outer connections to other structures
Choi (Figs.3-4) in a related art discloses a semiconductor structure comprising: a PCM array with selectively addressable unit cells. In each unit cell (C), an individual heater (85; [0040]) is applied to the PC resistor (80; [0043]) when the proper combination of selection transistors (60, 65, 70, 75; [0059]). Fig. 4 details a unit cell scheme layout and wherein the at least two heater lines (85) are individually addressable through separate electrical connections, wherein each heater line of the at least two heater lines (85) is configured to selectively activate a corresponding overlapping portion of the PCM line, wherein the PCM line exhibits at least four resistance states based upon the activated portion of the PCM by the at least two heater lines ([0059]).
Therefore, it would have been obvious in the art before the effective filing of the application to have a PCM array with selectively addressable unit cells to have an integrated devices that has a phase change memory device which have high reliability and high integrity.
Solomko in view of Ok in view of Kordus in view of Choi does not particularly disclose wherein the PCM line has a first end portion and a second end portion opposite the first end portion, and wherein the first end portion is encapsulated by the first electrode and the second end portion is encapsulated by the second electrode.
Li (Fig.10A/B) in a related art discloses a semiconductor structure wherein the PCM line (43; [0063]) has a first end portion (right side end) and a second end portion (left side end) opposite the first end portion, and wherein the first end portion is encapsulated by the first electrode (80A/B) and the second end portion is encapsulated by the second electrode (80A/B).
Therefore it would have been obvious in the art before the effective filing date of the application to have first and second electrodes encapsulating the first and second sides of the PCM line to achieve unprecedented thermal efficiency and confinement, which drastically reduces the programming current required to flip the material between its amorphous and crystalline states.
Regarding Claim 17. The method of claim 16, Solomko (Figs.6A-B) discloses wherein forming the at least two heater lines (multiple 62) over the planar top surface comprises: forming a first heater line (first 62) having a first width in a first horizontal direction; and forming a second heater line (second 62) having a second width in the first horizontal direction.
Solomko does not particularly disclose wherein the first width is different from the second width.
Ok (Fig.2) in a related art discloses a semiconductor structure comprising heater lines (202/204/206) wherein the first heater line is a different width than the second heater line in a first horizontal direction ([0049]).
Therefore, it would have been obvious in the art before the effective filing date of the application to have the heaters with different width to enclose insulator gaps and therefore enhance the characteristics of the whole structure.
Regarding Claim 18. The method of claim 16, Solomko (Figs.6A-B) discloses wherein forming the at least two heater lines (multiple 62) over the planar top surface comprises: forming a first heater line (first 62) with a first material; and forming a second heater line (second 62) with a second material.
Solomko does not particularly disclose wherein the first material is different from the second material.
Ok (Fig.2) in a related art discloses a semiconductor structure comprising heater lines (202/204/206) wherein the first heater line is a different material than the second heater line ([0042]).
Therefore, it would have been obvious in the art before the effective filing date of the application to have the heaters with different material to have different effects on PCM layer in different positions.
Regarding Claim 19. The method of claim 16, Solomko (Figs.6A-B) discloses wherein: the first end portion of the PCM line (11) contacts a sidewall (indirectly contacts) and a bottom surface of the first electrode (13A), the second end portion of the PCM line (11) contacts a sidewall and a bottom surface of the second electrode (13B), and a middle portion of the PCM line (11) between the first end portion and the second end portion overlies the at least two heater lines (62).
Regarding Claim 20. The method of claim 16, Kordus (Fig.15L) discloses forming a first dielectric material layer (209a) over the PCM-capping dielectric plate (209); forming a trench (212) in the first dielectric material layer (209a), wherein a top surface of a horizontally-extending portion of the PCM-capping dielectric plate (209) is exposed; depositing a conductive material (material in 212) over the first dielectric material layer and in the trench to be in contact with exposed portions of the PCM-capping dielectric plate (209); and patterning the conductive material into a trench heater line (see [0084]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAJAR KOLAHDOUZAN/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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