DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 07/06/2026 have been fully considered but they are not persuasive.
It is argued by the applicant that Yoon does not disclose or suggest "a third source/drain region coupled to the second source/drain region" of claims 1 and 21.
However, the examiner is persuaded as “couple” is a broad term and it means to join for combined effect. Figs. 4-5 of Yoon discloses many elements which are coupled (joined) together for combined effect – to produce a result of what the circuit was designed for.
In addition, Figs. 4-5 of Yoon does not disclose that the third source/drain region and the second source/drain region are a same source/drain region.
PNG
media_image1.png
648
372
media_image1.png
Greyscale
However, figs. 3C-3D of Yoon discloses that source/drain of programming device and a reading device can be combined to form a single source/drain region by removing the Dummy device DGS, as disclosed in par [0049] of Yoon in order to achieve the reduction of the cell area, as shown in FIG. 3D, the writing gate electrode WG and the reading gate electrode RG constituting the single unit cell may be formed to share the source/drain junction region 120 therebetween.
Therefore, it would have been obvious to form a structure wherein the third source/drain region and the second source/drain region are a same source/drain region in order to achieve the reduction of the cell area.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 and 15-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. 20170200727 in view of Wu et al. 20160104542.
PNG
media_image2.png
742
1263
media_image2.png
Greyscale
Regarding claim 1, figs. 4-5 of Yoon discloses a structure comprising:
a bit line BL; and
an anti-fuse cell comprising:
a first reading device (RGS transistor) comprising:
a first gate RGS coupled to the first word line;
first source/drain region (examiner labeled as 1) coupled to the bit line; and
a second source/drain region (examiner labeled as 2), wherein the first source/drain region and the second source/drain region are on opposite sides of the first gate;
a first programming device (WGS transistor) comprising:
a second gate WGS; and
a third source/drain region (examiner labeled as 3) coupled to the second source/drain region; and
a fourth source/drain region (examiner labeled as 4), wherein the third source/drain region and the fourth source/drain region are on opposite sides of the second gate; and
a dummy device (DGS transistor) comprising:
a third gate (left DGS);
a fifth source/drain region (examiner labeled as 5) directly coupled to the fourth source/drain region; and
a sixth source/drain (examiner labeled as 6) region,
wherein the fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate, the dummy device corresponding to a non-functional transistor.
Yoon does not disclose of a first word line and that the first gate RGS coupled to the first word line.
PNG
media_image3.png
450
443
media_image3.png
Greyscale
However, fig. 9 of Wu discloses a structure comprising:
a word line WLR;
a bit line BLR; and
an anti-fuse cell comprising:
a first reading device 540 comprising:
a first gate (that of 544);
a first source/drain region couple to the bit line BLR; and
a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the first gate;
In view of such teaching, it would have been obvious to form a structure of Yoon further comprising a first word line and that the first gate of the reading device coupled to the first word line such as taught by Wu in order to be able ot select proper memory cell.
Regarding claim 2, figs. 4-5 of Yoon discloses further comprising a second programming device comprising:a fourth gate; anda seventh source/drain region on one side of the fourth gate,wherein the first to seventh source/drain regions are included in a continuous active region including a semiconductor material.
Regarding claim 3, figs. 4-5 of Yoon discloses wherein the dummy device further comprises: a fifth gate (right DGS); an eighth source/drain region coupled to the sixth source/drain region; and a ninth source/drain region coupled to the seventh source/drain region, wherein the eighth source/drain region and the ninth source/drain region are on opposite sides of the fifth gate.
Regarding claim 4, figs. 4-5 of Yoon discloses further comprising: a second programming device, wherein the dummy device is coupled between the first programming device and the second programming device.
Fig. 10 of Wu discloses a second word line.
In view of such teaching, it would have been obvious to form a structure of Yoon and Wu further comprising a second word line such as taught by Wu in order to be able ot select proper memory cell for the second anti-fuse cell.
Regarding claim 5, figs. 4-5 of Yoon discloses wherein the second programming device comprises:a fourth gate;a seventh source/drain region; andan eighth source/drain region, wherein the seventh source/drain region and the eighth source/drain region are on opposite sides of the fourth gate.
Regarding claim 6, figs. 4-5 of Yoon discloses further comprising a second reading device comprising:a fifth gate coupled to the second word line;a ninth source/drain region coupled to the eighth source/drain region; anda tenth source/drain region coupled to the bit line, wherein the ninth source/drain region and the tenth source/drain region are on opposite sides of the fifth gate.
Regarding claim 7, further comprising: a second word line coupled to the second gate,wherein a width of the second word line is different from a width of the first word line.
Fig. 10 of Wu discloses a second word line.
In view of such teaching, it would have been obvious to form a structure of Yoon and Wu further comprising a second word line such as taught by Wu in order to be able ot select proper memory cell for the second anti-fuse cell.
The resulting structure would have been one wherein a width of the second word line is different from a width of the first word line as different is a term of degree.
Regarding claim 8, it would have been obvious to form a structure wherein the width of the second word line is greater than the width of the first word line as there line variation during processing of the structure.
Regarding claim 9, the resulting structure would have been one wherein the first reading device and the first programming device are each implemented with one or more transistors.
Regarding claim 10, it would have been obvious to form a structure further comprising:a voltage line coupled to the third gate and configured to receive a reference voltage in order to supply voltage to the gate.
PNG
media_image4.png
682
1136
media_image4.png
Greyscale
Regarding claim 15, figs. 4-5 of Yoon discloses a structure comprising:
a first bit line; and
a first anti-fuse cell comprising:
a first reading device comprising:
a first gate;
a first source/drain region coupled to the first bit line; and
a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the first gate;
a first programming device comprising:
a second gate;
a third source/drain region coupled to the second source/drain region; and
a fourth source/drain region, wherein the third source/drain region and the fourth source/drain region are on opposite sides of the second gate;
a first dummy device comprising:
a third gate;
a fifth source/drain region directly coupled to the fourth source/drain region; and
a sixth source/drain region, wherein the fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate, the first dummy device corresponding to a first non-functional transistor; and
a second dummy device (that of second row below first row in fig. 4) comprising:
a fourth gate;
a seventh source/drain region coupled to the sixth source/drain region; and
an eighth source/drain region, wherein the seventh source/drain region and the eighth source/drain region are on opposite sides of the fourth gate.
Figs. 4-5 of Yoon does not disclose that the third source/drain region and the second source/drain region are a same source/drain region.
PNG
media_image1.png
648
372
media_image1.png
Greyscale
However, figs. 3C-3D of Yoon discloses that source/drain of programming device and a reading device can be combined to form a single source/drain region by removing the Dummy device DGS, as disclosed in par [0049] of Yoon in order to achieve the reduction of the cell area, as shown in FIG. 3D, the writing gate electrode WG and the reading gate electrode RG constituting the single unit cell may be formed to share the source/drain junction region 120 therebetween.
Therefore, it would have been obvious to form a structure wherein the third source/drain region and the second source/drain region are a same source/drain region in order to achieve the reduction of the cell area.
Yoon does not disclose of a first word line and that the first gate RGS coupled to the first word line.
PNG
media_image3.png
450
443
media_image3.png
Greyscale
However, fig. 9 of Wu discloses a structure comprising:
a word line WLR;
a bit line BLR; and
an anti-fuse cell comprising:
a first reading device 540 comprising:
a first gate (that of 544);
a first source/drain region couple to the bit line BLR; and
a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the first gate;
In view of such teaching, it would have been obvious to form a structure of Yoon further comprising a first word line and that the first gate of the reading device coupled to the first word line such as taught by Wu in order to be able ot select proper memory cell.
Regarding claim 16, figs. 4-5 of Yoon discloses further comprising:a second anti-fuse cell comprising:a second programming device comprising:a fifth gate;a ninth source/drain region coupled to the eighth source/drain region;and a tenth source/drain region, wherein the ninth source/drain region and the tenth source/drain region are on opposite sides of the fifth gate,wherein the first to tenth source/drain regions are included in a continuous active region including a semiconductor material.
Regarding claim 17, fig. 4-5 of Yoon discloses further comprising: the second anti-fuse cell further comprises: a second reading device comprising:a sixth gate coupled to the second word line;an eleventh source/drain region coupled to the tenth source/drain region;and a twelfth source/drain region coupled to the first bit line, wherein the eleventh source/drain region and the twelfth source/drain region are on opposite sides of the sixth gate.
Fig. 10 of Wu discloses a second word line.
In view of such teaching, it would have been obvious to form a structure of Yoon and Wu further comprising a second word line such as taught by Wu in order to be able ot select proper memory cell for the second anti-fuse cell.
Regarding claim 18, figs. 4-5 of Yoon discloses wherein the second anti-fuse cell further comprises:a third dummy device comprising:a fifth gate;a ninth source/drain region coupled to the eighth source/drain region; and a tenth source/drain region, wherein the ninth source/drain region and the tenth source/drain region are on opposite sides of the fifth gate.
Regarding claim 19, figs. 4-5 of Yoon discloses further comprising: the second anti-fuse cell further comprises:a second programming device comprising:a sixth gate;an eleventh source/drain region coupled to the tenth source/drain region; and a twelfth source/drain region, wherein the eleventh source/drain region and the twelfth source/drain region are on opposite sides of the sixth gate; and a second reading device comprising:a seventh gate coupled to the second word line;a thirteenth source/drain region coupled to the twelfth source/drain region; anda fourteenth source/drain region coupled to the first bit line, wherein the thirteenth source/drain region and the fourteenth source/drain region are on opposite sides of the seventh gate, andwherein the first to fourteenth source/drain regions are included in a continuous active region including a semiconductor material.
Fig. 10 of Wu discloses a second word line.
In view of such teaching, it would have been obvious to form a structure of Yoon and Wu further comprising a second word line such as taught by Wu in order to be able ot select proper memory cell for the second anti-fuse cell.
Regarding claim 20, figs. 4-5 of Yoon discloses wherein the third gate, the fourth gate and the fifth gate are coupled together, and configured to receive a reference voltage from a reference voltage supply.
PNG
media_image2.png
742
1263
media_image2.png
Greyscale
Regarding claim 21, fig. 4-5 of Yoon discloses a structure comprising:
a bit line; and
an anti-fuse cell comprising:
a first reading device comprising:
a first gate;
a first source/drain region coupled to the bit line; and
a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the first gate;
a first programming device comprising: a second gate; and
a third source/drain region coupled to the second source/drain region; and
a fourth source/drain region, wherein the third source/drain region and the fourth source/drain region are on opposite sides of the second gate; and
a first dummy device comprising:
a third gate;
a fifth source/drain region directly coupled to the fourth source/drain region; and
a sixth source/drain region, wherein the fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate, the first dummy device corresponding to a first non-functional transistor; and
a second anti-fuse cell comprising: a second dummy device.
Yoon does not disclose of a first word line and that the first gate RGS coupled to the first word line.
PNG
media_image3.png
450
443
media_image3.png
Greyscale
However, fig. 9 of Wu discloses a structure comprising:
a word line WLR;
a bit line BLR; and
an anti-fuse cell comprising:
a first reading device 540 comprising:
a first gate (that of 544);
a first source/drain region couple to the bit line BLR; and
a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the first gate;
In view of such teaching, it would have been obvious to form a structure of Yoon further comprising a first word line and that the first gate of the reading device coupled to the first word line such as taught by Wu in order to be able ot select proper memory cell.
Regarding claim 22, figs. 4-5 of Yoon discloses wherein the second anti-fuse cell further comprises: a second programming device; and a second reading device, wherein the second dummy device is between the first dummy device and the second programming device.
Regarding claim 23, figs. 4-5 of Yoon discloses wherein the second programming device comprises: a fourth gate; and a seventh source/drain region on one side of the fourth gate, wherein the first to seventh source/drain regions are included in a continuous active region including a semiconductor material.
Regarding claim 24, figs. 4-5 of Yoon discloses wherein the second dummy device comprises: a fifth gate; an eighth source/drain region coupled to the sixth source/drain region; and a ninth source/drain region coupled to the seventh source/drain region, wherein the eighth source/drain region and the ninth source/drain region are on opposite sides of the fifth gate.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis Sue can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Prosecution Insights