Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election of Group I ( Claims 1 – 15 ) with traverse, in the reply filed on 12/1/2025 is acknowledged. Claims 16 – 19 are withdrawn. Claims 20 – 21 are canceled. Claims 22 – 23 are added.
Newly submitted claims 22 – 23 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
I. Claims 1 – 15, drawn to an integrated circuit structure, classified in H10D 30/014.
II. Claims 22 – 23, drawn to an integrated circuit structure, classified in H10D 30/6729.
Inventions I and II are directed to related product. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions have a materially different design. Inventions I requires a first body of dielectric material on a first side of the source or drain region, and a second body of dielectric material on a second side of the source or drain region; wherein a first section of the upper portion of the contact … and a second section of the upper portion of the contact; an imaginary horizontal line; while invention II requires wherein an entire perimeter of the upper portion is directly adjacent to the body of dielectric material.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 22 – 23 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chio ( Pub. No. US 20190148503 A1 ), hereinafter Choi.
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Regarding Independent Claim 1 (Original), Choi teaches an integrated circuit structure, comprising:
a source or drain region ( Choi, FIG. 3B, FIG. 4B, SD; [0069], source/drain regions SD ); and
a contact ( Choi, FIG. 3B, FIG. 4B, CA, CP, BL; [0078], contacts CA, conductive pillar CP, barrier layer BL ) having (i) an upper portion ( Choi, FIG. 3B, CA in 155 and 150; FIG. 4B, CA above SDT; [0074], first and second interlayered insulating layers 150 and 155 ; [0086], top surface SDT of the source/drain region SD ) outside the source or drain region and (ii) a lower portion ( FIG. 4B, CA below SDT and in RC; [0086], recess region RC ) extending within the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ), wherein the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ) wraps around the lower portion ( FIG. 4B, CA below SDT and in RC; [0086], recess region RC ) of the contact, such that an entire perimeter of the lower portion (FIG. 4B, CA below SDT and in RC) of the contact is adjacent to the source or drain region ( Choi, [0090], the upper region of the source/drain region SD may enclose the lower portion of the contact CA and the metal silicide layer SC, and thus, it is possible to reduce electric resistance between the contact CA and the source/drain region SD; [0086], A top surface SDT of the source/drain region SD may be higher than a bottom surface CAB of the contact CA ).
Regarding Claim 2 (Original), Choi teaches the integrated circuit structure as claimed in claim 1, on which this claim is dependent, Choi further teaches: further comprising:
a first body of dielectric material ( Choi, FIG. 3B, FIG. 4B, 150 on the left of SD; [0071], a first interlayered insulating layer 150 ) on a first side of the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ), and a second body of dielectric material ( Choi, FIG. 3B, FIG. 4B, 150 on the right of SD; [0071], a first interlayered insulating layer 150 ) on a second side of the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ), such that the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ) is laterally between the first ( Choi, FIG. 3B, FIG. 4B, 150 on the left of SD ) and second ( Choi, FIG. 3B, FIG. 4B, 150 on the right of SD ) bodies of dielectric material, wherein at least a corresponding section of the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ) is in contact with each of the first ( Choi, FIG. 3B, FIG. 4B, 150 on the left of SD ) and second ( Choi, FIG. 3B, FIG. 4B, 150 on the right of SD ) bodies of dielectric material,
wherein a first section ( Choi, FIG. 3B, left part of CA in 150 and 155 ) of the upper portion ( Choi, FIG. 3B, CA in 155 and 150 ) of the contact is laterally between the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ) and the first body ( Choi, FIG. 3B, FIG. 4B, 150 on the left of SD ) of dielectric material, and a second section ( Choi, FIG. 3B, right part of CA in 150 and 155 ) of the upper portion of the contact is laterally between the source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ) and the second body ( Choi, FIG. 3B, FIG. 4B, 150 on the right of SD ) of dielectric material.
Regarding Claim 3 (Original), Choi teaches the integrated circuit structure as claimed in claim 2, on which this claim is dependent, Choi further teaches:
wherein an imaginary horizontal line passes through the first body of dielectric material ( Choi, FIG. 3B, FIG. 4B, 150 on the left of SD; SP on the left of SD;[0080], spacers SP ), the first section ( Choi, FIG. 3B, left part of CA in 150 and 155 ) of the upper portion ( Choi, FIG. 3B, CA in 155 and 150 ) of the contact ( Choi, FIG. 3B, FIG. 4B, CA, CP, BL ), and the source or drain region ( Choi, FIG. 3B, left protrusion part of SD ).
Regarding Claim 4 (Original), Choi teaches the integrated circuit structure as claimed in claim 3, on which this claim is dependent, Choi further teaches:
wherein the imaginary horizontal line further passes through the lower portion ( FIG. 4B, CA below SDT and in RC; [0086], recess region RC ) of the contact ( Choi, FIG. 3B, FIG. 4B, CA, CP, BL ).
Regarding Claim 5 (Original), Choi teaches the integrated circuit structure as claimed in claim 3, on which this claim is dependent, Choi further teaches:
wherein the imaginary horizontal line further passes through the second section ( Choi, FIG. 3B, right part of CA in 150 and 155 ) of the upper portion of the contact ( Choi, FIG. 3B, FIG. 4B, CA, CP, BL ), and the second body of dielectric material ( Choi, FIG. 3B, FIG. 4B, 150 on the right of SD; SP on the right of SD;[0080], spacers SP ).
Regarding Claim 6 (Original), Choi teaches the integrated circuit structure as claimed in claim 3, on which this claim is dependent, Choi further teaches:
wherein the first section ( Choi, FIG. 3B, left part of CA in 150 and 155 ) of the upper portion ( Choi, FIG. 4B, CA in top portion of RC ) of the contact has a bottom surface ( Choi, FIG. 4B, SPB; [0088], bottom surface SPB of the spacer SP ) that resides in an imaginary horizontal plane which is lower than another imaginary horizontal plane ( Choi, FIG. 3B, SDT; [0088], top surface SDT of the source/drain region SD ) in which a top surface of the source or drain region ( Choi, FIG. 4B, SD ) resides.
Regarding Claim 7 (Original), Choi teaches the integrated circuit structure as claimed in claim 1, on which this claim is dependent, Choi further teaches:
wherein the source or drain region is a first source or drain region ( Choi, FIG. 2, the CA above the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) of a first device, and wherein the integrated circuit structure further comprises:
a second source or drain region ( Choi, FIG. 2, the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) of a second device, and a third source or drain region ( Choi, FIG. 2, the CA below the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) of a third device;
a first body ( Choi, FIG. 3A, 150 on the left of SD; FIG. 3B, FIG. 4B, 150 on the left of SD ) of dielectric material laterally between the first source or drain region and the second source or drain region, and a second body ( Choi, FIG. 3A, 150 on the right of SD; FIG. 3B, FIG. 4B, 150 on the right of SD ) of dielectric material laterally between the first source or drain region and the third source or drain region;
a first gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135; FIG. 3A, AF; [0069], active fins AF ) including a first gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the left of CHR ), and a second gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135, on the left or right of the first gate electrode 135; FIG. 3A, AF; [0069], active fins AF, on the left or right of the first active fin AF )including a second gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the right of CHR ), wherein the first, second, and third source or drain regions are laterally between the first gate stack and the second gate stack ( Choi, FIG. 2, multiples of contact CA are laterally between 135; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ),
wherein the upper portion ( Choi, FIG. 3B, CA in 150 ) of the contact is in contact with the first gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the left of CHR ), the second gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the right of CHR ), the first body ( Choi, FIG. 3A, 150 on the left of SD; FIG. 3B, FIG. 4B, 150 on the left of SD ) of dielectric material, and the second body ( Choi, FIG. 3A, 150 on the right of SD; FIG. 3B, FIG. 4B, 150 on the right of SD ) of dielectric material ( Choi, FIG. 2, [0071], The gate spacers 125 may extend along the gate electrodes 135 or parallel to the first direction D1 ).
Regarding Claim 8 (Original), Choi teaches the integrated circuit structure as claimed in claim 1, on which this claim is dependent, Choi further teaches:
wherein the source or drain region is a first source or drain region ( Choi, FIG. 2, the CA above the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) of a first device, and wherein the integrated circuit structure further comprises:
a second source or drain region ( Choi, FIG. 2, the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) of a second device, and a third source or drain region ( Choi, FIG. 2, the CA below the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) of a third device;
a first body ( Choi, FIG. 3A, 150 on the left of SD; FIG. 3B, FIG. 4B, 150 on the left of SD ) of dielectric material laterally between the first source or drain region and the second source or drain region, and a second body ( Choi, FIG. 3A, 150 on the right of SD; FIG. 3B, FIG. 4B, 150 on the right of SD ) of dielectric material laterally between the first source or drain region and the third source or drain region;
a first gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135; FIG. 3A, AF; [0069], active fins AF ) including a first gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the left of CHR ), and a second gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135, on the left or right of the first gate electrode 135; FIG. 3A, AF; [0069], active fins AF, on the left or right of the first active fin AF ) including a second gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the right of CHR ), wherein the first, second, and third source or drain regions are laterally between the first gate stack and the second gate stack ( Choi, FIG. 2, multiples of contact CA are laterally between 135; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ),
wherein the upper portion ( Choi, FIG. 3B, CA in 150 ) of the contact is adjacent to the first gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the left of CHR ), the second gate spacer ( Choi, FIG. 3B, 125; [0071], Gate spacers 125, on the right of CHR ), the first body ( Choi, FIG. 3A, 150 on the left of SD; FIG. 3B, FIG. 4B, 150 on the left of SD ) of dielectric material, and the second body ( Choi, FIG. 3A, 150 on the right of SD; FIG. 3B, FIG. 4B, 150 on the right of SD ) of dielectric material.
Regarding Claim 9 (Original), Choi teaches the integrated circuit structure as claimed in claim 8, on which this claim is dependent, Choi further teaches: further comprising:
a third body ( Choi, FIG. 3A, 3B, 4A; SP; [0080], spacer SP may be provided to enclose a sidewall of the contact CA ) of dielectric material wrapping around the upper portion ( Choi, FIG. 3B, CA in 155 and 150 ) of the contact, wherein the third body ( Choi, FIG. 3A, 3B, 4A; SP ) of dielectric material is (i) between the upper portion ( Choi, FIG. 3B, CA in 150 ) and the first gate spacer ( Choi, FIG. 3B, 125, on the left of CHR ), (ii) between the upper portion ( Choi, FIG. 3B, CA in 150 ) and the second gate spacer ( Choi, FIG. 3B, 125, on the right of CHR ), (iii) between the upper portion ( Choi, FIG. 3B, CA in 150 ) and the first body ( Choi, FIG. 3A, 150 on the left of SD ) of dielectric material, and (iv) between the upper portion ( Choi, FIG. 3B, CA in 150 ) and the second body ( Choi, FIG. 3A, 150 on the right of SD ) of dielectric material.
Regarding Claim 10 (Original), Choi teaches the integrated circuit structure as claimed in claim 9, on which this claim is dependent, Choi further teaches:
wherein an entire perimeter of the upper portion ( Choi, FIG. 3B, CA in 155 and 150 ) is adjacent to the third body ( Choi, FIG. 3A, 3B, 4A; SP; [0080], spacer SP ) of dielectric material.
Regarding Claim 11 (Original), Choi teaches the integrated circuit structure as claimed in claim 8, on which this claim is dependent, Choi further teaches:
wherein the contact ( Choi, FIG. 3B, FIG. 4B, CA, CP, BL ) is a first contact, the upper portion is a first upper portion ( Choi, FIG. 3B, CA in 155 and 150 ), and the lower portion ( FIG. 4B, CA below SDT and in RC ) is a first lower portion, and wherein the integrated circuit structure further comprises:
a second contact ( Choi, FIG. 2, multiples of contact CA are laterally between 135; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) having (i) a second upper portion ( Choi, FIG. 3B, CA in 155 and 150; FIG. 4B, CA above SDT ) outside the second source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ) and (ii) a second lower portion ( FIG. 4B, CA below SDT and in RC ) extending within the second source or drain region ( Choi, FIG. 3B, FIG. 4B, SD ), wherein the second source or drain region wraps around the second lower portion of the second contact ( Choi, [0090], the upper region of the source/drain region SD may enclose the lower portion of the contact CA and the metal silicide layer SC, and thus, it is possible to reduce electric resistance between the contact CA and the source/drain region SD; [0086], A top surface SDT of the source/drain region SD may be higher than a bottom surface CAB of the contact CA ).
Regarding Claim 12 (Original), Choi teaches the integrated circuit structure as claimed in claim 8, on which this claim is dependent, Choi further teaches: further comprising:
first one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprising semiconductor material ( Choi, [0069], Each of the active fins AF may include source/drain regions SD and a channel region CHR ) extending from the first source or drain region ( Choi, FIG. 2, the CA above the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) towards the first gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135 ), wherein the first gate stack wraps around ( Choi, [0072], For example, the gate dielectric layers 134 may cover top and side surfaces of the active fins AF ) the first one or more bodies; and
second one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprising semiconductor material ( Choi, [0069], Each of the active fins AF may include source/drain regions SD and a channel region CHR ) extending from the first source or drain region ( Choi, FIG. 2, the CA above the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) towards the second gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135, on the left or right of the first gate electrode 135; FIG. 3A, AF; [0069], active fins AF, on the left or right of the first active fin AF ), wherein the second gate stack wraps around ( Choi, [0072], For example, the gate dielectric layers 134 may cover top and side surfaces of the active fins AF ) the second one or more bodies.
Regarding Claim 13 (Original), Choi teaches the integrated circuit structure as claimed in claim 12, on which this claim is dependent, Choi further teaches: further comprising:
third one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprising semiconductor material ( Choi, [0069], Each of the active fins AF may include source/drain regions SD and a channel region CHR ) extending from the second source or drain region ( Choi, FIG. 2, the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) towards the first gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135 ), the first gate stack wrapping around ( Choi, [0072], For example, the gate dielectric layers 134 may cover top and side surfaces of the active fins AF ) the third one or more bodies;
fourth one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprising semiconductor material ( Choi, [0069], Each of the active fins AF may include source/drain regions SD and a channel region CHR ) extending from the second source or drain region ( Choi, FIG. 2, the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) towards the second gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135, on the left or right of the first gate electrode 135; FIG. 3A, AF; [0069], active fins AF, on the left or right of the first active fin AF ), the second gate stack wrapping around ( Choi, [0072], For example, the gate dielectric layers 134 may cover top and side surfaces of the active fins AF ) the fourth one or more bodies;
fifth one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprising semiconductor material ( Choi, [0069], Each of the active fins AF may include source/drain regions SD and a channel region CHR ) extending from the third source or drain region ( Choi, FIG. 2, the CA below the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) towards the first gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135 ), the first gate stack wrapping around ( Choi, [0072], For example, the gate dielectric layers 134 may cover top and side surfaces of the active fins AF ) the fifth one or more bodies; and
sixth one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprising semiconductor material ( Choi, [0069], Each of the active fins AF may include source/drain regions SD and a channel region CHR ) extending from the third source or drain region ( Choi, FIG. 2, the CA below the CA where II II’ and III III’ are crossed; [0077], contact CA may be connected to a corresponding one of the source/drain regions SD ) towards the second gate stack ( Choi, FIG. 2, 135; [0070], gate electrodes 135, on the left or right of the first gate electrode 135; FIG. 3A, AF; [0069], active fins AF, on the left or right of the first active fin AF ), the second gate stack wrapping around ( Choi, [0072], For example, the gate dielectric layers 134 may cover top and side surfaces of the active fins AF ) the sixth one or more bodies.
Regarding Claim 14 (Original), Choi teaches the integrated circuit structure as claimed in claim 12, on which this claim is dependent, Choi further teaches:
wherein each of the first one or more bodies and the second one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprises a vertical stack of nanoribbons, nanowires ( Choi, [0070], In other words, the gate electrodes 135 may be provided to cross the active fins AF protruding between the device isolation layers 104, and each of them may be a line-shaped structure extending in the first direction D1 ), or nanosheets.
Regarding Claim 15 (Original), Choi teaches the integrated circuit structure as claimed in claim 12, on which this claim is dependent, Choi further teaches:
wherein each of the first one or more bodies and the second one or more bodies ( Choi, FIG. 3A, FIG. 3B, AF; [0069], active fins AF ) comprises a fin.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817