Detail Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is a non-final office action in response to the communication filed 8/19/2025 and phone conversation on 12/4/2025.
Claims 1-20 are currently pending.
Claims 3, 4, and 5 have been withdrawn.
Claims 1, 2, and 6-20 have been examined.
Election/Restriction
Applicant initially elected Species B with the understanding that they would have claims 1-5 and 11-15. However on further consideration the Examiner realized that the description of Species B as defined by Fig. 5C and the specification starting at [0055] better described claims 3, 4, 5. And that Species A as defined by Fig. 5B and specification starting at [0051] would describe claims 1, 2, and 11-15.
Examiner Heim Kirin Grewal and Attorney Justin Brask Reg. No 61,080 as the Applicant’s Representative on 12/4/2025 and clarified that the intention of the election of the species of claim 1 without traverse and therefore elects Species A as defined by Fig. 5B. Therefore claims 1, 2, 11-15 and claims 6-10 and 16-20 (which are currently considered generic) are examined. This election was made without traverse in the a telephone interview with the Examiner Heim Kirin Grewal and Attorney Justin Brask Reg. No 61,080 on 12/4/2025.
Furthermore, claims 3, 4, and 5 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species B, there being no allowable linking claim.
Drawings
The drawings are objected to because no figures appear to give a z-direction the vertical direction can be implied but vertices for x, y, and z explicitly saying the directions (including the vertical direction) are appreciated as the direction of the cut appears to critical for claims 1 and 11 and those that depend thereon. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimbo US 20190165186 A1 (hereinafter Shimbo).
Regarding claim 1, Shimbo discloses:
An integrated circuit structure (Fig. 2 and 3), comprising:
a stack of horizontal nanowires along a vertical direction; (Fig. 3, nanowires 111 are in nanowire FETs including T1.)
a conductive contact laterally (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b.) adjacent to a source or drain region (source/drain region defined by pads 21 and 23) of the stack of horizontal nanowires, the conductive contact having a cut in the vertical direction; and (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b. and have a vertical cut that separates interconnects 45a and 45b.)
a gate stack over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack laterally spaced apart from the conductive contact. (Fig. 2, gate electrode 31p)
Regarding claim 2, Shimbo further discloses:
a second conductive contact laterally (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnect 41C) adjacent to a second source or drain region (source/drain region as defined by pads 22 and 24) of the stack of horizontal nanowires, the second conductive contact having no cut in the vertical direction. (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnect 41C and have no cut that separates 45c and 45d.)
Regarding claim 6, Shimbo discloses:
An integrated circuit structure, comprising:
a first stack of horizontal nanowires; (nanowires 111 defined by FET P1 provided by p-type transistor areas PA, [0031])
a second stack of horizontal nanowires; (nanowires 111 defined by FET N1 provided by n-type transistor areas NA, [0031])
a conductive contact (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b.) laterally adjacent to a source or drain region of the first stack (source/drain region defined by pad 21) of horizontal nanowires and laterally adjacent to a source or drain region of the second stack (source/drain region defined by pad 23) of horizontal nanowires, the conductive contact having a cut between the first stack of horizontal nanowires and the second stack of horizontal nanowires; and (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b. and have a vertical cut that separates interconnects 45a and 45b.)
a gate stack over the first stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires of the first stack of horizontal nanowires, (Fig. 2, gate electrode 31p surrounding the nanowires 111 of PA) and the gate stack over the second stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires of the second stack of horizontal nanowires, (Fig. 2, gate electrode 31p surrounding the nanowires 111 of NA) the gate stack laterally spaced apart from the conductive contact. (Fig.2)
Regarding claim 7, Shimbo further discloses:
a second conductive contact (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnect 41C) laterally adjacent to a second source or drain region of the first stack of horizontal nanowires (source/drain region defined by pad 22) and laterally adjacent to a second source or drain region of the second stack of horizontal nanowires, (source/drain region defined by pad 24) the second conductive contact continuous between the first stack of horizontal nanowires and the second stack of horizontal nanowires. (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnect 41C and have no cut that separates 45c and 45d.)
Regarding claim 8, Shimbo further discloses:
wherein the first stack of horizontal nanowires has a first conductivity type (nanowires 111 defined by FET P1 provided by p-type transistor areas PA, [0031]), and the second stack of horizontal nanowires has a second conductivity type. (nanowires 111 defined by FET N1 provided by n-type transistor areas NA, [0031])
Regarding claim 9, Shimbo further discloses:
wherein the first stack of horizontal nanowires are P-channel nanowires, (nanowires 111 defined by FET P1 provided by p-type transistor areas PA, [0031]), and the second stack of horizontal nanowires are N- channel nanowires. (nanowires 111 defined by FET N1 provided by n-type transistor areas NA, [0031])
Regarding claim 10, Shimbo further discloses:
wherein the gate stack is continuous between the first stack of horizontal nanowires and the second stack of horizontal nanowires. (Fig. 2, gate 31p is continuous between the nanowires of PA and NA)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 20140197377 A1 (hereinafter Kim) in view of Shimbo.
Regarding claim 11, Shimbo discloses:
the component including an integrated circuit structure (Fig. 2 and 3), comprising:
a stack of horizontal nanowires along a vertical direction; (Fig. 3, nanowires 111 are in nanowire FETs including T1.)
a conductive contact laterally (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b.) adjacent to a source or drain region (source/drain region defined by pads 21 and 23) of the stack of horizontal nanowires, the conductive contact having a cut in the vertical direction; and (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b. and have a vertical cut that separates interconnects 45a and 45b.)
a gate stack over the stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires, the gate stack laterally spaced apart from the conductive contact. (Fig. 2, gate electrode 31p)
While Shimbo does that the FET structure would be used in an integrated circuit (Shimbo, [0003]), therefore implying a board and a component coupled to the board for use in devices such as a laptop or other electronics. However, Shimbo does not appear to directly disclose:
A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
Kim, which teaches a computing device which contains an integrated circuit (Kim, [0079]), discloses:
A computing device (Kim, Fig. 7, computing device 700), comprising:
a board; and (board 702)
a component coupled to the board ([0074], the computing device may including a number of components.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Shimbo to have a board, and a component coupled to the board as taught by Kim for purposes of implementing the computing device in electronics such as a laptop, a netbook, etc. (Kim, [0080])
Regarding claim 12, Kim and Shimbo teach the elements of claim 11 as recited above.
Kim further discloses:
a memory (DRAM and ROM) coupled to the board (702). (Kim, Fig. 7, [0075])
Regarding claim 13, Kim and Shimbo teach the elements of claim 11 as recited above.
Kim further discloses:
a communication chip (706) coupled to the board. (702) (Kim, Fig.7, [0079])
Regarding claim 14, Kim and Shimbo teach the elements of claim 11 as recited above.
Kim further discloses:
wherein the component is a packaged integrated circuit die. (Kim, [0077])
Regarding claim 15, Kim and Shimbo teach the elements of claim 11 as recited above.
Kim further discloses:
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. (Kim, [0074] - [0076])
Regarding claim 16 Shimbo, discloses:
the component including an integrated circuit structure (Fig. 2 and 3), comprising:
a first stack of horizontal nanowires; (nanowires 111 defined by FET P1 provided by p-type transistor areas PA, [0031])
a second stack of horizontal nanowires; (nanowires 111 defined by FET N1 provided by n-type transistor areas NA, [0031])
a conductive contact (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b.) laterally adjacent to a source or drain region of the first stack (source/drain region defined by pad 21) of horizontal nanowires and laterally adjacent to a source or drain region of the second stack (source/drain region defined by pad 23) of horizontal nanowires, the conductive contact having a cut between the first stack of horizontal nanowires and the second stack of horizontal nanowires; and (Fig. 2, interconnect layer M1 that as part of VDD and VSS are made from interconnects 41a and 41b. and have a vertical cut that separates interconnects 45a and 45b.)
a gate stack over the first stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires of the first stack of horizontal nanowires, (Fig. 2, gate electrode 31p surrounding the nanowires 111 of PA) and the gate stack over the second stack of horizontal nanowires and surrounding a channel region of each of the horizontal nanowires of the second stack of horizontal nanowires, (Fig. 2, gate electrode 31p surrounding the nanowires 111 of NA) the gate stack laterally spaced apart from the conductive contact. (Fig.2)
While Shimbo does that the FET structure would be used in an integrated circuit (Shimbo, [0003]), therefore implying a board and a component coupled to the board for use in devices such as a laptop or other electronics. However, Shimbo does not appear to directly disclose:
A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
Kim, which teaches a computing device which contains an integrated circuit (Kim, [0079]), discloses:
A computing device (Kim, Fig. 7, computing device 700), comprising:
a board; and (board 702)
a component coupled to the board ([0074], the computing device may including a number of components.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Shimbo to have a board, and a component coupled to the board, the component including an integrated circuit structure as taught by Kim for purposes of implementing the computing device in electronics such as a laptop, a netbook, etc. (Kim, [0080])
Regarding claim 17, Kim and Shimbo teach the elements of claim 16 as recited above.
Kim further discloses:
a memory (DRAM and ROM) coupled to the board (702). (Kim, Fig. 7, [0075])
Regarding claim 18, Kim and Shimbo teach the elements of claim 16 as recited above.
Kim further discloses:
a communication chip (706) coupled to the board. (702) (Kim, Fig.7, [0079])
Regarding claim 19, Kim and Shimbo teach the elements of claim 16 as recited above.
Kim further discloses:
wherein the component is a packaged integrated circuit die. (Kim, [0077])
Regarding claim 20, Kim and Shimbo teach the elements of claim 16 as recited above.
Kim further discloses:
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. (Kim, [0074] - [0076])
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (US 20200144264 A1) – a 3d Vertical FET which includes nanowires and has a layout in Fig. 1 as described by claim 1 and 6.
Kishishita et al. (US 20190074297 A1) – Fig. 1 multiple devices as described by claim 1 and 6.
Cheng et al. (US 20150263088 A1) – A stacked nanowires device that is affixed to a motherboard and incorporated into integrated circuit chip which has discrete circuit elements. [0095]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893