7DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub. No. US 2022/0037192 A1) in view of Wang et al. (US 2021/0305262 A1).
Regarding claim 1, Yu teaches an integrated circuit structure (figs. 40A-40C), comprising:
a front-side structure (¶¶ 0065, 0070: 109 and/or 120) comprising:
a device layer (¶ 0065: 109) having a plurality of nanowire-based transistors (¶¶ 0011, 0065: 109 comprises nanowire-based FETs); and
a plurality of metallization layers (¶¶ 0066, 0073: interconnect structure 122, including plurality of metal layers 122) above the nanowire-based transistors of the device layer (fig. 40A among others: 120 disposed above 109), wherein a single one of the metallization layers includes an array of uninterrupted lines without an intervening power line (fig. 40A: 120 includes array of uninterrupted lines 122 without an intervening power line); and
a backside structure (¶ 0065: 164) below the nanowire-based transistors of the device layer (fig. 40A: 164 disposed below 109), the backside structure including a ground metal line (¶ 1016: 164 includes lines for provide ground connections).
Yu is silent to the uninterrupted lines comprising signal lines.
Wang teaches an integrated circuit structure (figs. 3-5 among others) including uninterrupted signal lines without an intervening power line (¶¶ 0041, 0058: MLI metallization layers, similar to 122 of Yu, provide the signal lines on the frontside of the device of FIGS. 3A or 4A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the uninterrupted lines of Yu as signal lines, as a means to facilitate reading or writing to the data stored in a memory cell (Wang, ¶ 0015, Yu, ¶ 0074), as well as decreasing resistance and capacitance, which thereby improves performance (Wang, ¶ 0018).
Regarding claim 2, Yu in view of Wang teaches the integrated circuit structure of claim 1, wherein the backside structure includes a stack of backside conductive structures that terminate at a conductive bump (Yu, ¶ 0106 & fig. 40A: 164 includes a stack of conductive structures 162/168 that terminates at bump 170).
Regarding claim 3, Yu in view of Wang teaches the integrated circuit structure of claim 1, wherein the device layer of the front-side structure further includes a trench contact, a gate contact or a contact via (Yu, ¶¶ 0065, 0072 & fig. 40A: 120 includes contacts 112, 114 and or unlabeled conductive vias).
Regarding claim 4, Yu in view of Wang teaches the integrated circuit structure of claim 1, wherein the front-side structure comprises a deep via layer between the nanowire-based transistors of the device layer and the backside structure (Yu, ¶ 0044 & fig. 40A: via 130 disposed between 109 and 164).
Regarding claim 5, Yu in view of Wang teaches the integrated circuit structure of claim 1, wherein the nanowire-based transistors device layer are memory nanowire-based transistors (Yu, ¶ 0074: transistor comprised by memory circuit).
Regarding claim 6, Yu teaches an integrated circuit structure (figs. 40A-40C), comprising:
a front-side structure (¶¶ 0065, 0070: 109 and/or 120) comprising:
a device layer (¶ 0065: 109) having a plurality of fin-based transistors (¶¶ 0011, 0065: 109 comprises FinFETs); and
a plurality of metallization layers (¶ 0066: 122) above the fin-based transistors of the device layer (fig. 40A among others: 120 disposed above 109), wherein a single one of the metallization layers includes an array of uninterrupted lines without an intervening power line (fig. 40A: 120 includes array of uninterrupted lines 122 without an intervening power line); and
a backside structure (¶ 0065: 164) below the fin-based transistors of the device layer (fig. 40A: 164 disposed below 109), the backside structure including a ground metal line (¶ 1016: 164 includes lines for provide ground connections).
Yu is silent to the uninterrupted lines comprising signal lines.
Wang teaches an integrated circuit structure (figs. 3-5 among others) including uninterrupted signal lines without an intervening power line (¶¶ 0041, 0058: MLI metallization layers, similar to 122 of Yu, provide the signal lines on the frontside of the device of FIGS. 3A or 4A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the uninterrupted lines of Yu as signal lines, as a means to facilitate reading or writing to the data stored in a memory cell (Wang, ¶ 0015, Yu, ¶ 0074), as well as decreasing resistance and capacitance, which thereby improves performance (Wang, ¶ 0018).
Regarding claim 7, Yu in view of Wang teaches the integrated circuit structure of claim 6, wherein the backside structure includes a stack of backside conductive structures that terminate at a conductive bump (Yu, ¶ 0106 & fig. 40A: 164 includes a stack of conductive structures 162/168 that terminates at bump 170).
Regarding claim 8, Yu in view of Wang teaches the integrated circuit structure of claim 6, wherein the device layer of the front-side structure further includes a trench contact, a gate contact or a contact via (Yu, ¶¶ 0065, 0072 & fig. 40A: 120 includes contacts 112, 114 and or unlabeled conductive vias).
Regarding claim 9, Yu in view of Wang teaches the integrated circuit structure of claim 6, wherein the front-side structure comprises a deep via layer between the fin-based transistors of the device layer and the backside structure (Yu, ¶ 0044 & fig. 40A: via 130 disposed between 109 and 164).
Regarding claim 10, Yu in view of Wang teaches the integrated circuit structure of claim 6, wherein the fin-based transistors device layer are memory fin-based transistors (Yu, ¶ 0074: transistor comprised by memory circuit).
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Weber et al. (PG Pub. No. US 2021/0074703 A1) and Wang.
Regarding claim 11, Yu teaches an integrated circuit structure (figs. 40A-40C), comprising:
a front-side structure (¶¶ 0065, 0070: 109 and/or 120) comprising:
a device layer (¶ 0065: 109) having a plurality of nanowire-based transistors (¶¶ 0011, 0065: 109 comprises nanowire-based FETs); and
a plurality of metallization layers (¶ 0066: 122) above the nanowire-based transistors of the device layer (fig. 40A among others: 120 disposed above 109), wherein a single one of the metallization layers includes an array of uninterrupted lines without an intervening power line (fig. 40A: 120 includes array of uninterrupted lines 122 without an intervening power line); and
a backside structure (¶ 0065: 164) below the nanowire-based transistors of the device layer (fig. 40A: 164 disposed below 109), the backside structure including a ground metal line (¶ 1016: 164 includes lines for provide ground connections).
Yu fails to teach a computing device, comprising:
a board; and
a component coupled to the board, the component including the integrated circuit structure, and
the uninterrupted lines comprising signal lines.
Weber teaches a computing device (¶ 0107 & fig. 9: 900), comprising:
a board (¶ 0107: 902); and
a component (¶ 0107: 904, 906 among others) coupled to the board (fig. 9), the component including an integrated circuit structure (¶¶ 0035, 0039, 0110: at least component 904 and/or 906 includes an integrated circuit built in accordance with implementations of the disclosure).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the integrated circuit structure of Yu in the computing device of Weber, as a means to provide a computing device with reduced parasitic capacitance and reduced dopant contamination to greatly improve the performance of such devices (Weber, ¶ 0093).
Yu in view of Weber fails to teach the uninterrupted lines comprising signal lines.
Wang teaches an integrated circuit structure (figs. 3-5 among others) including uninterrupted signal lines without an intervening power line (¶¶ 0041, 0058: MLI metallization layers, similar to 122 of Yu, provide the signal lines on the frontside of the device of FIGS. 3A or 4A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the uninterrupted lines of Yu in view of Weber as signal lines, as a means to facilitate reading or writing to the data stored in a memory cell (Wang, ¶ 0015, Yu, ¶ 0074), as well as decreasing resistance and capacitance, which thereby improves performance (Wang, ¶ 0018).
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, combining the integrated circuit of Yu with the computing device of Weber and signal functionality of Wang would have yielded nothing more than predictable results.
Regarding claim 12, Yu in view of Weber and Wang teaches the computing device of claim 11, further comprising:
a memory (Weber, ¶ 0108) coupled to the board (Weber, fig. 9: memory such as DRAM and/or ROM coupled to board 902).
Regarding claim 13, Yu in view of Weber and Wang teaches the computing device of claim 11, further comprising:
a communication chip (Weber, ¶ 1017: 906) coupled to the board (Weber, 906 coupled to board 902).
Regarding claim 14, Yu in view of Weber and Wang teaches the computing device of claim 11, wherein the component is a packaged integrated circuit die (Weber, ¶ 0110: 900 includes packaged circuit die).
Regarding claim 15, Yu in view of Weber and Wang teaches the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Weber, ¶ 0107: 906 comprises a communication chip).
Regarding claim 16, Yu teaches an integrated circuit structure (figs. 40A-40C), comprising:
a front-side structure (¶¶ 0065, 0070: 109 and/or 120) comprising:
a device layer layer (¶ 0065: 109) having a plurality of fin-based transistors (¶¶ 0011, 0065: 109 comprises FinFETs); and
a plurality of metallization layers (¶ 0066: 122) above the fin-based transistors of the device layer (fig. 40A among others: 120 disposed above 109), wherein a single one of the metal layers includes an array of uninterrupted lines without an intervening power line (fig. 40A: 120 includes array of uninterrupted lines 122 without an intervening power line); and
a backside structure (¶ 0065: 164) below the fin-based transistors of the device layer (fig. 40A: 164 disposed below 109), the backside structure including a ground metal line (¶ 1016: 164 includes lines for provide ground connections).
Yu fails to teach a computing device, comprising:
a board; and
a component coupled to the board, the component including the integrated circuit structure, and
the uninterrupted lines comprising signal lines.
Weber teaches a computing device (¶ 0107 & fig. 9: 900), comprising:
a board (¶ 0107: 902); and
a component (¶ 0107: 904, 906 among others) coupled to the board (fig. 9), the component including an integrated circuit structure (¶¶ 0035, 0039, 0110: at least component 904 and/or 906 includes an integrated circuit built in accordance with implementations of the disclosure).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the integrated circuit structure of Yu in the computing device of Weber, as a means to provide a computing device with reduced parasitic capacitance and reduced dopant contamination to greatly improve the performance of such devices (Weber, ¶ 0093).
Yu in view of Weber fails to teach the uninterrupted lines comprising signal lines.
Wang teaches an integrated circuit structure (figs. 3-5 among others) including uninterrupted signal lines without an intervening power line (¶¶ 0041, 0058: MLI metallization layers, similar to 122 of Yu, provide the signal lines on the frontside of the device of FIGS. 3A or 4A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the uninterrupted lines of Yu in view of Weber as signal lines, as a means to facilitate reading or writing to the data stored in a memory cell (Wang, ¶ 0015, Yu, ¶ 0074), as well as decreasing resistance and capacitance, which thereby improves performance (Wang, ¶ 0018).
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, combining the integrated circuit of Yu with the computing device of Weber and signal functionality of Wang would have yielded nothing more than predictable results.
Regarding claim 17, Yu in view of Weber and Wang teaches the computing device of claim 16, further comprising:
a memory (Weber, ¶ 0108) coupled to the board (Weber, fig. 9: memory such as DRAM and/or ROM coupled to board 902).
Regarding claim 18, Yu in view of Weber and Wang teaches the computing device of claim 16, further comprising:
a communication chip (Weber, ¶ 1017: 906) coupled to the board (Weber, 906 coupled to board 902).
Regarding claim 19, Yu in view of Weber and Wang teaches the computing device of claim 16, wherein the component is a packaged integrated circuit die (Weber, ¶ 0110: 900 includes packaged circuit die).
Regarding claim 20, Yu in view of Weber and Wang teaches the computing device of claim 16, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Weber, ¶ 0107: 906 comprises a communication chip).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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