DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1, 23, and 26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 objected to because of the following informalities: In claim 1 ll. 7 after “liner”, a semicolon --;-- is missing.
Claim 26 object to because of the following informalities: In claim 26 ll. 7 after “liner”, a semicolon --;-- is missing.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2021/0375721) (“Chen”).
With regard to claim 26, fig. 3B of Chen discloses an electronic package 300, comprising: a first layer 120, wherein the first layer 120 is a dielectric material (“passivation layer 120 may be formed of silicon nitride”, par [0022]); a trace 130b on the first layer 130a; a pad 130a on the first layer 120; a liner 122 over the first layer 120, the trace 130b, and the pad 130a, wherein a first hole 140 is through the liner 122; a second layer 150 over the first layer 120, the trace 130b, the pad 130a, and the liner 122[;] a second hole (hole in 150 above 130a) through the second layer 150 over the pad 130a; and a via 172 through the second hole (opening 81) and the first hole 140, wherein the via 172 lands on the pad 130a, wherein the via 172 does not contact the liner 122.
With regard to claim 27, fig. 3B of Chen discloses that the liner 122 comprises silicon and nitrogen (“passivation layer 120 may be formed of silicon nitride”, par [0022]).
With regard to claim 28, fig. 1H of Chen discloses that surfaces of the trace 130b and the pad 130a are not roughened.
With regard to claim 29, fig. 1H of Chen discloses that the liner 122 is on sidewalls of the trace 130b and a top surface of the trace 130b.
With regard to claim 30, fig. 1H of Chen discloses that the second layer 150 comprises a dielectric material (“insulating layer 150 may include silicon oxide”, par [0027]).
With regard to claim 31, fig. 3B of Chen a third hole 140 is positioned between the trace 130b and the pad 130a.
With regard to claim 32, fig. 3B of Chen discloses that the second layer 150 contacts the first layer 120 through the third hole 140.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8-13, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Raghunathan et al. (US 2015/0357185) (“Raghunathan”) in view of Kim et al. (US 2009/0239369) (“Kim”).
With regard to claim 1, fig. 1g of Raghunathan discloses an electronic package (“package structure 120”, par [0017]), comprising: a first layer 126, wherein the first layer 126 is a dielectric material (“first CVD dielectric material”, par [0017]); a trace (rightmost “conductive material 120”, par [0017], fig. 1g) on the first layer ; a pad (leftmost conductive material 120, fig. 1g) on the first layer 126; a liner 127 over the first layer 126, the trace (rightmost conductive material 120, fig. 1g), and the pad (leftmost conductive material 120, fig. 1g), wherein a first hole (hole in 127 above leftmost 120, fig. 1g) is through the liner 127; and a second layer 124 over the first layer 126, the trace (rightmost 120), the pad (leftmost conductive material 120), and the liner 127[;] a second hole (opening in 124) through the second layer 124 over the pad (leftmost 120); and a via (via under leftmost 123) through the second hole (opening in 124) and the first hole (opening in 127), wherein the via lands (via under leftmost 123) on the pad (leftmost 120).
Raghunathan does not disclose that the via contacts a top surface of the liner.
However, fig. 11E of Kim discloses that the via 360 contacts a top surface of the liner 330a.
Therefore, it would have been obvious to one of ordinary skill in the art to form the via of Rahunathan with the width as taught in Kim in order to provide conductive patterns with improved device yield and limited void formation. See par [0004] of Kim.
With regard to claim 5, fig. 1g of Raghunathan discloses that the via (via above leftmost 120, fig. 1g) contacts a sidewall of the liner 127.
With regard to claim 8, fig. 1g of Raghunathan discloses that a third hole (hole in 127 between leftmost conductive material 120 and middle conductive material 120, fig. 1g) is positioned between the trace (rightmost conductive material 120, fig. 1g) and the pad (leftmost conductive material 120, fig. 1g).
With regard to claim 9, fig. 1g of Raghunathan discloses that the second layer 124 contacts the first layer 126 through the third hole (hole in 127 between leftmost conductive material 120 and middle conductive material 120, fig. 1g).
With regard to claim 10, fig. 1g of Raghunathan discloses that the liner 127 comprises silicon and nitrogen (“first CVD dielectric material 206 may comprise at least one of a silicon nitride”, par [0021]).
With regard to claim 11, fig. 1g of Raghunathan discloses that surfaces of the trace and the pad (“conductive material 120”, par [0017]) are not roughened (“no roughness”, par [0014]).
With regard to claim 12, fig. 1g of Raghunathan discloses that the liner 127 is on sidewalls of the trace (rightmost 120, fig. 1g) and a top surface of the trace (rightmost 120, fig. 1g).
With regard to claim 13, fig. 1g of Raghunathan discloses that the second layer 124 comprises a dielectric material (“second dielectric material 124”, par [0017]).
With regard to claim 23, fig. 1g of Raghunathan discloses that an electronic system, comprising: a board (“circuit board”, par [0027]); a package substrate (“package structure”, par [0017]) coupled to the board (“package structures may be coupled (e.g., a circuit board)”, par [0027]), wherein the package substrate (“package structure”, par [0017]) comprises: a first layer 126, wherein the first layer 126 is a dielectric material (“first CVD dielectric material”, par [0017]); a trace (rightmost 120, fig. 1g) over the first layer; a pad (leftmost 120, fig. 1g) on the first layer 126; a liner 127 over the first layer 126, the pad (leftmost 120, fig. 1g), and the trace (rightmost 120, fig. 1g), wherein a first hole (hole in 127, fig. 1g) is through the liner 127; and a second layer 124 over the first layer 126, the trace (rightmost 120), the pad (leftmost 120), and the liner 127; a second hole (opening in 124) through the second layer 124 over the pad (leftmost 120); a via (via under leftmost 123) through the second hole (opening in 124) and the first hole (opening in 127 under leftmost 123), wherein the via (via under leftmost 123) lands on the pad (leftmost 120), and a second layer over the first layer, the pad, the trace, and the liner; and a die (“die 162”, par [0029]) coupled to the package substrate (“package structure 120”, par [0017]).
Raghunathan does not disclose that the via contacts a top surface of the liner.
However, fig. 11E of Kim discloses that the via 360 contacts a top surface of the liner 330a.
Therefore, it would have been obvious to one of ordinary skill in the art to form the via of Rahunathan with the width as taught in Kim in order to provide conductive patterns with improved device yield and limited void formation. See par [0004] of Kim.
With regard to claim 24, fig. 1g of Raghunathan discloses that the liner 127 comprises silicon and nitrogen (“first CVD dielectric material 206 may comprise at least one of a silicon nitride”, par [0021]).
With regard to claim 25, fig. 1g of Raghunathan discloses that a portion of the first layer 126 directly contacts a portion of the second layer 124.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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