DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Applicant’s IDS submitted on 8/4/25, 6/16/25, and 6/29/22 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Status
Claims 6-14 are under consideration int this application.
Claims 1-5 are withdrawn as being directed to a non-elected device. The election was made in the response of 11/12/24.
Claim Rejections - 35 USC § 102
3In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gu et al., US 20220189848 A1, hereafter Gu.
Regarding claim 11, Gu discloses the following limitations:
A method of manufacturing a semiconductor device, the method comprising:
preparing an insulated circuit substrate (Figure 1A, substrate 130) including a conductive plate (Figure 1A, metal layer 131 and metal layer 133);
forming a recess (Figure 1A, recesses A1 and A2) having a groove-like shape (Figure 1B, A1 and A2 run up and down the substrate and are therefore groove like) in the conductive plate (Figure 1A, recesses A1 and A2 are in metal layer 131);
partially fixing a plate-like bonding member (Figure 1A, plate 120 Is partially fixed by grooves A1 and A2 and portion 122, which extend into the grooves) having a striped projection (Figures 1A and 1B show that portion 122 extend along the side of conductive-bonding component 120, making 122 striped) onto the conductive plate so that the striped projection conforms to the recess so as to fix a position of the plate-like bonding member on the conductive plate in a horizontal direction (Figure 1A and 1B shows that portions 122 are in the groove A1 and A2, and therefore fix conductive-bonding component 120);
mounting a semiconductor chip (Figure 1A, semiconductor component 110) on the plate-like bonding member (Shown, Figure 1A); and heating and melting the plate-like bonding member so as to form a bonding layer for bonding the insulated circuit substrate and the semiconductor chip to each other ([0033] discloses that component 120 is heated to reflow).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Saito, JP 04037054 A, hereafter Saito in view of Gu et al., US 20220189848 A1, hereafter Gu.
Note: cites to Saito refer to the translation submitted with the IDS of 6/16/25.
Regarding independent claim 6, Saito discloses the following limitations:
A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate including a conductive plate (Saito, Figure 6, heat sink 12);
fixing in a horizontal direction a plate-like bonding member (Saito, Figure 6, solder tablet 6, having a rivet-shape is pressed into recess 15) onto the conductive plate (Saito, Figure 2, heat sink 12), the plate-like bonding member and the conductive plate to be partially bonded to each other by a partially bonded part provided on an inner side of an outer circumference of the plate-like bonding member (Saito Figure 6, solder tablet 6 pressed into recess 15 of heatsink 12) so as to fix a position of the plate-like bonding member on the conductive plate in the horizontal direction (Saito, Figure 6, solder tablet 6 is fixed in a horizontal direction because it extends into recess 15);
mounting a semiconductor chip on the plate-like bonding member to form a stacked body (Saito, Figure 6, semiconductor pellet 4 is on top of solder 5, and the disclosure which states that Figure 6 is an example of a different shape of solder tablet 6 that can be used); and
heating the stacked body to melt the plate-like bonding member (Saito, page 4, discloses that the solder is heated and melted to fix the semiconductor pellet to the heat sink 12) so as to form a bonding layer for bonding the substrate and the semiconductor chip to each other (Figure 4, and page 4, which discloses that semiconductor pellet 4 is fixed to the heat sink 12).
Saito fails to disclose the following limitation:
an insulated circuit substrate
Gu discloses the following limitations:
an insulated circuit substrate (Gu, Figure 1A, substrate 130, including metal layer 131, dielectric 132, and metal layer 133)
Saito discloses a method that includes everything claimed except it attaches the semiconductor device to a heat sink instead of to an insulating circuit substrate. Gu discloses a method semiconductor device attached to an insulating substrate. One or ordinary skill in the art would have recognized that heat sinks and insulative substrates are known equivalents for mounting substrates for semiconductor devices within the semiconductor art. It would have been obvious to one of ordinary skill in the art to substitute an insulative substate for the heat sink resulting in the predictable result of attaching the semiconductor device to a substrate.
Regarding claim 7, Saito discloses the following limitations:
The method of manufacturing the semiconductor device of claim 6, wherein
the position of the plate-like bonding member in the horizontal direction is fixed by inserting a projection provided on the plate-like bonding member to a recess provided on the conductive plate (Saito, Figure 5, solder pellet 6 rivet-shaped and shaft is pressed into a recess).
Regarding claim 13, Saito discloses the following limitations:
The method of manufacturing the semiconductor device of claim 6, wherein
the partially bonded part is located inside an outer circumference of the semiconductor chip in a plan view (Saito, Figure 6 shows a recess in the center of the region where the chip is placed and Figure 4 which shows that the recesses are inside the outer circumference of the semiconductor chip).
Regarding claim 14, Saito discloses the following limitations:
The method of manufacturing the semiconductor device of claim 13, wherein
the partially bonded part does not stick out from the outer circumference of the semiconductor chip in the plan view (Saito, Figure 4 shows that solder 5 does not stick out past the semiconductor chip 4).
Claim 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Saito and Gu as applied to claim 6 above, and further in view of Sugiyama et al., JP S60166487 U, hereafter Sugiyama.
Note: cites to Saito refer to the translation submitted with the IDS of 6/16/25.
Regarding claim 8, Saito and Gu fail to disclose the following limitations:
The method of manufacturing the semiconductor device of claim 6, wherein
the position of the plate-like bonding member in the horizontal direction is fixed by bonding a part of the conductive plate and a part of the plate-like bonding member to each other by laser welding.
Sugiyama discloses the following limitations:
The method of manufacturing the semiconductor device of claim 6, wherein
the position of the plate-like bonding member in the horizontal direction is fixed by bonding a part of the conductive plate and a part of the plate-like bonding member to each other by laser welding (Sugiyama, Figure 1, discloses that Brazing metal 4 (also disclosed as foil or sheet-shaped solder or brazing material) is temporarily fixed to Base material 2, at temporary fixing part 3).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teaching of Sugiyama to the process of Saito and Gu because both Saito and Sugiyama teach methods to partially attach a solder sheet to metal piece (Saito used a part inserted into a recess and Sugiyama used a laser to spot weld portions) and subsequently melting the entire solder layer to join a different part to the to the metal. Because both methods are known to partially affix a solder sheet to a metal part, they are known equivalent methods for the purpose of partially affixing a solder plate to a metal part, therefore the combination of the two methods would have been obvious to one of ordinary skill. See MPEP 2144.06.
Regarding claim 12, Sugiyama discloses the following limitations:
The method of manufacturing the semiconductor device of claim 6, further comprising laser welding (Sugiyama, Figure 1, discloses locally temporarily fixing a sheet shaped solder using laser welding) at least a portion of the conductive plate and at least a portion of the plate-like bonding member (Sugiyama, Figure 1(c), temporary fixing part 3) to form one or more projections as alloy layers (Sugiyama, Figure 1(c), shows projections from Brazing metal 4 (also disclosed as foil or sheet-shaped solder or brazing material) into Base material 2, at temporary fixing part 3) including material of the plate-like bonding member and material of the conductive plate (Sugiyama, Figure 1(c), protrusions into the base material 2).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Saito, Gu and Sugiyama as applied to claim 8 above, and further in view of Kim et al., US 20200152876 A1, hereafter Kim.
Regarding claim 9, Saito, Gu, and Sugiyama fail to disclose the following limitations:
The method of manufacturing the semiconductor device of claim 8, further comprising,
before the laser welding, forming a recess at a position on a top surface of the plate-like bonding member to which heat is applied by the laser welding.
Kim discloses the following limitations:
The method of manufacturing the semiconductor device of claim 8, further comprising, before the laser welding, forming a recess at a position on a top surface of the bonding member to which heat is applied by the laser welding (Figure 1, 7, and [0098] which discloses hatching areas HA1 and HA2 formed in the top surface to increase the portion of the laser that is absorbed in the material being treated).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Kim to the process of Saito, Gu, and Sugiyama and to therefore have formed a hatch pattern in the top surface that is to be laser treated. Doing so it taught by Kim to increase the process efficiency and improve the characteristics of the welding.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Saito, Gu and Sugiyama as applied to claim 8 above, and further in view of Dubowski et al, US 20030194882 A1, hereafter Dubowski.
Saito, Gu and Sugiyama fail to disclose the following limitation:
The method of manufacturing the semiconductor device of claim 8, further comprising, before the laser welding, selectively forming a metal layer at a position on a top surface of the bonding member to which heat is applied by the laser welding.
Dubowski discloses the following limitation:
The method of manufacturing the semiconductor device of claim 8, further comprising, before the laser welding, selectively forming a metal layer at a position on a top surface of the bonding member to which heat is applied by the laser welding (Dubowski [0029] discloses forming an anti-reflection layer of silver on top of an electrode prior to laser processing).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Dubowski to the process of Saito, Gu and Sugiyama and to therefore have applied silver to the areas that would be subjected to laser treatment because Dubowski discloses that a silver anti-reflection coating allows enhances the coupling of a laser light to the layer below [0017] and that the laser fluence needed to ablate the aluminum to be much lower resulting in less damage to the underlaying layers [0031].
Response to Arguments
Applicant’s arguments with respect to claim(s) 6-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s argument that the claims as amended define over the prior art are not persuasive in view of the new ground of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shimada et al., JP 2010012509 A, discloses busbar (20) on an insulating sheet (50) that has protrusions (51) within the outer edges of a transistor chip.
Okumura et al., US 20070057373 A1, discloses different shapes for the solder grooves.
Nakagawa et al., JP 2016203217 A, discloses the use of laser irradiation to partly join solder to a tabular conductor.
Kadoguchi et al., US 20160225690 A1, discloses a soldering foil that is used to connect metal plates where the groove can be inside or outside of the upper plate.
Shibata et al., JP H08222586 A, discloses JP H08222586 A discloses a solder sheet used to bond a semiconductor chip to a member such as a lead frame, a heat sink, where a thin tools is pressed against the solder sheet on a heat sink to make a plurality of dents on the surface of the heat sink.
Stroemberg et al., US 20200119510 A1, discloses the used of grooves to align solder sheets with groove protrusions prior to melting the solder.
Suzuki, US 20220285181 A1, discloses that a joining layer formed by laser irradiation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 7:30-4:30 ET, first Friday off.
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/LINDA J. FLECK/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812