DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 5, 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0046066).
Regarding claim 1, Park discloses a memory module comprising: a printed circuit board comprising a multi-layer (see Figure 3, module board 102), wherein a length of the PCB in a first direction (see Figure 2, horizontal) is longer than a length of the PCB in a second direction (vertical) perpendicular to the first direction: first memory chip (211 for example) mounted on the PCB; a second memory chip (221 for example) spaced apart from the first memory chip in the second direction; a third memory chip (212 for example) spaced apart from the first memory chip in the first direction; a fourth memory chip (222 for example) spaced apart from the second memory chip in the first direction; and a signal line (300 and wiring to chips) transmitting a command/address signal to each of the first to fourth memory chips, wherein the signal line comprises a first wiring formed inside the PCB (see Figure 3), the first wiring (vertical sections in Figure 7) connecting the first memory chip to the second memory chip, and connecting the third memory chip to the fourth memory chip; and a second wiring (diagonal section) formed inside the PCB, the second wiring connecting the second memory chip to the third memory chip.
Park discloses that the memory chips length in the first direction is shorter than the length of the memory chips in the second direction (i.e. the chips are rotated 90 degrees from the claimed orientation).
However, it would have been obvious to one having ordinary skill at the time of filing to rotate the chips in a layout since those of ordinary skill were aware at the time of filing the variables effected by such orientations and modification thereof represents a mere optimization of a result effective variable. For example, aligning the creation of wider routing channels between the rows of chips, fitting the chip counts into standard PCB form factors, heat distribution, etc.
Regarding claim 4, Park discloses the memory module of claim 1, wherein: the second memory chip is disposed on a same axis as an axis of the first memory chip in the second direction; and the fourth memory chip is disposed on a same axis as an axis of the third memory chip in the second direction (see Figure 2, array style).
Regarding claim 5, Park discloses the memory module of claim 4, wherein: the first wiring is in a shape of a straight line extending in the second direction: and the second wiring is in a shape of a straight line extending in a direction between the first direction and the second direction (see Figure 7).
Regarding claim 8, Park discloses the memory module of claim 1, wherein a length of the first wiring and a length of the second wiring are different from each other (See Figure 7).
Regarding claim 11, Park discloses the signal line is a command/address signal line (CA).
Claim(s) 7, 10, 12, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0046066) in view of Djordjevic (US 2008/0099238).
Regarding claims 12 and 10, Park discloses a memory module comprising: a printed circuit board comprising a multi-layer having a wiring structure formed therein, wherein a length of the PCB in a first direction is longer than a length of the PCB in a second direction perpendicular to the first direction; and a plurality of memory chips including a plurality of solder balls, the plurality of memory chips is arranged in a first row and a second row respectively extending in the first direction on the PCB (see rejection of claim 1 above), wherein the wiring structure alternately zigzag-connects the plurality of memory chips arranged in the first row and the second row inside the PCB (see Figure 7).
While Park shows solder ball arrangement, it does not show great detail and therefore fails to teach wherein the plurality of solder balls is arranged continuously in the first direction, and is partially discontinuously arranged in the second direction, wherein a number of the plurality of solder balls arranged in the first direction is greater than a number of the plurality of solder balls arranged in the second direction. However, inasmuch as understood (see 112 rejection above) this amounts to 1) the packages of park being mounted with long edge aligned with the long edge of PCB (obvious for the reasons in rejection of claim 1 above) and 2) an discontinuity among the solder ball arrangement along the short edge direction.
Regarding #2 it was known at the time of filing (see Djordjevic for example, Figure 3) with solder connections for memory elements arranged discontinuously along the short edge and continuously along the long edge). Therefore, it would have been obvious to one having ordinary skill at the time of filing to provide such an orientation since this was a known technique at the time of filing and yields the predictable result of signal connection in the memory device.
Regarding claim 16, Park discloses the memory module of claim 12, wherein the plurality of memory chips arranged in the second row is arranged in the second direction on a same axis as an axis of the plurality of memory chips arranged in the first row (see Park Figure 2).
Regarding claim 17 and 7, Park discloses the memory module of claim 12, but fails to teach wherein the plurality of memory chips arranged in the second row is arranged in the second direction on an axis different from an axis of the plurality of memory chips arranged in the first row.
However, it would have been obvious to one having ordinary skill at the time of filing since it was known to arrange memory chips in an offset fashion as shown by Djordjevic (see Figure 3) with the lower row offset from the upper row and since this was a known technique at the time of invention and yields the predictable result of optimizing layout and wiring.
Claim(s) 2, 3, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0046066) in view of Djordjevic (US 2006/0180917, herein ‘917) and Sugano (US 2008/123303).
Regarding claim 18, Park discloses a memory system comprising: a memory module comprising a printed circuit board wherein a length of the PCB in a first direction is longer than a length of the PCB in a second direction perpendicular to the first direction, and a plurality of memory chips arranged in a first row and a second row respectively extending in the first direction on the PCB, wherein a length of each memory module in the first direction is longer than a length of each memory module in the second direction (see rejection of claim 1 above); and a memory controller (110) transmitting a signal to the memory module, wherein the PCB comprises: a first wiring connecting the plurality of memory chips arranged in the first row and the second row (see Figure 2, portion between 224 and 215), the first wiring having a shape of a straight line extending in a third direction (vertical—see Figure 7); a second wiring (diagonal components) connecting the plurality of memory chips arranged in the first row and the second row, wherein the second wiring has a shape of a straight line extending in a fourth direction (diagonal) that is a direction different from the third direction.
Park fails to teach that different wiring components are formed on different layers with interconnect vias. However, this was a known technique at the time of filing (see Sugano Figure 4 for example showing different interchip connections on different wiring layers and/or ‘917 showing similar in Figures 5-6). Therefore, it would have been obvious to one having ordinary skill at the time of filing to provide the different wiring components on differing layers since this was a known technique at the time of filing and yields the predictable result of wiring optimization.
Regarding claim 19, Park discloses the memory system of claim18, wherein: the third direction is a same direction as the first direction (in view of the modification the chips are rotated); and the fourth direction is a direction between the first direction and the second direction (diagonal).
Regarding claim 2, Park discloses the memory module of claim 1, wherein the first wiring and the second wiring are disposed in different layers of the multi-layer from each other (See rejection of claim 18 above).
Regarding claim 3, Park discloses the memory module of claim2, further comprising: a landing pad disposed on the PCB and including an exposed surface, the landing pad electrically connecting each of the first to fourth memory chips to the PCB; a first via electrically connecting the landing pad to the first wiring; and a second via electrically connecting the first wiring to the second wiring (see Sugano Figure 4 in view of the modification)
Claim(s) 6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0046066) in view of Izadian (US 2010/0307798).
Regarding claims 6, Park discloses the memory module of claim 4, but fails the first wiring is in a shape of a straight line extending in a direction between the first direction and the second direction; and the second wiring is in a shape of a straight line extending in a direction between the first direction and the second direction and crossing an extending direction of the first wiring.
However, this represents an overlapping of angled wiring (i.e. a twisted pair of sorts). It was known at the time of filing that such an arrangement can minimize cross talk (see Izadian) and therefore, it would have been obvious to one having ordinary skill at the time of filing to provide the wirings crossing each other in a repeated manner in order to reduce cross talk.
Regarding claim 9, Park as modified above discloses the memory module of claim 1, wherein the first wiring has a same length as a length of the second wiring (in view of this modification, the “twisted pairs” have the same length).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0046066) in view of Djordjevic (US 2006/0180917, herein ‘917) and Sugano (US 2008/123303) .
Regarding claim 20, Park discloses the memory system of claim 18, but fails to teach the fourth direction is a direction between the first direction and the second direction that crosses the third direction, the third direction is a direction between the first direction and the second direction.
However, this represents an overlapping of angled wiring (i.e. a twisted pair of sorts). It was known at the time of filing that such an arrangement can minimize cross talk (see Izadian) and therefore, it would have been obvious to one having ordinary skill at the time of filing to provide the wirings crossing each other in a repeated manner in order to reduce cross talk.
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0046066) in view of Djordjevic (US 2008/0099238), Djordjevic (US 2006/0180917, herein ‘917), Izadian (US 2010/0307798) and Sugano (US 2008/123303).
Claims 13-15 represent a combination of all the features addressed in the various combinations above and it is thought to be clear the grounds of rejection.
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive. Applicant principally argues that 1) the examiner uses impermissible hindsight (see page 10); that 2) the cited art fails to establish chip orientation as a result effective variable (see page 11); and 3) that such a modification would significantly change the Park invention (see page 12).
With respect to argument 1, the Examiner disagrees. The prior art is rife with examples of chips of various orientations (see the cited Hwang, Yu, etc.). The question addressed by the modification in the rejection is would it have been obvious to one having ordinary skill to modify Park to have a different orientation of modules.
With respect to argument 2, the Examiner also disagrees. It is a fundamental practice of component layout that orientation with respect of airflow, proximity to neighboring thermal sources, etc. directly effects the cooling of the module at question. The examiner has concluded that a mere modification of the orientation of a module by 90 degrees is within the ordinary skill in the art and a reason for doing so would be to optimize for the use case of the module (e.g. for better cooling).
With respect to argument 3, any modification will inherently change the modified device but one of ordinary skill is capable of assessing the trade offs of the modification. Additionally, Applicant has merely pointed to the discussion of signal lengths and not explained why the proposed modification is incompatible with any constraints of the functioning device of Park.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824