Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-8, 11-12 and 22-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawabata, US 2018/0138131.
Regarding claim 1, Kawabata discloses (figs. 2, 6 and related text) an integrated circuit (11B) comprising: a substrate (20) having a first surface (upper surface of 20); a semiconductor die (31) having a second surface (bottom surface of 31) opposing the first surface; metal interconnects (24) between the second surface of the semiconductor die (31) and the first surface of substrate (20); an insulation layer (50) is between the second surface of the semiconductor die (31, bottom surface) and the first surface of the substrate (20, if one draws a line from the bottom surface of 31 to the top surface of the substrate 20, the line crosses the insulating layer 50, hence layer (50) is between the second surface of the semiconductor die (31, bottom surface) and the first surface of the substrate (20)), the insulation layer (50) surrounding each individual metal interconnect (24 underneath 32) of the metal interconnects (24, 50 surrounding 24 under 32, note the claim does not require the metal interconnects to be completely surrounded by the insulator layer); an inductor (32, [0069]) coupled to the substrate (fig. 2); and a magnetic material (40) encapsulating the semiconductor die (31), the inductor (32), the metal interconnects (24) and the insulation layer (50), the magnetic material (40) having a different material from the insulation layer (40 is magnetic mold resin [0067], and the insulation layer (50 is non-magnetic [0072]).
Regarding claim 5, Kawabata discloses (fig. 6 and related text) the magnetic material (40) includes metal particles (5, [0083]) and an epoxy resin (4) in which the metal particles are suspended (fig. 6).
Regarding claim 6, Kawabata discloses the insulation layer ([0072], common resin) has a higher breakdown voltage than the magnetic material (40, same material as the claimed invention, hence the same electrical property).
Regarding claim 7, Kawabata discloses the insulation layer ([0072]) includes a dielectric material [0072].
Regarding claim 8, Kawabata discloses the dielectric material ([0072]) includes a Polyimide material (resin).
Regarding claim 11, Kawabata discloses the insulation layer (50) is a first insulation layer, the metal interconnects (24) are first metal interconnects, and the substrate (20) includes: first metal pads (25) on a first side of the substrate (upper side of 20), the first metal pads (25) coupled to the first metal interconnects (24); second metal pads (26) on a second side of the substrate (bottom side of 20) opposite to the first side; a second insulation layer ([0069], substrate material) between the first side and the second side (fig. 2); and second metal interconnects (26) in the second insulation layer [0069] and coupled between the first metal pads (25) and the second metal pads (25).
Regarding claim 12, Kawabata discloses the first metal pads (25) and the second metal (26) interconnects include a Copper metal [0070]; the second metal pads include at least one of a Palladium metal or a Silver metal [0070]; and the second insulation layer includes a polymer material (thermoplastic resin, polymer material).
Regarding claim 22, Kawabata discloses the insulation layer (50) abuts the magnetic material (40, fig. 2).
Regarding claim 23, Kawabata discloses the insulation layer (50, common resin [0072]) has a higher break down voltage than the magnetic material (40, same material as the claimed invention, hence the same electrical property).
Regarding claim 24, Kawabata discloses (fig. 2 and related test) an integrated circuit (11B) comprising: a substrate (20) having a first surface (upper surface of 20); a semiconductor die (31) having a second surface (bottom surface of 31); metal interconnects (24) between the second surface of the semiconductor die (bottom surface of 31) and first surface of the substrate (upper surface 20), (a line can be drawn between bottom surface of 31 and 20 that passes through 24, then 24 is between 31 and 20); a layer of a first material (50) between the second surface of the semiconductor die (31) and the first surface of the substrate (20, a line drawn from the bottom surface of 31 to the top surface of the substrate 20 crosses the insulating layer 50, hence layer (50) is between the second surface of the semiconductor die (31, bottom surface) and the first surface of the substrate 20) and overlapping the semiconductor die (50 laterally overlaps 31, note the claim does not require the first material vertically overlaps the semiconductor die), the layer of the first material (50) surrounding the metal interconnects (24, underneath 32, note the claim does not require the metal interconnects to be completely surrounded by the first material); and a second material (40) different from the first material (50) covering at least parts of the semiconductor die (31), the metal interconnects (24), and the layer of the first material (50).
Regarding claim 25, Kawabata discloses the first material (50, ([0072], common resin) has a higher break down voltage than the second material (40, same material as the claimed invention, hence the same electrical property).
Regarding claim 26, Kawabata discloses the second material (40) includes a magnetic mold compound (40 is magnetic mold resin [0067]).
Regarding claim 27, Kawabata discloses the insulation layer (50) fills spaces between adjacent pairs of the metal interconnects (the space between 24 underneath 31 and 32 is filled with 50).
Regarding claim 28, Kawabata discloses the layer of the first material (50) fills spaces between adjacent pairs of the metal interconnects (the space between 24 underneath 31 and 32 is filled with 50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata in view of Herbert et al., US 2017/0053904.
Regarding claim 2, Kawabata discloses an inductor coil (32, [0069]). However, Kawabata does not explicitly disclose the inductor includes a stilt portion, the stilt portion coupled to the substrate.
Herbert discloses (fig. 11 and related text) the inductor including a stilt portion (1404), the stilt/support portion (1404) coupled to the substrate (fig. 11) to provide support and provide electrical connection [0045].
Kawabata and Herbert are analogous art because they both are directed to electronic circuit package devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata with the specified features of Herbert because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Kawabata to include the stilt/support as taught by Herbert in order to provide support and provide electrical connection [0045].
Regarding claim 3, Kawabata does not disclose the coil portion is on the semiconductor die.
Herbert discloses the coil (inductor 1402), portion is on the semiconductor die (102) in order to provide regulated power to other functional circuits [0061].
Kawabata and Herbert are analogous art because they both are directed to electronic circuit package devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata with the specified features of Herbert because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Kawabata to include the inductor coil on the semiconductor die as taught by Herbert in order to provide regulated power to other functional circuits [0061].
Regarding claim 4, Kawabata does not disclose a capacitor encapsulated in the magnetic material and coupled to the substrate; wherein the coil portion is on the capacitor.
Herbert discloses a capacitor (102, controller IC, controller ICs’ include capacitors) encapsulated in a suitable molding material (1406) material and coupled to the substrate; wherein the coil (1402) portion is on the capacitor (104) in order to provide regulated power to other functional circuits [0061].
Kawabata and Herbert are analogous art because they both are directed to electronic circuit package devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata with the specified features of Herbert because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Kawabata to include the capacitor as taught by Herbert in order to provide regulated power to other functional circuits [0061]. The combined structure discloses a capacitor encapsulated in the magnetic material and coupled to the substrate; wherein the coil portion is on the capacitor as claimed.
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata in view of Lin et al., US 2013/0032923.
Regarding claim 9, Kawabata does not explicitly the semiconductor die includes a passivation layer coupled to the metal interconnects.
Lin discloses (fig. 1A and related text) semiconductor die (100) includes a passivation layer (112) coupled to the metal interconnects (114) in order to provide an integrated inductor with a high Quality factor (Q) (abstract).
Kawabata and Lin are analogous art because they both are directed to electronic circuit package devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Kawabata to include the passivation layer as taught by Lin in order to provide an integrated inductor with a high Quality factor (Q) (abstract).
Regarding claim 10, Kawabata does not disclose the metal interconnects include at least one of: pillars, or under bump metallization (UBM) interconnects.
Lin discloses the metal interconnects include under bump metallization (UBM) interconnects (132) in order to provide an integrated inductor with a high Quality factor (Q) (abstract).
Kawabata and Lin are analogous art because they both are directed to electronic circuit package devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Kawabata to include the UBM as taught by Lin in order to provide an integrated inductor with a high Quality factor (Q) (abstract).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata in view Kang et al., US 2022/0172963.
Regarding claim 13, Kawabata does not disclose the integrated circuit of claim 11, further comprising a solder resist layer on the second side.
Kang discloses (fig. 1 and related text) an integrated circuit package (100) comprising a solder resist layer (116) on the second side (second side of 102) in order reduce conductive pattern peeling [0003].
Kawabata and Kang are analogous art because they both are directed to electronic circuit package devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata with the specified features of Kang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Kawabata to include solder resist layer as taught by Kang in order reduce conductive pattern peeling [0003].
Response to Arguments
Applicant's arguments filed 05/18/2026 have been fully considered but they are not persuasive. Applicant argues the non-magnetic member 50 of Kawabata does not surround each individual metal interconnect of the metal interconnect between the bottom surface of the electronic components 31 and the top surface of the substate 20 as recited in claim 1. Applicant further argues regarding claim 24, the non-magnetic member 50 is not between the bottom surface of electronic components 31 (which allegedly corresponds to the semiconductor die) and substrate 20, the non-magnetic member 50 does not surround solders 24 between the bottom surface of electronic components 31 and the top surface of substrate 20, and the non-magnetic member 50 does not overlap electronic components 31.
As clearly explained in the final rejection of claims 1 and 24 above, with regards to claim 1, Kawabata clearly discloses the insulation layer (50) surrounding each individual metal interconnect (there are at least 2 interconnects 24 underneath 32) of the metal interconnects (24, 50 surrounding 24 under 32). As stated above the claim does not require the metal interconnects to be completely surrounded by the insulator layer 50. Fig. 2, clearly shows two interconnects individually surrounded by 50.
Regarding claim 24, clearly Kawabata shows a line can be drawn between bottom surface of 31 and 20, the same line passes through 24, therefore 24 is clearly between 31 and 20. Furthermore a layer of a first material (50) between the second surface of the semiconductor die (31) and the first surface of the substrate (20). Using the same argument, a line drawn from the bottom surface of 31 to the top surface of the substrate 20 crosses the insulating layer 50, hence layer (50) is between the second surface of the semiconductor die (31, bottom surface) and (the first surface of the substrate 20) and overlapping the semiconductor die. Fig. 2, clearly shows 50 laterally overlapping 31. As stated above there is no requirement for the first material (50) to vertically overlaps the semiconductor die 31.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Prosecution Insights