DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/25/26 has been entered.
Note: capacitive-loading wing in an interconnect bridge refers to an extended or stub-like routing structure (a "wing") attached to a signal line or bus to add intentional parasitic capacitance, matching impedance, or stabilizing signal reflections.
Back-staggers in an interconnect bridge routing trace deviation refer to intentional zig-zag or offset patterns used to match trace lengths, reduce crosstalk, and manage high-speed signal skew across hardware interfaces.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 11, 22, 25, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2020/0395300) in view of Shen et al. (U.S. Patent 9,996,653).
As to claim 1, Xie discloses an interconnect bridge (110), as shown in figure 1 comprising:
an electrical routing trace (118, para 0023+) having a routing length in a major plane of the interconnect bridge (110) between a first interconnect (contacts 133 of dies 114-1) and a second interconnect (contacts 133 of dies 114-1); and
a routing trace deviation (a middle portion of element 118 formed between the conductive planes 119) conductively coupled with the electrical routing trace (118).
Xie does not specifically disclose the routing trace deviation has a first end and a second end, the first end is conductively coupled with the electrical routing trace, and the second end is surrounded by a dielectric material.
Shen teaches an apparatus for performing dual track routing as shown in figures 3-4 comprising a routing trace deviation (3041 or 3043) has a first end (the end connected to element 304) and a second end (the end extended to the trace), the first end is conductively coupled with the electrical routing trace, and the second end is surrounded by a dielectric material (the dielectric material of the PCB 300).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Shen employed in the interconnect bridge of Xie in order to provide high-speed signals and maximize cross-talk reduction.
Regarding claim 2, Xie as modified by Shen discloses the routing length (the length of element 118) extends in a first direction, and the routing trace deviation (the middle portion of element 118) extends away from the first direction.
Regarding claim 3, Xie as modified by Shen teaches the routing trace deviation (3041 or 3043) extends in a second direction, and the second direction is opposite the first direction.
Regarding claim 4, Xie as modified by Shen discloses at least half of the routing length (118) extends along the first direction.
Regarding claim 5, Xie as modified by Shen discloses the electrical routing trace (118) is a first electrical routing trace, and the routing length is a first routing length, and wherein the interconnect bridge (110) further includes:
a second electrical routing trace (top routing trace 118 above the element 119) having a second routing length;
wherein the second electrical trace (top 118) has a direct route between third and fourth interconnects (contacts 133 of die 114-2), and
wherein a routing time to transmit a first electrical signal (para-0015+) across the first electrical routing trace (118) and the routing trace deviation corresponds to a routing time to transmit a second electrical signal across the second electrical routing trace (top 118).
Regarding claim 11, Xie as modified by Shen teaches in figures 3-4 that the routing trace deviation (3041 or 3043) back-staggers the first electrical routing trace.
Regarding claim 22, Xie as modified by Shen discloses the routing trace deviation (the middle portion 118) is configured to alter one or more of a capacitance or a resistance of the electrical routing trace (118), para-0034+.
Regarding claim 25, Xie as modified by Shen teaches in figures 3-4 that the second end of the routing trace deviation (3041 or 3043) is electrically isolated within the interconnect bridge.
Regarding claim 26, Xie as modified by Shen teaches in figures 3-4 that the routing trace deviation (3041 or 3043) back-staggers the first electrical routing trace.
Regarding claim 32, Xie as modified by Shen teaches in figure 3 that the routing trace deviation (3041 or 3043) is outside a direct route between the first and second interconnects (3021-2).
As to claim 30, Xie discloses an electronic device (100) as shown in figure 1, comprising:
a first die (114-1) having a first electrical interconnect (133);
a second die (114-2) having a second electrical interconnect (133); and
an interconnect bridge (110), comprising:
an electrical routing trace (118) having a routing length in a plane of the interconnect bridge (110) between the first and second electrical interconnects (133), and
a routing trace deviation (the middle portion of the element 118) conductively coupled with the electrical routing trace.
Xie does not specifically disclose the routing trace deviation back-staggers the electrical routing trace.
Shen teaches in figures 3-4 that the routing trace deviation (3041 or 3043) back-staggers the first electrical routing trace.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Shen employed in the interconnect bridge of Xie in order to match trace lengths, reduce crosstalk, and manage high-speed signal skew across hardware interfaces.
Regarding claim 31, Xie as modified by Shen teaches in figure 3 that the routing trace deviation (3041 or 3043) is outside a direct route between the first and second interconnects (3021-2).
Allowable Subject Matter
Claims 8-10, 23 are objected to as being dependent upon a rejected base
claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
Claims 12, 14, and 27-29 are allowed.
The following is an examiner's statement of reasons for allowance:
Neither the references cites nor the cites references teach, suggest, or in
combination of an electronic device having a routing trace deviation conductively
coupled in with the electrical routing trace, wherein the routing trace deviation is a
capacitive-loading wing (claim 12).
Any comments considered necessary by applicant must be submitted no later
than the payment of the issue fee and, to avoid processing delays, should preferably
accompany the issue fee. Such submissions should be clearly labeled "Comments on
Statement of Reasons for Allowance."
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 8-12, 14, 22-23, 25-32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T DINH/Primary Examiner, Art Unit 2847
Prosecution Insights