Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 01/09/2026 has been entered. Claim 1, 22, 24, 25 are amended. Claims 5, 8 – 20, 23 are canceled. Claims 1 – 4, 6 – 7, 21 – 22, 24 – 26 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 6 – 7, 21, 24 – 26 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn ( Pub. No. US 20200365617 A1 ), hereinafter Ahn, in view of Lee ( US 20200144285 A1 ), hereinafter Lee.
PNG
media_image1.png
1446
1431
media_image1.png
Greyscale
Regarding Independent Claim 1 ( Currently amended ), Ahn teaches a semiconductor memory device, comprising:
a lower structure ( Ahn, FIG. 2A, the structure below LV1, and above 102 ) including a cell region ( Ahn, FIG. 2A, MEC; [0022], memory cell region MEC ) and a contact region ( Ahn, FIG. 2A, CON, PERI; [0022], connection region CON; [0021], peripheral circuit region PERI );
a first stacked structure ( Ahn, FIG. 2A, STA; [002], lower memory stack STA ) including a first portion ( Ahn, FIG. 2A, STA over MEC ) over the cell region (Ahn, FIG. 2A, MEC) of the lower structure ( Ahn, FIG. 2A, 102 ) and a second portion ( Ahn, FIG. 2A, STA over CON and PERI ) over the contact region ( Ahn, FIG. 2A, CON, PERI ) of the lower structure ( Ahn, FIG. 2A, 102 );
a second stacked structure ( Ahn, FIG. 2A, STB; [002], upper memory stack STB ) stacked
an interlayer insulating layer ( Ahn, FIG. 2A, 187A, 187B; [0037], lower intermediate insulating film 187A, upper intermediate insulating film 187B ) over the second portion ( Ahn, FIG. 2A, STA over CON and PERI ) of the first stacked structure ( Ahn, FIG. 2A, STA ),
wherein the first portion ( Ahn, FIG. 2A, STA over MEC ) of the first stacked structure ( Ahn, FIG. 2A, STA; [002], lower memory stack STA ) includes at least one lower cell plug pattern ( Ahn, FIG. 2A, 180A; [0036], lower channel structure 180A ) and a lower slit pattern ( Ahn, FIG. 2B, WCA; [0030], lower word line cut structure WCA ) extending in a vertical direction,
wherein the second portion ( Ahn, FIG. 2A, STA over CON and PERI ) of the first stacked structure ( Ahn, FIG. 2A, STA) includes first material layers and second material layers alternately disposed over a surface of the interlayer insulating layer facinq away from the lower structure, and a first conductive layer (Ahn, FIG. 2A, 116, P116; [0052], lower contact plugs 116; [0062], lower peripheral contact plugs P116 ) extending,
wherein the interlayer insulating layer ( Ahn, FIG. 2A, 187A, 187B ) includes a second conductive layer (Ahn, FIG. 2A, 126, P126; [0055], upper contact plugs 126; [0063], upper peripheral contact plugs P126) extending in the vertical direction and contacting the first conductive layer (Ahn, FIG. 2A, 116, P116),
wherein the second stacked structure includes at least one upper cell plug pattern ( Ahn, FIG. 2A, 180B; [0036], upper channel structure 180B ) extending in the vertical direction and directly contacting an upper surface of the at least one lower cell plug pattern ( Ahn, FIG. 2A, 180A; [0036], lower channel structure 180A ) and an upper slit pattern ( Ahn, FIG. 2B, WCB; [0030], upper word line cut structure WCB ) extending in the vertical direction and directly contacting an upper surface of the lower slit pattern ( Ahn, FIG. 2B, WCA; [0030], lower word line cut structure WCA ), and
wherein a lower surface of the at least one upper cell plug pattern ( Ahn, FIG. 2A, 180B; [0036], upper channel structure 180B ) contacting the upper surface of the at least one lower cell plug pattern ( Ahn, FIG. 2A, 180A; [0036], lower channel structure 180A ) has a lower critical dimension than the upper surface of the at least one lower cell plug pattern ( Ahn, FIG. 2A, 180A; [0036], lower channel structure 180A ) ( Ahn, [0037], A lower surface of the upper channel structure 180B may contact an upper surface of the lower channel structure 180A. In the horizontal direction (X direction and/or Y direction), the width of the lower surface of the upper channel structure 180B may be smaller than the width of the upper surface of the lower channel structure 180A ).
Ahn does not explicitly disclose:
a first conductive layer extending through the first material layers and the second materials layers.
However, Lee teaches:
a first conductive layer ( Lee, FIG. 1, 182; [0023], common source line 182 ) extending through ( Lee, [0039], The stacked structure 172 may include insulation layers 120 and the gate electrodes 170 alternately and repeatedly stacked; [0063], The common source lines 182 may pass through the stacked structure 172 ) the first material layers ( Lee, FIG. 1, 120; [0039], insulation layers 120 ) and the second materials layers ( Lee, FGI. 1, 170; [0035], gate electrodes 170 ).
Ahn and Lee are both considered to be analogous to the claimed invention because they are forming semiconductor memory devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahn ( lower contact plugs 116, lower peripheral contact plugs P116 ), to incorporate the teachings of Lee ( common source lines 182 may pass through the stacked structure 172, stacked structure 172 may include insulation layers 120 and the gate electrodes 170 ), to implement that a first conductive layer extending through the first material layers and the second materials layers. Doing so would provide the vertical conductive contact via, passing through first material layers and second material layers, and therefore the shorter connection path and lower resistance, and also the support structure for semiconductor memory devices can be implemented.
Regarding Claim 2 ( Previously presented ), Ahn and Lee teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Ahn further teaches:
wherein the first portion ( Ahn, FIG. 2A, STA over MEC ) of the first stacked structure ( Ahn, FIG. 2A, STA; [002], lower memory stack STA ) and the second stacked structure ( Ahn, FIG. 2A, STB; [002], upper memory stack STB ) further include a dummy cell plug ( Ahn, [0048], dummy channel structures ) extending in the vertical direction.
Regarding Claim 3 ( Original ), Ahn and Lee teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Ahn further teaches:
wherein the dummy cell plug ( Ahn, [0048], dummy channel structures ) comprises:
a lower dummy plug pattern included in the first stacked structure ( Ahn, [0048], dummy channel structures (not shown) may be located on the stepped lower connection portion 110 ); and
an upper dummy plug pattern included in the second stacked structure ( Ahn, [0048], dummy channel structures (not shown) may be located on … the stepped upper connection portion 120 ), the upper dummy plug pattern contacting the lower dummy plug pattern ( Ahn, [0048], dummy channel structures (not shown) may be located on the stepped lower connection portion 110 ) ( Ahn, [0048], In some example embodiments, on the connection region CON, a plurality of dummy channel structures (not shown) may be located on the stepped lower connection portion 110 and the stepped upper connection portion 120. The dummy channel structures may support the edge portions of the lower word lines WLA and the upper word lines WLB, and the lower pad regions 112 and the upper pad regions 122 to prevent or reduce the likelihood of the occurrence of undesirable structural deformation such as bending and/or breakage ).
Regarding Claim 4 ( Original ), Ahn and Lee teach the semiconductor memory device as claimed in claim 3, on which this claim is dependent, Ahn further teaches:
wherein the lower surface of the upper dummy plug pattern ( Ahn, [0048], dummy channel structures (not shown) may be located on … the stepped upper connection portion 120 ) contacting the lower dummy plug pattern ( Ahn, [0048], dummy channel structures (not shown) may be located on the stepped lower connection portion 110 ) has a lower critical dimension than the upper surface of the lower dummy plug pattern ( Ahn, [0037], A lower surface of the upper channel structure 180B may contact an upper surface of the lower channel structure 180A. In the horizontal direction (X direction and/or Y direction), the width of the lower surface of the upper channel structure 180B may be smaller than the width of the upper surface of the lower channel structure 180A ).
Regarding Claim 6 ( Previously presented ), Ahn and Lee teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Ahn further teaches:
wherein the first conductive layer ( Ahn, FIG. 2A, 116, P116 ) and the second conductive layer ( Ahn, FIG. 2A, 126, P126 ) form a contact plug (Ahn, FIG. 2A, 116, 126, P116, P126; [0052], lower contact plugs 116; [0055], upper contact plugs 126; [0062], lower peripheral contact plugs P116; [0063], upper peripheral contact plugs P126).
Regarding Claim 7 ( Previously presented ), Ahn and Lee teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Ahn further teaches:
wherein a lower surface of the second conductive layer (Ahn, FIG. 2A, P126; [0063], upper peripheral contact plugs P126) contacting the upper surface of the first conductive layer (Ahn, FIG. 2A, P116; [0062], lower peripheral contact plugs P116) has a lower critical dimension than the upper surface of the first conductive layer (Ahn, FIG. 2A, P116; [0062], lower peripheral contact plugs P116) ( Ahn, [0037], A lower surface of the upper channel structure 180B may contact an upper surface of the lower channel structure 180A. In the horizontal direction (X direction and/or Y direction), the width of the lower surface of the upper channel structure 180B may be smaller than the width of the upper surface of the lower channel structure 180A ).
Regarding Claim 21 ( Previously presented ), Ahn and Lee teach s the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Ahn further teaches:
wherein a lower surface of the upper slit pattern ( Ahn, FIG. 2B, WCB; [0030], upper word line cut structure WCB ) contacting the upper surface of the lower slit pattern ( Ahn, FIG. 2B, WCA; [0030], lower word line cut structure WCA ) has a lower critical dimension than the upper surface of the lower slit pattern (Ahn, FIG. 2B, WCA, WCB; [0030], In the second horizontal direction (Y direction), the width of the lower surface of the upper word line cut structure WCB may be smaller than the width of the upper surface of the lower word line cut structure WCA).
Regarding Claim 24 ( Currently amended ), Ahn and Lee teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Ahn further teaches:
further comprising a support structure (Ahn, [0048], dummy channel structures) passing through the interlayer insulating layer ( Ahn, FIG. 2A, 187A, 187B; [0037], lower intermediate insulating film 187A, upper intermediate insulating film 187B ) and the second portion ( Ahn, FIG. 2A, STA over CON and PERI ) of the first stacked structure ( Ahn, FIG. 2A, STA ) ( Ahn, [0048], In some example embodiments, on the connection region CON, a plurality of dummy channel structures (not shown) may be located on the stepped lower connection portion 110 and the stepped upper connection portion 120. The dummy channel structures may support the edge portions of the lower word lines WLA and the upper word lines WLB, and the lower pad regions 112 and the upper pad regions 122 to prevent or reduce the likelihood of the occurrence of undesirable structural deformation such as bending and/or breakage ).
Regarding Claim 25 ( Previously presented ), Ahn and Lee teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Ahn further teaches: wherein the lower structure ( Ahn, FIG. 2A, the structure below LV1, and above 102 ) comprises:
a first connection structure ( Ahn, FIG. 2A, 110, 112; [0024], The lower pad regions 112 are located on the connection region CON and constitute, or are included in, a stepped lower connection portion 110 ) disposed over a substrate ( Ahn, FIG. 2A, 102; [0022], substrate 102 ), the first connection structure ( Ahn, FIG. 2A, 110, 112; [0024], The lower pad regions 112 are located on the connection region CON and constitute, or are included in, a stepped lower connection portion 110 ) including a first connection conductor ( Ahn, FIG. 2A, 112; [0024], lower pad regions 112 );
a complementary metal oxide semiconductor (CMOS) circuit ( Ahn, FIG. 2A, TR; [0061], peripheral transistor TR ) disposed between the substrate ( Ahn, FIG. 2A, 102; [0022], substrate 102 ) and the first connection structure ( Ahn, FIG. 2A, 110, 112; [0024], The lower pad regions 112 are located on the connection region CON and constitute, or are included in, a stepped lower connection portion 110 ), the transistor ( Ahn, FIG. 2A, TR; [0061], peripheral transistor TR ) being connected to the first connection conductor ( Ahn, FIG. 2A, 112; [0024], lower pad regions 112 ) ( Ahn, FIG. 2A, TR; [0061], The peripheral transistor TR may be electrically connected to the memory cell region MEC through an interconnection structure located on the connection region CON );
a first bonding structure ( Ahn, FIG. 2A, MA, PMA, 116, P116; [0053], A plurality of lower interconnection layers MA may be formed on the lower contact plugs 116; [0062], lower peripheral interconnection layers PMA; lower peripheral contact plugs P116 ) including a first bonding pad ( Ahn, FIG. 2A, 116; [0053], lower contact plugs 116 ) connected to the first connection conductor ( Ahn, FIG. 2A, 112; [0024], lower pad regions 112 ), the first bonding structure ( Ahn, FIG. 2A, MA, 116; [0053], A plurality of lower interconnection layers MA may be formed on the lower contact plugs 116 ) being disposed on the first connection structure ( Ahn, FIG. 2A, 110, 112; [0024], The lower pad regions 112 are located on the connection region CON and constitute, or are included in, a stepped lower connection portion 110 );
a second bonding structure ( Ahn, FIG. 2A, MB, PMB, 126, P126; [0056], On the connection region CON, the upper interconnection layers MB may be formed on the upper contact plugs 126; [0064], upper peripheral interconnection layers PMB; [0063], upper peripheral contact plugs P126 ) including a second bonding pad ( Ahn, FIG. 2A, PMB, P126; [0064], upper peripheral interconnection layers PMB; [0063], upper peripheral contact plugs P126 ) connected to the first bonding pad ( Ahn, FIG. 2A, PMA, P116; [0062], lower peripheral interconnection layers PMA; lower peripheral contact plugs P116 ), the second bonding structure ( Ahn, FIG. 2A, MB, PMB, 126, P126; [0056], On the connection region CON, the upper interconnection layers MB may be formed on the upper contact plugs 126; [0064], upper peripheral interconnection layers PMB; [0063], upper peripheral contact plugs P126 ) being disposed on the first bonding structure ( Ahn, FIG. 2A, MA, PMA, 116, P116; [0053], A plurality of lower interconnection layers MA may be formed on the lower contact plugs 116; [0062], lower peripheral interconnection layers PMA; lower peripheral contact plugs P116 );
a second connection structure ( Ahn, FIG. 2A, 120, 122; [0025], stepped upper connection portion 120; upper pad regions 122 ) including a second connection conductor ( Ahn, FIG. 2A, 122; [0025], upper pad regions 122 ) connected to the second bonding pad ( Ahn, FIG. 2A, MB, 126; [0056], On the connection region CON, the upper interconnection layers MB may be formed on the upper contact plugs 126 ), the second connection structure ( Ahn, FIG. 2A, 122; [0025], upper pad regions 122 ) being disposed on the second bonding structure ( Ahn, FIG. 2A, MB, PMB, 126, P126; [0056], On the connection region CON, the upper interconnection layers MB may be formed on the upper contact plugs 126; [0064], upper peripheral interconnection layers PMB; [0063], upper peripheral contact plugs P126 ).
Regarding Claim 26 ( Previously presented ), Ahn and Lee teach the semiconductor memory device as claimed in claim 25, on which this claim is dependent, Ahn further teaches:
second connection conductor ( Ahn, FIG. 2A, 122, 126; [0025], upper pad regions 122; [0055], upper contact plugs 126 ) is coupled to an end of the at least one lower cell plug pattern ( Ahn, FIG. 2A, 112, 116; [0024], lower pad regions 112; [0052], lower contact plugs 116 ) ( Ahn, [0055], None of the upper contact plugs 126 passing through the upper insulating film 124 may be connected to one of the lower interconnection layers MA extending at the first vertical level LV1 ).
Allowable Subject Matter
Claim 22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s argument for claim 1: page 9, line 14, cited “ However, as shown in FIG. 2A of Ahn, neither the upper contact plug 126 nor the upper peripheral contact plug P126 extends through the insulating films 156B and the upper word lines WLB. As argued above, Ahn fails to disclose the first conductive layer extending through the first material layers and the second materials layers alternately disposed over the surface of the interlayer insulating layer facing away from the lower structure. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ However, Lee teaches:
a first conductive layer ( Lee, FIG. 1, 182; [0023], common source line 182 ) extending through ( Lee, [0039], The stacked structure 172 may include insulation layers 120 and the gate electrodes 170 alternately and repeatedly stacked; [0063], The common source lines 182 may pass through the stacked structure 172 ) the first material layers ( Lee, FIG. 1, 120; [0039], insulation layers 120 ) and the second materials layers ( Lee, FGI. 1, 170; [0035], gate electrodes 170 ).
Ahn and Lee are both considered to be analogous to the claimed invention because they are forming semiconductor memory devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ahn ( lower contact plugs 116, lower peripheral contact plugs P116 ), to incorporate the teachings of Lee ( common source lines 182 may pass through the stacked structure 172, stacked structure 172 may include insulation layers 120 and the gate electrodes 170 ), to implement that a first conductive layer extending through the first material layers and the second materials layers. Doing so would provide the vertical conductive contact via, passing through first material layers and second material layers, and therefore the shorter connection path and lower resistance, and also the support structure for semiconductor memory devices can be implemented. ”. Therefore, Ahn and Lee disclose the first conductive layer extending through the first material layers and the second materials layers alternately disposed over the surface of the interlayer insulating layer facing away from the lower structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights