Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to the applicants’ arguments dated 04/21/2026, the amendment to independent claim 21 overcomes the previous prior art rejection. However, a new rejection is formulated below with a new reference, Hwang et al (US 20200335480) as a secondary reference.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 by being unpatentable over Su et al (US 20120061853 A1) in view of Hwang et al (US 20200335480).
Su et al teaches
[claim 21] A semiconductor package, comprising: a substrate; a first semiconductor chip on the substrate, the first semiconductor chip having a first sidewall and a second sidewall different from the first sidewall (figure 4, paragraph 0036, where element 100 is the semiconductor package, element 125 is the substrate, and element 110 is the first semiconductor chip on the substrate),
a second semiconductor chip on the substrate and laterally spaced apart from the first semiconductor chip (figure 4, paragraph 0036, element 115 ist he second semiconductor chip and is laterally spaced apart from the first semiconductor chip [element 110] and on the substrate [element 125]);
and a molding layer on the substrate, the molding layer being between the first sidewall of the first semiconductor chip and a sidewall of the second semiconductor chip (figure 4, paragraph 0040, element 155 and 180 is the molding layer, and is situated between the first sidewall of the first semiconductor chip [right hand side of element 110] and the sidewall of the second semiconductor chip [left-hand side of element 115]),
wherein the molding layer exposes the second sidewall of the first semiconductor chip, wherein, between the first semiconductor chip and the second semiconductor chip, a bottom surface of the molding layer is vertically spaced apart from an upper surface of the substrate (figure 4, paragraph 0040, where elements 155 and 180 [molding layer] fills in between the semiconductor chips [elements 110 and 115] and exposes a second sidewall of the first semiconductor chip [left-hand side of element 110 is exposed], and is situated vertically away from the substrate [element 125]).
However, Su et al does not specifically disclose
[claim 21] [wherein the molding layer] completely [exposes the second sidewall of the first semiconductor chip]
However, Hwang et al does teach
[claim 21] [wherein the molding layer] completely [exposes the second sidewall of the first semiconductor chip] (figure 2, paragraph 0049, where element 400 is the first semiconductor chip, and the left-hand side is the second sidewall, where the second sidewall is completely exposed to the air as designated by element AG – air gap).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Su et al to incorporate the teachings of Hwang et al to minimize heat transfer from one chip to another chip allowing greater performance of the chips (paragraph 0049).
Claim(s) 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 20120061853 A1), and Hwang et al (US 20200335480) in further view of Huang et al (US 10867951 B2).
Regarding claim 22, Su et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 22] bumps between the substrate and the first semiconductor chip; and an under-fill layer between the substrate and the first semiconductor chip, the underfill layer covering sidewalls of the bumps, wherein the second sidewall of the first semiconductor chip is vertically aligned with an outer sidewall of the underfill-layer.
However, Huang et al does teach a semiconductor package, further comprising: bumps between the substrate and the first semiconductor chip (figure 5b, element 64, where the first semiconductor chip is element 60);
and an under-fill layer between the substrate and the first semiconductor chip, the underfill layer covering sidewalls of the bumps (figure 5b, element 72),
wherein the second sidewall of the first semiconductor chip is vertically aligned with an outer sidewall of the under-fill layer (figure 5b, element 60E is the sidewall and is vertically aligned with element 72 [underfill layer]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaches of Su et al as modified to include the teachings of Huang in order to maximize conductivity between the semiconductor die and the any other circuit attached to the substrate in order to have a functioning semiconductor die.
Regarding claim 23, Su et al further teaches
The semiconductor package wherein the under-fill layer fills a gap between the bottom surface of the molding layer and the upper surface of the substrate (paragraph 0040, figure 4, where element 145 is the under-fill layer and fills the gap between the molding layer [elements 155 and 180] and the stop of the substrate [element 125]).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 20120061853 A1), Hwang et al (US 20200335480) and in further view of Chen et al (US 11694975 B2).
Regarding claim 24, Su et al as modified teaches the semiconductor package of claim 1, wherein the molding layer includes: a first part between the first semiconductor chip and the second semiconductor chip (figure 4, element 155 and 180 is situated between the first and second semiconductor chips [elements 110 and 115 respectively]).
Su et al as modifieddoes not specifically disclose
a second part on an upper surface at an edge region of the substrate, wherein, when viewed in plan, the edge region of the substrate is between the second sidewall of the first semiconductor chip and a sidewall of the substrate, and wherein a top surface of the second part of the molding layer is at a level lower than a level of a top surface of the first part of the molding layer.
However, Chen et al does teach a second part on a top surface at an edge region of the substrate, wherein, when viewed in plan, the edge region of the substrate is between the second sidewall of the first semiconductor chip and a sidewall of the substrate (Figures 1A and 1B, edge part is between the outside sidewall of element 134 and the outside sidewall of element 110),
and wherein an upper surface of the second part of the molding layer is at a level lower than a level of a top surface of the first part of the molding layer (element 150 is the second part, element 135 is the first part where the top surface of element 150 is lower than the top surface of element 135).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaches of Su et al as modified to incorporate the teachings of Chen in order to create a more stable package material by leveling the molding layer with the semiconductor die.
Claim(s) 25 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 20120061853 A1), and Hwang et al (US 20200335480) in further view of Park et al (US 20150048519 A1).
Regarding claims 25, Su et al as modified teaches all of the limitations of the parent claim, claim 21, and further teaches the upper semiconductor chip having a first lateral surface and a second lateral surface different from the first lateral surface, wherein the molding layer is on the first lateral surface of the upper semiconductor chip, and wherein the molding layer is not on the second lateral surface of the upper semiconductor chip (figure 4, element 155 and 180 [molding layer] is on the first lateral side of element 110 [furthest to the right] but not on the other lateral side of said element [labeled second lateral surface]).
Su et al as modified does not specifically disclose a semiconductor package further comprising an upper semiconductor chip on the first semiconductor chip.
However, Park does teach a semiconductor package further comprising an upper semiconductor chip on the first semiconductor chip (figure 6, element 5001 [upper semiconductor chip] on a lower semiconductor chip [element 4000]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Su et al to incorporate the teachings of Park by layering the semiconductor dies such that the top layer does have a semiconductor die with one exposed side and one covered side by the molding layer in order to increase efficiency of the entire semiconductor system by incorporating more die into a smaller area thus increasing efficiency of packaging.
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Su et al as modified to incorporate the teachings of Park to create a larger molding layer than the substrate to maximize structural stability for stacked die on the substrate in order to stack more die and increase the density of stacked die in a semiconductor package.
Claim(s) 26 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 20120061853 A1), Hwang et al (US 20200335480) and Park et al (US 20150048519 A1) in further view of Huang et al (US 10867951 B2).
Su et al as modified teaches all of the limitations of the parent claim, claim 25, but does not specifically disclose
[claim 26] wherein the upper semiconductor chip is provided in plural, an upper surface of the molding layer and an upper surface of an uppermost upper semiconductor chip among the upper semiconductor chips are at same vertical level.
However, Huang et al does teach
[claim 26] wherein the upper semiconductor chip is provided in plural, an upper surface of the molding layer and an upper surface of an uppermost upper semiconductor chip among the upper semiconductor chips are at same vertical level (figure 5B, col 7 lines 22-58, where element 62 is the molding layer around a plurality of upper semiconductor chips [element 60] where the modling layer is the same height as the plurality of upper semiconductor chips]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Su et al as modified to incorporate the teachings of Huang et al in order to support a plurality of structures by having the molding layer go to the top level of the upper semiconductor chip to provide structural stability and maximize performance of the package.
Claim(s) 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 20120061853 A1), Hwang et al (US 20200335480), and Park et al (US 20150048519 A1) in further view of Hong et al (US 20140117506 A1) and Gang (US 20210066368 A1)
Su et al as modified teaches the limitations of the parent claim, claim 25, but does not specifically disclose:
[claim 27] the semiconductor package of claim 25, further comprising a molding pattern on a top surface of the first semiconductor chip, the molding pattern covering the first lateral surface of the upper semiconductor chip, wherein the molding pattern is between the molding layer and the first lateral surface of the upper semiconductor chip.
[claim 28] the semiconductor package of claim 27, wherein the molding pattern exposes the second lateral surface of the upper semiconductor chip.
However, Hong does teach
[claim 27] a semiconductor package, further comprising a molding pattern on a top surface of the first semiconductor chip (figure 1A, element 250 [molding pattern] on top side of first semiconductor die [element 120]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaches of Su et al as modified to incorporate the teachings of Hong to have placed a molding layer the top side of the first semiconductor chip in order to create a more stable semiconductor package structure.
Su et al as further modified by Hong above does not specifically disclose:
[claim 27] the molding pattern covering the first lateral surface of the upper semiconductor chip, wherein the molding pattern is between the molding layer and the first lateral surface of the upper semiconductor chip
[claim 28] the semiconductor package of claim 6, wherein the molding pattern exposes the second lateral surface of the upper semiconductor chip.
However Gang does teach
[claim 27] the molding pattern covering the first lateral surface of the upper semiconductor chip, wherein the molding pattern is between the molding layer and the first lateral surface of the upper semiconductor chip (column 1 lines 38-48),
[claim 28] a semiconductor package wherein the molding pattern exposes the second lateral surface of the upper semiconductor chip (column 1 lines 38-48).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teaches of Su et al as modified to incorporate the teachings of Gang to have placed a molding layer on the lateral sides of the semiconductor chip as well as the top side of the first semiconductor chip in order to create a more stable semiconductor package structure.
Allowable Subject Matter
Claims 29-40 are allowed. Specifically, the limitations of independent claims 29 and 37 are all present in already allowable claims 11 and 16 from the office action dated 07/28/2025. Thus, claims 29 and 37 overcome the previous prior art. Additionally, dependent claims 30-36 and 38-40 further limit independent claims 29 and 37 and the combination thereof, thus are also in a state of allowance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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