DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 11/24/2025, has been entered. The Applicant has amended claims 1-3, 9, 12, 14, and 20, and canceled claim 13. Accordingly, claims 1-12 and 14-20 remain pending in the application.
Applicant' s amendment to claim 12 has also overcome the 25. U.S.C. 112(b) rejections made on claim 12 in the Non-Final Office Action mailed on 8/22/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 2016/0307887 A1) in view of Yoon (US 2022/0208790 A1).
Regarding claim 1, Song teaches a semiconductor structure (semiconductor device 100, Figs. 1 and 2A, [0025]) comprising:
a logic device region (transistor area TA, Figs. 1 and 2A, [0026]: transistor area includes a transistor, which is a common logic device) located in a first portion (the portion of the substrate 101 occupied by the transistor area TA, Fig. 2A, [0026] and [0008]: “…fabricating a semiconductor device may include providing a substrate including a transistor area and a resistor area, …”) of a semiconductor substrate (substrate 101, Fig. 2A, [0027]: “The substrate 101 may include a bulk single crystalline silicon substrate or a silicon-on-insulator (SOI) substrate“), the logic device region (transistor area TA, Figs. 1 and 2A) comprising a first gate structure (active gate structure 110R, Fig. 2A, [0028]); and
a resistor device region (resistor area RA, Figs. 1 and 2A, [0046]) located in a second portion (portion of the substrate 101 occupied by the transistor area TA, Fig. 2A, [0026] and [0008]: “…fabricating a semiconductor device may include providing a substrate including a transistor area and a resistor area, …”) of the semiconductor substrate (substrate 101, Fig. 2A), the resistor device region (resistor area RA, Figs. 1 and 2A) is entirely absent of any source/drain region (Fig. 2A, [0047]:” The source/drain area is not formed in the substrate 101 between the dummy gate structures 110D.”) and comprises a second gate structure (dummy gate structures 110D, Fig. 2A, [0047]), and a first metal resistor (resistor element 152, Fig. 2A, [0053] and claim 4: “the resistor element comprises a metal.”) located above the second gate structure (dummy gate structures 110D, Fig. 2A), wherein the second gate structure (dummy gate structures 110D, Fig. 2A) is a component of a non-functional device ([0047]: “The dummy gate structures 110D do not form the transistors and are not used to operate the transistors.”)
Song, however, does not teach that the transistor device in the semiconductor device is a nanosheet field-effect transistor, and therefore does not teach that
the logic device region comprises the first gate structure wrapped around a
first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the semiconductor substrate; and
the resistor device region comprises the second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the resistor device region, and a bottom dielectric isolation layer separating the second gate structure from the second portion of the semiconductor substrate.
Yoon, on the other hand, teaches an integrated circuit device (Fig. 14B, Abstract and [0048]) comprising a region (first region R1, see Illustrative Fig. 1 which is an annotated version of Yoon’s Fig. 14B, [0047]; [0111]: first region R1 may be a logic region) which includes a nanosheet field effect transistor (nanosheet transistors including stacked nanosheets N1, N2, N3; Illustrative Fig. 1, [0031]),
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wherein the nanosheet field effect transistor (nanosheet transistors, Illustrative Fig. 1) comprises a gate structure (gate structures comprising gate electrode 150, gate spaces GS, and gate spacer 130, Illustrative Fig. 1, [0048]) wrapped around a vertical nanosheet stack (stacked structure NSS, Illustrative Fig. 2, [0072]), a source/drain region (source/drain regions 160A, Illustrative Fig. 1, [0043]) extending from sidewalls of each of the semiconductor channel material nanosheets (nanosheets N1, N2, N3; Illustrative Fig. 1: source/drain regions 160A cover the sidewalls of the nanosheets N1, N2, N3) of the first vertical nanosheet stack (stacked structure NSS, Illustrative Fig. 1), and a bottom dielectric isolation layer (insulating substrate layer 102, Illustrative Fig. 1, [0016]: insulating substrate layer 102 may include silicon dioxide which is a dielectric) separating the gate structure (comprising gate electrode 150, gate spaces GS, and gate spacer 130, Illustrative Fig. 1, [0048]) and the source/drain region (source/drain regions 160A, Illustrative Fig. 2, [0043]) from the semiconductor substrate (impurity region 104, Illustrative Fig. 1, [0025]).
Yoon further discloses that the design of the nanosheet transistors including the insulating substrate layer 102 on the base substrate layer (impurity region 104, Illustrative Fig. 1) improves the performance of the transistor by reducing the leakage currents ([0083]). A person of ordinary skill in the art before the effective filing date of the claimed invention would also be familiar with the fact that gate-all-around nanosheet field-effect transistors, such as the one disclosed by Yoon, provides scaling and current control advantages over FinFETs and other transistors, as evidenced by Kumari (page 2, paragraph 3, Kumari and Prithvi (2022), Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters, Microelectronics Journal, Volume 125, 2022, 105432, ISSN 1879-2391, https://doi.org/10.1016/j.mejo.2022.105432). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the transistor in the transistor region TA of Song with the gate-all-around nanosheet transistor of Yoon and the dummy transistor structure in the resistor area RA of Song with the gate-all-around nanosheet transistor of Yoon but without the source/drain regions (as taught by Song) to obtain a semiconductor structure with an improved device performance and scaling.
Accordingly, the combination of Song and Yoon leads to a semiconductor structure (see Illustrative Fig. 2 for the device structure of Song modified by Yoon: the transistors in the transistor region TA of Song are replaced by the nanosheet transistors of Yoon, and the dummy transistors in the resistor region RA are replaced nanosheet transistors of Yoon but without the source/drain regions), wherein
the logic device region comprises the first gate structure wrapped around a first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the semiconductor substrate; and
the resistor device region comprises the second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the resistor device region, and a bottom dielectric isolation layer separating the second gate structure from the second portion of the semiconductor substrate.
Thus, the combination of Song and Yoon meets all the limitations of claim 1.
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Regarding claim 10, Song in view of Yoon teaches the semiconductor structure of Claim 1, wherein
The combination of Song and Yoon (Illustrative Fig. 2) further teaches that the semiconductor structure comprises a first semiconductor sub-fin (Yoon: first fin-type active area FAA in the transistor area TA, Illustrative Fig. 2 and Fig. 14A, [0067]) located beneath the first vertical nanosheet stack (stacked structure NSS in the transistor area TA, Illustrative Fig. 2) and a second semiconductor sub-fin (Yoon: first fin-type active area FAA in the resistor area RA, Illustrative Fig. 2 and Fig. 14A, [0067]) located beneath the second vertical nanosheet stack (stacked structure NSS in the resistor area RA, Illustrative Fig. 2).
Regarding claim 11, Song in view of Yoon teaches the semiconductor structure of Claim 10, wherein
The combination of Song and Yoon further teaches that the first semiconductor sub-fin (Yoon: first fin-type active area FAA in the transistor area TA, Illustrative Fig. 2, [0067]) and the second semiconductor sub-fin (Yoon: first fin-type active area FAA in the resistor area RA, Illustrative Fig. 2, [0067]) are both in physical contact with the semiconductor substrate (semiconductor substrate layer 100B, Illustrative Fig. 2, [0029]: first and second sub-fins are extensions of the semiconductor substrate 100B).
Allowable Subject Matter
Claims 2 and 6-9 are objected.
Claims 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2, disclosing that the semiconductor device also comprises “a second resistor device region located in a third portion of the semiconductor substrate, the second resistor device region comprising a third gate structure wrapped around a third vertical nanosheet stack of semiconductor channel material nanosheets that is present in the second resistor device region, and a second metal resistor located above the third gate structure, wherein the third gate structure includes a source/drain region located beneath the second metal resistor that is present in the second resistor device region and extending outward from sidewalls of each semiconductor channel material nanosheets of the third vertical nanosheet stack”, would be allowable if the limitation about a second resistive device with a source/drain region is incorporated in claim 1 or written in independent form along with limitations of claim 1.
Claims 6-9 are objected because they depend directly or indirectly on objected claim 2.
Claim 3-5, 12, and 14-20 are allowed.
Independent claim 3 is allowed because the references of the prior art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that “the source/drain region of the third gate structure extends upward from, and is in direct physical contact with, a surface of a semiconductor sub-fin that is located beneath the third gate structure and the third vertical nanosheet stack” when these limitations are further accompanied by the remaining structural limitations of the claim 3.
The closest prior art regarding the invention disclosed in claim 3 is the combination of Hu (US 2021/0066193 A1), Yoon (US 2022/0208790 A1), and Shin-008 (US 2009/0051008 A1) as detailed in the non-final office action. Accordingly, Hu teaches a semiconductor structure (semiconductor device, Fig. 9B, [0064]) comprising:
a logic device region (circuit area, Fig. 9B, [0042]: the circuit area includes a Fin FET ([0049]-[0050]: the embodiment where the transistor is a FinFET), which is a component of common logic circuits) located in a first portion (see first portion in Illustrative Fig. 3 which is an annotated version of Hu’s Fig. 9B) of a semiconductor substrate (substrate 1, Illustrative Fig. 3, [0028] and [0051]: p-type silicon substrate (Fig. 6C shows the Fin FET structure in 3D where the substrate is 300), the logic device region (circuit area, Illustrative Fig. 3) comprising a first gate structure (metal gate structures 9’ shown as first gate structure in Illustrative Fig. 3, [0042]); and
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a resistor device region (resistor area, Fig. 9B, [0042]: the resistor area includes a Fin FET ([0049]-[0050]: the embodiment where the transistor is a FinFET) located in a second portion (first portion, Illustrative Fig. 3) of the semiconductor substrate (substrate 1, Illustrative Fig. 3), the resistor device region (resistor area, Illustrative Fig. 3) comprising a second gate structure (metal gate structures 9 shown as second gate structure in Illustrative Fig. 3, [0043]), and a first metal resistor (resistor wire 200, Illustrative Fig. 3, [0017]: “The resistor wire 200 is made of a conductive material, such as a metal …”) located above the second gate structure (second gate structure, Illustrative Fig. 3), wherein the second gate structure (second gate structure, Illustrative Fig. 3) is a component of a non-functional nanosheet device (the components of the resistor are dummy structures ([0043]; and “ In the present disclosure, a dummy "element" means that the "element" has no electrical function or is not part of a functioning circuit.” ([0022])).
Hu, however, does not teach that the FET device in the semiconductor device is a nanosheet field-effect transistor, and therefore does not teach that
the logic device region comprises the first gate structure wrapped around a
first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the semiconductor substrate; and
the resistor device region comprises the second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the resistor device region, and a bottom dielectric isolation layer separating the second gate structure from the second portion of the semiconductor substrate.
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Yoon, on the other hand, teaches an integrated circuit device (Fig. 14B, Abstract and [0048]) comprising a region (first region R1, see Illustrative Fig. 4 which is an annotated version of Yoon’s Fig. 14B, [0047]; [0111]: first region R1 may be a logic region) which includes a nanosheet field effect transistor (nanosheet transistors including stacked nanosheets N1, N2, N3; Illustrative Fig. 4, [0031]),
wherein the nanosheet field effect transistor (nanosheet transistors, Illustrative Fig. 4) comprises a gate structure (gate structures comprising gate electrode 150, gate spaces GS, and gate spacer 130, Illustrative Fig. 4, [0048]) wrapped around a vertical nanosheet stack (stacked structure NSS, Illustrative Fig. 4, [0072]), a source/drain region (source/drain regions 160A, Illustrative Fig. 4, [0043]) extending from sidewalls of each of the semiconductor channel material nanosheets (nanosheets N1, N2, N3; Illustrative Fig. 4: source/drain regions 160A cover the sidewalls of the nanosheets N1, N2, N3) of the first vertical nanosheet stack (stacked structure NSS, Illustrative Fig. 4), and a bottom dielectric isolation layer (insulating substrate layer 102, Illustrative Fig. 4, [0016]: insulating substrate layer 102 may include silicon dioxide which is a dielectric) separating the gate structure (comprising gate electrode 150, gate spaces GS, and gate spacer 130, Illustrative Fig. 4, [0048]) and the source/drain region (source/drain regions 160A, Illustrative Fig. 4, [0043]) from the semiconductor substrate (impurity region 104, Illustrative Fig. 4, [0025]).
Yoon further discloses that the design of the nanosheet transistors including the insulating substrate layer 102 on the base substrate layer (impurity region 104, Illustrative Fig. 4) improves the performance of the transistor by reducing the leakage currents ([0083]). A person of ordinary skill in the art before the effective filing date of the claimed invention would also be familiar with the fact that gate-all-around nanosheet field-effect transistors, such as the one disclosed by Yoon, provides scaling and current control advantages over FinFETs, as evidenced by Kumari (page 2, paragraph 3, Kumari and Prithvi (2022), Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters, Microelectronics Journal, Volume 125, 2022, 105432, ISSN 1879-2391, https://doi.org/10.1016/j.mejo.2022.105432). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the FinFET transistors in the circuit and resistor areas of the semiconductor structure of Hu with the gate-all-around nanosheet transistors of Yoon to obtain a semiconductor structure with an improved device performance and scaling.
Accordingly, the combination of Hu and Yoon leads to a semiconductor structure wherein
the logic device region comprises the first gate structure wrapped around a first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the semiconductor substrate; and
the resistor device region comprises the second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the resistor device region, and a bottom dielectric isolation layer separating the second gate structure from the second portion of the semiconductor substrate.
Neither Hu nor Yoon teaches that the semiconductor structure further comprises
a second resistor device region located in a third portion of the semiconductor substrate, the second resistor device region comprising a third gate structure wrapped around a third vertical nanosheet stack of semiconductor channel material nanosheets that is present in the second resistor device region, and a second metal resistor located above the third gate structure, wherein the third gate structure includes a source/drain region located beneath the second metal resistor that is present in the second resistor device region and extending outward from sidewalls of each semiconductor channel material nanosheets of the third vertical nanosheet stack.
Shin-008, on the other hand, teaches a semiconductor device (Figs. 1, [0048]) comprising a circuit region b1 (Fig. 1, [0049]) and a resistor region b2 (Fig. 1, [0049]), wherein the resistor region b2 comprises multiple resistor traces R in separate isolation regions 102 (Fig. 1, [0049]) which are analogous to resistor device regions of the current application and of Hu in view of Yoon in that the resistors of tight tolerance levels needed for a semiconductor circuit ([0002]). Accordingly, Shin-008 teaches that multiple resistor device regions (isolation regions 102, Fig. 1, [0049]) can be formed around an integrated analog/digital circuit ([0002]) which requires multiple resistors.
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a second resistor device region located in a third portion of the semiconductor substrate in the semiconductor structure of Hu in view of Yoon for accommodating a logic device which requires two resistors with tight resistor tolerances (Shin-008, [0002]). Furthermore, a person of ordinary skill in the art would be motivated to form the second resistor device region in an identical form of the first resistor device region for simplifying the manufacturing steps. Thus, the combination of Hu, Yoon and Shin-008 leads to a semiconductor structure comprising
a second resistor device region located in a third portion of the semiconductor substrate, the second resistor device region comprising a third gate structure wrapped around a third vertical nanosheet stack of semiconductor channel material nanosheets that is present in the second resistor device region, and a second metal resistor located above the third gate structure, wherein the third gate structure includes a source/drain region located beneath the second metal resistor that is present in the second resistor device region and extending outward from sidewalls of each semiconductor channel material nanosheets of the third vertical nanosheet stack.
Hu, Yoon, and Shin-008, however, fail to teach the specific limitation that “the source/drain region of the third gate structure extends upward from, and is in direct physical contact with, a surface of a semiconductor sub-fin that is located beneath the third gate structure and the third vertical nanosheet stack, and wherein the semiconductor fin is in contact with the semiconductor substrate”.
Other relevant prior art regarding the invention disclosed in claim 3 is the combination of Shin-254 (US 2021/0296254 A1), Yoon, and Shin-008 (Shin-254 replacing Hu in the prior art combination above), which also fails to teach the same limitation above. Therefore, there has been no prior art identified that can, by itself or in combination with other, render the invention disclosed in claim 3 anticipated or obvious.
Claims 4-5 are also allowed because they inherit allowable subject matter from allowed claim 3.
Independent claim 12 is allowed, because the references of the prior art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that “the source/drain region of the third gate structure extends upward from, and is in direct physical contact with, a surface of a semiconductor sub-fin that is located beneath the second gate structure and the second vertical nanosheet stack, and wherein the semiconductor sub-fin is in contact with the semiconductor substrate” when these limitations are further accompanied by the remaining structural limitations of the claim 12.
The closest prior art regarding the invention disclosed in claim 12 is the combination of Hu (US 2021/0066193 A1) and Yoon (US 2022/0208790 A1) as detailed in the non-final office action. Accordingly, Hu teaches a semiconductor structure (semiconductor device, Fig. 9B, [0064]) comprising:
a logic device region (circuit area, Fig. 9B, [0042]: the circuit area includes a Fin FET ([0049]-[0050]: the embodiment where the transistor is a FinFET), which is a component of common logic circuits) located in a first portion (see first portion in Illustrative Fig. 3 which is an annotated version of Hu’s Fig. 9B) of a semiconductor substrate (substrate 1, Illustrative Fig. 3, [0028] and [0051]: p-type silicon substrate (Fig. 6C shows the Fin FET structure in 3D where the substrate is 300), the logic device region (circuit area, Illustrative Fig. 3) comprising a first gate structure (metal gate structures 9’ shown as first gate structure in Illustrative Fig. 3, [0042]); and
a resistor device region (resistor area, Fig. 9B, [0042]: the resistor area includes a Fin FET ([0049]-[0050]: the embodiment where the transistor is a FinFET) located in a second portion (first portion, Illustrative Fig. 3) of the semiconductor substrate (substrate 1, Illustrative Fig. 3), the resistor device region (resistor area, Illustrative Fig. 3) comprising a second gate structure (metal gate structures 9 shown as second gate structure in Illustrative Fig. 3, [0043]), and a metal resistor (resistor wire 200, Illustrative Fig. 3, [0017]: “The resistor wire 200 is made of a conductive material, such as a metal …”) located above the second gate structure (second gate structure, Illustrative Fig. 3), wherein the second gate structure (second gate structure, Illustrative Fig. 3) includes a source/drain region (source/drain regions 50, Illustrative Fig. 3, [0043]) located beneath the metal resistor (resistor wire 200, Illustrative Fig. 3) that is present in the resistor device region (resistor, Illustrative Fig. 3).
Hu, however, does not teach that the FET device in the semiconductor device is a nanosheet field-effect transistor, and therefore does not teach that
the logic device region comprises the first gate structure wrapped around a
first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the semiconductor substrate; and
the resistor device region comprises the second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the resistor device region, and the source/drain region extending outward from sidewalls of each semiconductor channel material nanosheets of the second vertical nanosheet stack.
Yoon, on the other hand, teaches an integrated circuit device (Fig. 14B, Abstract and [0048]) comprising a region (first region R1, see Illustrative Fig. 4 which is an annotated version of Yoon’s Fig. 14B, [0047]; [0111]: first region R1 may be a logic region) which includes a nanosheet field effect transistor (nanosheet transistors including stacked nanosheets N1, N2, N3; Illustrative Fig. 4, [0031]), wherein the nanosheet field effect transistor (nanosheet transistors, Illustrative Fig. 4) comprises a gate structure (gate structures comprising gate electrode 150, gate spaces GS, and gate spacer 130, Illustrative Fig. 4, [0048]) wrapped around a vertical nanosheet stack (stacked structure NSS, Illustrative Fig. 4, [0072]), a source/drain region (source/drain regions 160A, Illustrative Fig. 4, [0043]) extending from sidewalls of each of the semiconductor channel material nanosheets (nanosheets N1, N2, N3; Illustrative Fig. 4: source/drain regions 160A cover the sidewalls of the nanosheets N1, N2, N3) of the first vertical nanosheet stack (stacked structure NSS, Illustrative Fig. 4), and a bottom dielectric isolation layer (insulating substrate layer 102, Illustrative Fig. 4, [0016]: insulating substrate layer 102 may include silicon dioxide which is a dielectric) separating the gate structure (comprising gate electrode 150, gate spaces GS, and gate spacer 130, Illustrative Fig. 4, [0048]) and the source/drain region (source/drain regions 160A, Illustrative Fig. 4, [0043]) from the semiconductor substrate (impurity region 104, Illustrative Fig. 4, [0025]).
Yoon further discloses that the design of the nanosheet transistors including the insulating substrate layer 102 on the base substrate layer (impurity region 104, Illustrative Fig. 4) improves the performance of the transistor by reducing the leakage currents ([0083]). A person of ordinary skill in the art before the effective filing date of the claimed invention would also be familiar with the fact that gate-all-around nanosheet field-effect transistors, such as the one disclosed by Yoon, provides scaling and current control advantages over FinFETs, as evidenced by Kumari (page 2, paragraph 3, Kumari and Prithvi (2022), Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters, Microelectronics Journal, Volume 125, 2022, 105432, ISSN 1879-2391, https://doi.org/10.1016/j.mejo.2022.105432). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the FinFET transistors in the circuit and resistor areas of the semiconductor structure of Hu with the gate-all-around nanosheet transistors of Yoon to obtain a semiconductor structure with an improved device performance and scaling.
Accordingly, the combination of Hu and Yoon leads to a semiconductor 4 wherein
the logic device region comprises the first gate structure wrapped around a first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the first portion of the semiconductor substrate; and
the resistor device region comprises the second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the resistor device region, and the source/drain region extending outward from sidewalls of each semiconductor channel material nanosheets of the second vertical nanosheet stack.
Hu and Yoon, however, fail to teach that “the source/drain region of the third gate structure extends upward from, and is in direct physical contact with, a surface of a semiconductor sub-fin that is located beneath the second gate structure and the second vertical nanosheet stack, and wherein the semiconductor sub-fin is in contact with the semiconductor substrate”
Other relevant prior art regarding the invention disclosed in claim 12 is the combination of Shin-254 (US 2021/0296254 A1) and Yoon, which also fails to teach the same limitation above. Therefore, there has been no prior art identified that can, by itself or in combination with other, render the invention disclosed in claim 12 anticipated or obvious.
Claims 14-20 are also allowed because they inherit allowable subject matter from allowed claim 12.
Response to Arguments
It has been acknowledged that the applicant amended claims 1-3, 9, 12, 14, and 20, and cancelled claim 13 per response dated on 11/24/2025. Applicant's arguments with respect to claims have been fully considered.
Regarding amended claim 1, now disclosing the limitation “the first resistor device region is entirely absent of any source/drain region”, the Examiner agrees with the Applicant on that the amended claim 1 overcame the rejection made previously based on the prior art Hu and Yoon in the non-final office action. However, amended claim 1 is now rejected under new grounds based on a new prior-art, Song (US 2016/0307887 A1), in the current office action. Rejections are also made on claims 10-11 which are dependent on claim 1 based on this new prior-art or its combination with the prior-art of the non-final office action.
However, amended claim 1 now rendered claim 2 allowable because no prior art has been identified that can make claim 2 anticipated or obvious considering the limitations inherited from the amended claim 1. Therefore, claim 2 and claim 6-9 which are dependent on claim 2 are objected in the current office action.
Regarding amended claim 3, the applicant amended this claim to present it in an independent form by combining with claims 1 and 2 of the original application. Therefore, as detailed above in the current office action, claim 3 is allowed. Accordingly, claims 4-5 are also allowed.
Regarding amended claim 12, the applicant amended claim 12 by incorporating allowable subject matter from claim 13. Therefore, as detailed above in the current office action, claim 12 is allowed. Accordingly, claims 14-20 which are directly or indirectly dependent on claim 12 are also allowed.
For the purpose of compact prosecution, the Examiner notes that incorporating claim 2 fully or partly with independent claim 1 might render claim 1 also inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812