Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 10/27/2025 is acknowledged.
Response to Amendment
The amendment filed 10/27/2025 has been entered. Claims 1-21 remain pending. Examiner finds Applicant’s argument with respect to method claims 10-15 persuasive, and therefore, will be examining Claims 1-21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over US20210225809A1 (Yu) in view of US20190279919A1 (Xu).
Regarding Claim 1, Yu discloses an electronic device (Fig. 11A, el. 1100, Para. [0079] comprising: a package substrate (Fig. 11A, el. 1110, Para. [0082] – although this is described as an interposer substrate, Examiner is considering it to be a package substrate, since the devices 1102 and 900 sit on it); a memory integrated circuit (IC) (Fig. 11A, el. 900, Para. [0080]) mounted on the package substrate (Para. [0080]), a mold layer (Fig. 11A, el. 1104, Para. [0080]) including a device die (Fig. 11A, el. 1102, Para. [0080]) also mounted on the package substrate (Para. [0080]), and a heat spreader (Fig. 11A, el. 1106, Para. [0081]) having a uniform surface (Fig. 11A) contacting the memory IC and the device die (Para. [0081])
Yu does not disclose that the mold layer includes one or more chiplets and a base die within the mold layer, the one more more chiplets arranged on the base die. Yu also does not disclose a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC, and that the heat spreader contacts the top chiplet.
Xu discloses a package on package structure (Fig. 2, el. 200, Para. [0034]) that includes a mold layer (Fig. 2, el. 112, Para. [0027]) including a base die (Fig. 2, el. 108A) and one or more chips (Fig. 2, els. 108b-108f) arranged on the base die (Fig. 2); and a top chip mounted on a surface of the mold layer (Fig. 2, el. 210, Para. [0034]). Xu further discloses multiple TMVs disposed around a periphery of the one or more chips (Fig. 1B, Para. [0033]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to substitute the stacked die structure with the molding layer of Xu for the device die of Yu, keeping the height of the stacked structure substantially the same as the device die, so as to maintain the configuration of the structure disclosed by Yu. Doing so would have the benefit of allowing multiple different kinds of chips to be integrated in one molding layer (Xu, Para. [0020]). Adding a top chip has the benefit of allowing a compact PoP packaging structure. Finally, it would be obvious to use chiplets in place of chips to take advantage of their smaller size compared to chips while using a stacked architecture.
Regarding Claim 2, Yu in view of Xu discloses the electronic device of claim 1.
Xu further discloses at least one through mold via (Figs. 1a and 2, el. 116a, Para. [0028]) that provides electrical continuity form the package substrate to the top chip (Figs. 1A and 2, Para. [0030] and [0031]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add the TMV of Xu to the combination of Yu and Xu to allow electrical connection from the top chiplet to the package substrate without having to use a TSV.
Regarding Claim 3, Yu in view of Xu discloses the electronic device of Claim 2.
Xu further discloses multiple TMVs disposed around a periphery of the one or more chips (Fig. 1B, Para. [0033]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add multiple TMVs that are arranged around a periphery of the one or more chiplets, as taught by Xu. Doing so would have the benefit of allowing multiple interconnections between the top chiplet and the package substrate. Connecting them to a ground plane has the benefit of providing a solid ground for the entire molding layer package.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu and US20180174972A1 (Weng).
Regarding Claim 4, Yu in view of Xu discloses the electronic device of claim 1, including a redistribution layer (RDL) (Yu, Fig. 11A, el. 1114, Para. [0083]) disposed between the mold layer and the package substrate (Fig. 11A, where the RDL layer 1114 is disposed between the mold layer 1104 and the package substrate 1116), wherein the RDL layer includes an electrically conductive microstrip in the RDL layer to carry a signal between the memory IC and the one or more chiplets within the mold layer (Para. [0083]).
Yu in view of Xu does not disclose that the package substrate has a surface microstrip on a surface of the package substrate, and does not disclose that the RDL layer includes a shield layer to shield the surface microstrip from EMI.
Weng discloses a microelectronics package (Fig. 1, el. 100, Para. [0014]) that includes a first die (Fig. 1, el. 102, Para. [0014]), a second die (Fig. 1, el. 104, Para. [0014]), a package interconnect (Fig. 1, el. 106, Para. [0014]), and a substrate (Fig. 1, el. 108, Para. [0014]). Weng further discloses a microstrip routing package (Figs. 4A and 4B, el. 400, Para. [0016]), with an EMI shield (Fig. 4B, el. 426, Para. [0019]) that protects dual data rate lines from EMI interference (Para. [0019]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use the EMI shielding structure of Weng in the RDL layer of Yu in view of Xu, while moving the microstrip from the RDL layer to the package substrate below to provide for EMI shielding of the memory signals. As disclosed by Weng, adding this shielding layer above the memory signals can protect nearby radio antennas from undesired energy coupling from the memory signals (Para. [0019]). Further, moving the microstrip from an internal layer to the surface of the package substrate is an obvious design choice (MPEP 2144.04(VI)(C)).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu and Weng.
Regarding Claim 5, Yu in view of Xu discloses the electronic device of Claim 1, wherein the RDL layer includes an electrically conductive microstrip to carry a memory signal between the memory IC and the one or more chiplets within the mold layer (Para. [0083]).
Yu in view of Xu does not disclose that the microstrip is in the package substrate and does not disclose a shield layer in the package substrate.
Weng discloses a microelectronics package (Fig. 1, el. 100, Para. [0014]) that includes a first die (Fig. 1, el. 102, Para. [0014]), a second die (Fig. 1, el. 104, Para. [0014]), a package interconnect (Fig. 1, el. 106, Para. [0014]), and a substrate (Fig. 1, el. 108, Para. [0014]). Weng further discloses a microstrip routing package (Figs. 4A and 4B, el. 400, Para. [0016]), with an EMI shield (Fig. 4B, el. 426, Para. [0019]) that can be above or below the microstrip (Para. [0021]) that protects dual data rate lines from EMI interference (Para. [0019]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use the EMI shielding structure of Weng in the package substrate of Yu in view of Xu, while moving the memory signals to the package substrate below to provide for EMI shielding of the memory signals. Moving the memory signals to the package substrate allows for a shielding layer to be placed in the RDL layer above, while adding a shielding layer below the memory signals in the package substrate can protect devices that are below the memory signal from interference.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu, Weng, and US20200027813A1 (Cheah).
Regarding Claim 6, Yu in view of Zu and Weng discloses the electronic device of Claim 5.
Yu in view of Zu and Weng does not disclose wherein the base IC die includes a first through silicon (TSV) connected to the microstrip and the one or more chiplets, and at least a second TSV connected to the shield layer and the one or more chiplets.
Cheah discloses a electronic system (Fig. 1A, el. 100) including two stacked dies (Fig. 1A, els. 110 and 112, Para. [0013]) and a Through Silicon Via (Fig. 1A, el. 118, Para. [0013]) that extends through the first die and connects the first and second dies to a substrate.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add TSVs through the base die, as in Cheah, to connect the microstrip and another chiplet, and another TSV to connect the shield layer and another chiplet. This has the benefit of connecting these elements while saving space by having the via through the base die.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu and US20170018497A1 (Zhai).
Regarding Claim 7, Yu in view of Xu discloses the electronic device of claim 1.
Xu further discloses at least one through mold via (Figs. 1a and 2, el. 116a, Para. [0028]) that provides electrical continuity form the package substrate to the top chip (Figs. 1A and 2, Para. [0030] and [0031]).
Yu in view of Xu does not disclose that the top chiplet includes at least one MIM capacitor, and does not disclose a TMV that provides electrical continuity from the package substrate to the MIM capacitor of the top chiplet.
Zhai discloses a chip (Fig. 2, el. 200, Para. [0028]) that includes a MIM capacitor (Fig. 2, el. 210) integrated into the chip (Para. [0028]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use an integrated MIM capacitor in the top chiplet of Yu in view of Zu. As disclosed by Zhai, having an integrated MIM capacitor has many advantages over an external capacitor. For example, having a MIM capacitor can save space (Zhai, Para. [0027]). Further, it would have been obvious to add a TMV to connect the MIM capacitor to the package substrate. First, Xu already discloses a TMV that connects the top chip to the package substrate. Further, doing so would have the advantage of connecting the MIM capacitor to a ground plane in the package structure efficiently, without having to use a via through the silicon, which is more expensive and complicated in design.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu and Zhai.
8. Regarding Claim 8, Yu in view of Xu discloses the electronic device of claim 1.
9. Xu further discloses that the chips within the mold layer include a SoC chip and a compute chip stacked on the base die (Para. [0020]).
10. Yu in view of Xu does not disclose that the top chiplet includes at least one MIM capacitor.
Zhai discloses a chip (Fig. 2, el. 200, Para. [0028]) that includes a MIM capacitor (Fig. 2, el. 210) integrated into the chip (Para. [0028]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to have one of the chiplets be an SoC chiplet and another be a compute chiplet. This would have the benefit of including a standard digital chips integrated in the stackup. Further, it would have been obvious to use an integrated MIM capacitor in the top chiplet of Yu in view of Zu. As disclosed by Zhai, having an integrated MIM capacitor has many advantages over an external capacitor. For example, having a MIM capacitor can save space (Zhai, Para. [0027]).
Regarding Claim 9, Yu in view of Xu and Zhai discloses the electronic device of Claim 8.
Xu further discloses that the top chip can include multiple semiconductor devices (Para. [0035]) and discloses multiple TMVs disposed around a periphery of the one or more chiplets (Fig. 1B, Para. [0033]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to include a fourth chiplet bonded to the top chiplet. Xu already discloses that the top package can comprise multiple chips. Adding a fourth chiplet to the top chiplet has the benefit of increasing the functionality to the stackup. Further, it would have been obvious to add multiple TMVs that are arranged around a periphery of the one or more chiplets, as taught by Xu. Doing so would have the benefit of allowing multiple interconnections between the top chiplet and the package substrate. Connecting them to a ground plane has the benefit of providing a solid ground for the entire molding layer package.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu.
Regarding Claim 10, Yu discloses a method of forming an electronic device (inherent in the device structure), the method comprising: mounting a memory integrated circuit (IC) (Fig. 11A, el. 900, Para. [0080]) on a package substrate (Fig. 11A, el. 1110, Para. [0082] – although this is described as an interposer substrate, Examiner is considering it to be a package substrate, since the devices 1102 and 900 sit on it); forming a mold layer (Fig. 11A, el. 1104, Para. [0080]) including a device die (Fig. 11A, el. 1102, Para. [0080]) also mounted on the package substrate (Para. [0080]); and contacting the memory IC and the device die with a uniform surface of a heat spreader (Fig. 11A, el. 1106, Para. [0081]).
Yu does not disclose that the mold layer includes one or more chiplets and a base die within the mold layer, the one more more chiplets arranged on the base die. Yu also does not disclose mounting a top chiplet on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC, and that the heat spreader contacts the top chiplet.
Xu discloses a package on package structure (Fig. 2, el. 200, Para. [0034]) that includes a mold layer (Fig. 2, el. 112, Para. [0027]) including a base die (Fig. 2, el. 108A) and one or more chips (Fig. 2, els. 108b-108f) arranged on the base die (Fig. 2); and a top chip mounted on a surface of the mold layer (Fig. 2, el. 210, Para. [0034]), with at least one through mold via (Figs. 1a and 2, el. 116a, Para. [0028]) that provides electrical continuity form the package substrate to the top chip (Figs. 1A and 2, Para. [0030] and [0031]). Xu further discloses multiple TMVs disposed around a periphery of the one or more chips (Fig. 1B, Para. [0033]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to substitute the stacked die structure with the molding layer of Xu for the device die of Yu, keeping the height of the stacked structure substantially the same as the device die, so as to maintain the configuration of the structure disclosed by Yu. Doing so would have the benefit of allowing multiple different kinds of chips to be integrated in one molding layer (Xu, Para. [0020]). Adding a top chip has the benefit of allowing a compact PoP packaging structure. Finally, it would be obvious to use chiplets in place of chips to take advantage of their smaller size compared to chips while using a stacked architecture.
Regarding Claim 11, Yu in view of Xu discloses the method of claim 10.
Xu further discloses forming at least one through mold via (Figs. 1a and 2, el. 116a, Para. [0028]) that provides electrical continuity form the package substrate to the top chip (Figs. 1A and 2, Para. [0030] and [0031]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add the step of forming the TMV of Xu to the combination of Yu and Xu to allow electrical connection from the top chiplet to the package substrate without having to use a TSV.
Regarding Claim 12, Yu in view of Xu discloses the method of Claim 10.
Xu further discloses multiple TMVs disposed around a periphery of the one or more chips (Fig. 1B, Para. [0033]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add multiple TMVs that are arranged around a periphery of the one or more chiplets, as taught by Xu. Doing so would have the benefit of allowing multiple interconnections between the top chiplet and the package substrate. Connecting them to a ground plane has the benefit of providing a solid ground for the entire molding layer package.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu and Weng.
Regarding Claim 13, Yu in view of Xu discloses the method of claim 10, including disposing a redistribution layer (RDL) (Yu, Fig. 11A, el. 1114, Para. [0083]) between the mold layer and the package substrate (Fig. 11A, where the RDL layer 1114 is disposed between the mold layer 1104 and the package substrate 1116), and forming an electrically conductive microstrip in the RDL layer to carry a signal between the memory IC and the one or more chiplets within the mold layer (Para. [0083]).
Yu in view of Xu does not disclose forming a surface microstrip on a surface of the package substrate, and does not disclose that the RDL layer includes a shield layer to shield the surface microstrip from EMI.
Weng discloses a microelectronics package (Fig. 1, el. 100, Para. [0014]) that includes a first die (Fig. 1, el. 102, Para. [0014]), a second die (Fig. 1, el. 104, Para. [0014]), a package interconnect (Fig. 1, el. 106, Para. [0014]), and a substrate (Fig. 1, el. 108, Para. [0014]). Weng further discloses a microstrip routing package (Figs. 4A and 4B, el. 400, Para. [0016]), with an EMI shield (Fig. 4B, el. 426, Para. [0019]) that protects dual data rate lines from EMI interference (Para. [0019]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use the EMI shielding structure of Weng in the RDL layer of Yu in view of Xu, while moving the microstrip from the RDL layer to the package substrate below to provide for EMI shielding of the memory signals. As disclosed by Weng, adding this shielding layer above the memory signals can protect nearby radio antennas from undesired energy coupling from the memory signals (Para. [0019]). Further, forming the microstrip on the surface of the package substrate is an obvious design choice (MPEP 2144.04(VI)(C)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu and Weng.
Regarding Claim 14, Yu in view of Xu discloses the method of Claim 10, including forming RDL lan electrically conductive microstrip in the RDL layer to carry a memory signal between the memory IC and the one or more chiplets within the mold layer (Para. [0083]).
Yu in view of Xu does not disclose forming the microstrip in the package substrate and does not disclose forming a shield layer.
Weng discloses a microelectronics package (Fig. 1, el. 100, Para. [0014]) that includes a first die (Fig. 1, el. 102, Para. [0014]), a second die (Fig. 1, el. 104, Para. [0014]), a package interconnect (Fig. 1, el. 106, Para. [0014]), and a substrate (Fig. 1, el. 108, Para. [0014]). Weng further discloses a microstrip routing package (Figs. 4A and 4B, el. 400, Para. [0016]), with an EMI shield (Fig. 4B, el. 426, Para. [0019]) that can be above or below the microstrip (Para. [0021]) that protects dual data rate lines from EMI interference (Para. [0019]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention form an EMI shield layer (similar to Weng) in the package substrate of Yu in view of Xu, while forming the microstrip in the package substrate below the RDL to provide for EMI shielding of the memory signals. Forming the microstrip in the package substrate allows for a shielding layer to be placed in the RDL layer above, while forming a shielding layer below the memory signals in the package substrate can protect devices that are below the memory signal from interference.
Regarding Claim 15, Yu in view of Xu discloses the method of claim 1.
Yu in view of Xu does not disclose that the top chiplet includes at least one MIM capacitor, and the mold layer includes at least one TMV that provides electrical continuity from the package substrate to the MIM capacitor of the top chiplet.
Zhai discloses a chip (Fig. 2, el. 200, Para. [0028]) that includes a MIM capacitor (Fig. 2, el. 210) integrated into the chip (Para. [0028]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use an integrated MIM capacitor in the top chiplet of Yu in view of Zu. As disclosed by Zhai, having an integrated MIM capacitor has many advantages over an external capacitor. For example, having a MIM capacitor can save space (Zhai, Para. [0027]). Further, it would have been obvious to add a TMV to connect the MIM capacitor to the package substrate. First, Xu already discloses a TMV that connects the top chip to the package substrate. Further, doing so would have the advantage of connecting the MIM capacitor to a ground plane in the package structure efficiently, without having to use a via through the silicon, which is more expensive and complicated in design.
Claim 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu.
Regarding Claim 16, Yu discloses a packaged electronic system (Fig. 11A, el. 1100, Para. [0079]) comprising: a package substrate (Fig. 11A, el. 1110, Para. [0082] – although this is described as an interposer substrate, Examiner is considering it to be a package substrate, since the devices 1102 and 900 sit on it); a memory integrated circuit (IC) (Fig. 11A, el. 900, Para. [0080]) mounted on the package substrate (Para. [0080]), a mold layer (Fig. 11A, el. 1104, Para. [0080]) including a device die (Fig. 11A, el. 1102, Para. [0080] also mounted on the package substrate (Para. [0080]); a redistribution layer (RDL) (Yu, Fig. 11A, el. 1114, Para. [0083]) disposed between the mold layer and the package substrate (Fig. 11A, where the RDL layer 1114 is disposed between the mold layer 1104 and the package substrate 1116), wherein the RDL layer includes an electrically conductive surface microstrip in the RDL layer to carry a signal between the memory IC and the one or more chips within the mold layer (Para. [0083]).
Yu does not disclose that the mold layer includes multiple chiplets and a base die within the mold layer, the multiple chiplets including at least one chiplet stacked on the base die. Yu also does not disclose that the package substrate has the microstrip, that the microstrip is on the surface of the package substrate and does not disclose that the RDL layer includes a shield layer to shield the surface microstrip from EMI.
Xu discloses a package on package structure (Fig. 2, el. 200, Para. [0034]) that includes a mold layer (Fig. 2, el. 112, Para. [0027]) including a base die (Fig. 2, el. 108A) and one or more chips (Fig. 2, els. 108b-108f) arranged on the base die (Fig. 2); and a top chip (Fig. 2, el. 210, Para. [0034]), with at least one through mold via (Figs. 1a and 2, el. 116a, Para. [0028]) that provides electrical continuity form the package substrate to the top chip (Figs. 1A and 2, Para. [0030] and [0031]). Xu further discloses multiple TMVs disposed around a periphery of the one or more chiplets (Fig. 1B, Para. [0033]).
Weng discloses a microelectronics package (Fig. 1, el. 100, Para. [0014]) that includes a first die (Fig. 1, el. 102, Para. [0014]), a second die (Fig. 1, el. 104, Para. [0014]), a package interconnect (Fig. 1, el. 106, Para. [0014]), and a substrate (Fig. 1, el. 108, Para. [0014]). Weng further discloses a microstrip routing package (Figs. 4A and 4B, el. 400, Para. [0016]), with an EMI shield (Fig. 4B, el. 426, Para. [0019]) that protects dual data rate lines from EMI interference (Para. [0019]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to substitute the stacked die structure with the molding layer of Xu for the device die of Yu. Doing so would have the benefit of allowing multiple different kinds of chips to be integrated in one molding layer (Xu, Para. [0020]).
Further, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to use the EMI shielding structure of Weng in the RDL layer of Yu in view of Xu, while moving the memory signals to the package substrate below to provide for EMI shielding of the memory signals. As disclosed by Weng, adding this shielding layer above the memory signals can protect nearby radio antennas from undesired energy coupling from the memory signals (Para. [0019]). Finally, moving the microstrip from an internal layer to the surface of the package substrate is an obvious design choice (MPEP 2144.04(VI)(C)).
Regarding Claim 17, Yu in view of Xu and Weng discloses the system of Claim 16.
Yu in view of Xu and Weng does not disclose an electrically conductive microstrip to carry a memory signal between the memory IC and the at least one chiplet of the multiple chiplets within the mold layer; and a shield layer to shield the microstrip from EMI.
However, it would have been obvious to add another memory signal in the package substrate as a way to connect the memory IC to the stacked dies using another layer of the package substrate. Adding another EMI shield in the package substrate is also obvious because it can shield the signal from below.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu, Weng, and Zhai.
Regarding Claim 18, Yu in view of Xu and Weng discloses the system of Claim 16.
Xu further discloses a top chip mounted on a surface of the mold layer (Fig. 2, el. 210, Para. [0034]), with at least one through mold via (Figs. 1a and 2, el. 116a, Para. [0028]) that provides electrical continuity form the package substrate to the top chip (Figs. 1A and 2, Para. [0030] and [0031]).
Yu in view of Zu and Weng does not disclose that a top chiplet disposed on a surface of the mold layer that includes a MIM capacitor, and does not disclose that at least one TMV provides electrical continuity from the package substrate to the MIM capacitor of the top chiplet.
Zhai discloses a chip (Fig. 2, el. 200, Para. [0028]) that includes a MIM capacitor (Fig. 2, el. 210) integrated into the chip (Para. [0028]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add the top chiplet to the stack of chiplets in Yu in view of Xu, as disclosed by Xu. This would have the benefit of adding more functionality to the stack and allowing for a device with a larger footprint to be added on top.
Further, it would have been obvious to use an integrated MIM capacitor in the top chiplet of Yu in view of Zu. As disclosed by Zhai, having an integrated MIM capacitor has many advantages over an external capacitor. For example, having a MIM capacitor can save space (Zhai, Para. [0027]). Finally, it would have been obvious to add a TMV to connect the MIM capacitor to the package substrate. Doing so would have the advantage of connecting the MIM capacitor to a ground plane in the package structure, for example.
Regarding Claim 19, Yu in view of Xu, Weng and Zhai discloses the system of claim 18.
Xu further discloses multiple TMVs disposed around a periphery of the one or more chiplets (Fig. 1B, Para. [0033]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add multiple TMVs that are arranged around a periphery of the one or more chiplets, as taught by Xu. Doing so would have the benefit of allowing multiple interconnections between the top chiplet and the package substrate. Connecting them to a ground plane has the benefit of providing a solid ground for the entire molding layer package.
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xu, Weng and Cheah.
Regarding Claim 20, Yu in view of Zu and Weng discloses the system of Claim 16.
Yu in view of Zu and Weng does not disclose wherein the base IC die includes a first through silicon (TSV) connected to the microstrip and the at least one chiplet of the multiple chiplets, and at least a second TSV connected to the shield layer of the RDL and the at least one chiplet.
Cheah discloses a electronic system (Fig. 1A, el. 100) including two stacked die (Fig. 1A, els. 110 and 112, Para. [0013]) and a Through Silicon Via (Fig. 1A, el. 118, Para. [0013]) that extends through the first die and connects the first and second dies to a substrate.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add TSVs through the base die, as in Cheah, to connect the microstrip and another chiplet, and another TSV to connect the shield layer and another chiplet. This has the benefit of connecting these elements while saving space by having the via through the base die.
Regarding Claim 21, Yu in view of Xu and Weng discloses the system of Claim 16.
Xu further discloses that the multiple chiplets within the mold layer include a first chiplet (Fig. 2, el. 108b) and a second chiplet (Fig. 2, el. 108c) stacked on the base IC die (Fig. 2, el. 108A).
Yu in view of Xu and Weng does not disclose that the I/O pad of the first chiplet is connected to an I/O pad of the second chiplet by a through silicon interconnect of a top chiplet.
Cheah discloses a electronic system (Fig. 1A, el. 100) including two stacked die (Fig. 1A, els. 110 and 112, Para. [0013]) and a Through Silicon Via (Fig. 1A, el. 118, Para. [0013]) that extends through the first die and connects the first and second dies to a substrate.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add TSVs through a top chiplet, to provide connections between the first die and the second die while saving space using a TSV. Further, adding a top chiplet can extend the functionality of the package, and having a TSV through it allows the top chiplet to connect to the rest of the dies.
Conclusion
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899