DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102/103, filed 11/24/2025, with respect to the rejection of claim 1 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kuo, Chia-Ming et al. (Pub No. US 20170243952 A1) (hereinafter, Kuo).
6. Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102/103, filed 11/24/2025, with respect to the rejection of claim 21 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim, Kook-Tae et al. (Pub No. US 20160141381 A1) (hereinafter, Kim).
6. Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102/103, filed 11/24/2025, with respect to the rejection of claim 24 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kuo, Chia-Ming et al. (Pub No. US 20170243952 A1) (hereinafter, Kuo) in view of Song, Hyun-Seung (Pub No. US 20160020205 A1) (hereinafter, Song).
7. Applicant’s arguments, see Claim Rejection under 35 U.S.C. § 112, filed 11/24/2025, with respect to the rejection of claims 15-20 have been fully considered and are persuasive. The rejection of claims 15-20 has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1-5 and 7-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo, Chia-Ming et al. (Pub No. US 20170243952 A1) (hereinafter, Kuo).
Kuo, Fig 8: Transistor with SiCN/SiOCN Multilayer Spacer
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Re Claim 1, (Currently Amended) Kuo teaches a transistor, comprising:
a channel region (Fin type active pattern; 110; Fig 8; ¶[0030]);
a gate structure (Metal gate structure; 170; Fig 8; ¶[0044]) over the channel region;
a first spacer (Right hand spacer/Blocking film; 130/150; Fig 8; ¶[0035]) on a first end (Right side) of the gate structure;
a second spacer (Left hand spacer/Blocking film; 130/150; Fig 8; ¶[0035]) on a second end (Left side) of the gate structure, wherein each of the first spacer and the second spacer comprises:
a first layer (Spacer film; 132a; Fig 8; ¶[0035]) with a first dielectric constant (Dielectric constant of SiOCN; ¶[0035]); and
a second layer (Blocking Film; 150; Fig 8; ¶[0035]) with a second dielectric constant (Dielectric constant from value of 4 to 6, SiCN; ¶[0035]) that is higher (Dielectric constant of SiCN is higher than SiOCN due to the lack of oxygen composition in SiCN) than the first dielectric constant;
the second layer along an outer sidewall (Outer sidewall of 132a; Fig 8) of the first layer, wherein the first layer is between the channel region and the second layer (Per Figure 8, the first layer 132a is between the channel region 110 and the blocking film 150);
a source region (Epitaxial structure (may be source region); 140; Fig 8; ¶[0036]) adjacent to the first spacer; and
a drain region (Epitaxial structure (may be drain region); 140; Fig 8; ¶[0036]) adjacent to the second spacer.
Re Claim 2, Kuo teaches the transistor of claim 1, wherein the first layer (Spacer film; 132a; Fig 8; ¶[0035]) is adjacent to the channel region (Fin type active pattern; 110; Fig 8; ¶[0030]), and
wherein the second layer (Blocking Film; 150; Fig 8; ¶[0035]) is outside of the first layer.
Re Claim 3, (Original) Kuo teaches the transistor of claim 1, wherein the first layer (Spacer film; 132a; Fig 8; ¶[0035]) has a first etch resistance (Per ¶[0033] 132 has poor etch resistance against the oxygen-based etch process in comparison to SiCN), and the second layer (Blocking Film; 150; Fig 8; ¶[0035]) has a second etch resistance (Per ¶[0032]) 131 has higher etch resistance against oxygen-based etch process), wherein the first etch resistance is lower than the second etch resistance.
Re Claim 4, (Currently Amended) Kuo teaches the transistor of claim 1, wherein each of the first spacer (Right hand spacer; 130; Fig 8; ¶[0035]) and the second spacer (Left hand spacer; 130; Fig 8; ¶[0035]) further comprises:
a third layer (Second spacer film 131a closest to gate electrode; Fig 8), wherein the third layer is between (Between 132 and 110; Fig 8) the first layer and the channel region.
Re Claim 5, (Original) Kuo teaches the transistor of claim 4, wherein the third layer (Second spacer film 131a closest to gate electrode; Fig 8) is the same material as the second layer (Spacer film; 131a; Fig 8; ¶[0035]).
Re Claim 7, (Original) Kuo teaches the transistor of claim 4, wherein a thickness (Thickness of third layer (lower portion); Fig 8) of the third layer (Second spacer film 131a closest to gate electrode; Fig 8) is different (Thickness of first layer closest to gate electrode varies whereas thickness of second layer is uniform; Fig 8) than a thickness (Thickness of entire second layer 131; Fig 8) of the second layer (Spacer film furthest from gate electrode; 131a; Fig 8; ¶[0035]).
Re Claim 8, (Original) Kuo teaches the transistor of claim 4, wherein a thickness (Uniform thickness; ¶[0032]) of the third layer (Second spacer film 131a closest to gate electrode; Fig 8) is the same as a thickness of the second layer (Spacer film; 131a; Fig 8; ¶[0035]).
Re Claim 9, (Original) Kuo teaches the transistor of claim 1, wherein the first layer (Spacer film; 132a; Fig 8; ¶[0035]) has a first oxygen concentration (May be SiOCN; ¶[0033]) and wherein the second layer (Blocking Film; 150; Fig 8; ¶[0035]) has a second oxygen concentration (May have a gradient concentration of SiOCN; ¶[0034])), wherein the first oxygen concentration is greater (Spacer film 132a may have less SiCN concentration making it dominant in SiOCN (Oxygen); ¶[0034]) than the second oxygen concentration.
Re Claim 10, (Original) Kuo teaches the transistor of claim 9, wherein an oxygen concentration of the first spacer (Right hand spacer; 130; Fig 8; ¶[0035]) and the second spacer (Left hand spacer; 130; Fig 8; ¶[0035]) includes a gradient (In an embodiment, a gradient concentration of SiOCN, therefore oxygen changes through a decrease in SiCN concentration from the substrate to the outer surface; ¶[0034]) from the first oxygen concentration to the second oxygen concentration.
Re Claim 11, (Original) Kuo teaches the transistor of claim 1, wherein the first layer (Spacer film; 132a; Fig 8; ¶[0035]) comprises silicon, oxygen, and nitrogen (May be SiOCN; ¶[0033]), and
wherein the second layer (Spacer film; 131a; Fig 8; ¶[0035]) comprises silicon, carbon, and nitrogen (May have a gradient concentration of SiOCN; ¶[0034])).
Re Claim 12, (Original) Kuo teaches the transistor of claim 10, wherein the first layer (Spacer film; 132a; Fig 8; ¶[0035]) further comprises carbon (May contain carbon; ¶[0033]), and wherein the second layer (Spacer film; 131a; Fig 8; ¶[0035]) further comprises oxygen (May contain oxygen; ¶[0035]).
Re Claim 13, (Original) Kuo teaches the transistor of claim 1, wherein the channel region (Fin type active pattern; 110; Fig 8; ¶[0030]) comprises a semiconductor fin (Comprises of a fin; ¶[0030]).
10. Claims 15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harada, Kazuhiro et al. (Pub No. US 20210040609 A1) (hereinafter, Harada).
Re Claim 15, (Currently Amended) A method of forming a spacer (SiOCN film; ¶[0046]) in a transistor (Wafer, i.e. used for a transistor; ¶[0046]), comprising:
performing a deposition cycle (Cycle to deposit SiOCN film; ¶[0046]), comprising:
flowing a silicon source (Silicon (Si) source, i.e. Hexachlorodisilane (HDCS) gas; ¶[0046]) into a chamber (Process container; ¶[0046]);
flowing a carbon source (Carbon (C) source, i.e. C3H6 ; ¶[0046]) into the chamber;
flowing a nitrogen source (Nitrogen (N) source, i.e. NH3; ¶[0046]) into the chamber;
and flowing an oxygen source (Oxygen (O2) source; ¶[0046]) into the chamber; and
repeating the deposition cycle a plurality of times (Cycle with predetermined number n times is repeated; ¶[0046]).
Re Claim 19, (Original) The method of claim 15, further comprising:
an inert purge (Purge using inert gas, i.e. N2; ¶¶[0029, 0063, 0072, 0081, 0090]; Note: paragraphs 0063, 0072, 0081 and 0090 correspond to each process in the deposition cycle, respectively) between each operation of the deposition cycle (Cycle to deposit SiOCN film; ¶[0046]).
Re Claim 20, (Original) The method of claim 15, wherein the silicon source (Silicon (Si) source, i.e. Hexachlorodisilane (HDCS) gas; ¶[0046]) comprises halogenated silane (HDCS is a silane containing a halogen element; ¶[0023]),
and wherein the nitrogen source (Nitrogen (N) source, i.e. NH3; ¶[0046]) comprises ammonia (Ammonia, i.e. NH3; ¶[0026]).
11. Claims 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim, Kook-Tae et al. (Pub No. US 20160141381 A1) (hereinafter, Kim).
Kim, Fig 4: Transistor comprising of spacers with concentration gradients
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Re Claim 21, (Currently Amended) Kim teaches a transistor, comprising:
a pair of spacers (Gate spacers on left and right side of gate; 150; Fig 4; ¶[0031]), wherein each of the spacers comprises:
a composition gradient (Different compositions of oxygen concentration between the first, second and third spacers 151/152/153; ¶¶[0054, 0060]) from a first layer (First spacer; 151; Fig 4; ¶[0049]) to a second layer (Third spacer; 153; Fig 4; ¶[0052]),
wherein the composition gradient has a first oxygen concentration (151 may have oxygen concentration of 25% to 40% and not limited to the same concentration as the oxygen concentration of 153; ¶[0060]) at the first layer,
a second oxygen concentration (Spacer 152 may have oxygen concentration of 35% to 50%; ¶[0054]) at a third layer (Second spacer; 152; Fig 4; ¶[0049]) of the spacer between the first layer and the second layer,
and a third oxygen concentration (153 may have oxygen concentration of 25% to 40% and not limited to the same concentration as the oxygen concentration of 151; ¶[0060]) at the second layer, wherein the second oxygen concentration is greater (Oxygen concentration of middle spacer 152 has greater range, i.e. 35-50% than oxygen concentration of outer spacers 151/153; i.e. 25-40%; ¶¶[0054, 0060]) than the first oxygen concentration and the third oxygen concentration;
wherein the third layer has a lower dielectric constant (Second spacer 152 may have a lower dielectric constant than first/third spacers 151/153; ¶[0064]) than the first layer and a lower dielectric constant than the second layer, and
wherein the second layer is along an outer sidewall (Third spacer 153 is on an outer sidewall of second spacer 152; Fig 4) of the third layer,
a channel region (Fin active pattern; 120; Fig 20; ¶[0033]; Note: Per Fig 20 the Upper portion of fin active pattern 120 is between pair of spacers) between the pair of spacers; and
a gate stack (Gate electrode; 147; Fig 4; ¶[0031]) over the channel region.
Re Claim 22, (Original) Kim teaches the transistor of claim 21, wherein the channel region (Fin active pattern; 120; Fig 20; ¶[0033]) comprises a semiconductor fin, a stack of nanowires, or a stack of nanoribbons (Semiconductor fin; ¶[0033]).
Claim Rejections - 35 USC § 103
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo, Chia-Ming et al. (Pub No. US 20170243952 A1) (hereinafter, Kuo) as applied to claim 4 above, and further in view of Kim, Kook-Tae et al. (Pub No. US 20160141381 A1) (hereinafter, Kim).
Re Claim 6, (Original) Kuo does not teach the transistor of claim 4, wherein the third layer is a different material than the second layer.
In the same field of endeavor, Kim teaches the transistor of claim 4, wherein the third layer (First spacer; 151; Fig 4; ¶[0060]) is a different material (Per ¶[0060] may have different carbon concentrations which renders the spacers 151 and 153 materially different) than the second layer (Third spacer; 153; fig 4; ¶[0060]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a third layer which is a different material than the second layer, as taught by Kim, for the transistor of Kuo. One would have been motivated to do this with a reasonable expectation of success because the etch rate during the manufacturing process may be optimized, which depends on the carbon and oxygen concentrations of the inner and outer spacers, as suggested by Kim (¶[0065]).
14. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo, Chia-Ming et al. (Pub No. US 20170243952 A1) (hereinafter, Kuo) as applied to claim 1 above, and further in view of Bedell, Stephen W. et al. (Pub No. US 20100207208 A1) (hereinafter, Bedell).
Re Claim 14, (Original) Kuo does not teach the transistor of claim 1, wherein the channel region comprises semiconductor nanoribbons or nanowires.
In the same field of endeavor, Bedell teaches the transistor of claim 1, wherein the channel region (Nanowires; 32; Figs 10A/10C; ¶[0065]) comprises semiconductor nanoribbons or nanowires (Nanowires; 32; Figs 10A/10C; ¶[0065]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a channel region comprising of semiconductor nanowires, as taught by Bedell, for the transistor of Kuo. One would have been motivated to do this with a reasonable expectation of success because nanowires provide superior electrostatic control of the channel by the gate, due to their ability to occupy minimal space and scaling density, whereas a fin structure may cause more current leakage in comparison, as suggested by Bedell (¶[0002]).
15. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Kook-Tae et al. (Pub No. US 20160141381 A1) (hereinafter, Kim) as applied to claim 21 above, and further in view of Kuo, Chia-Ming et al. (Pub No. US 20170243952 A1) (hereinafter, Kuo).
Re Claim 23, (Currently Amended) Kim does not teach the transistor of claim 21, wherein an etch resistance of the first layer and the second layer is higher than an etch resistance at the midpoint of the third layer.
In the same field of endeavor, Kuo teaches the transistor of claim 21, wherein an etch resistance (Per ¶[0032]) 131 has higher etch resistance than oxygen-based etch process) of the first layer (Spacer film 131a; Fig 8; ¶[0035]) and the second layer (Blocking film; 150; Fig 8; ¶[0035]) is higher than an etch resistance (Per ¶[0033] 132 has poor etch resistance against the oxygen-based etch process in comparison to SiCN) at the midpoint of third layer (Spacer film; 132a; Fig 8; ¶[0035]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an etch resistance of the first surface and the second surface is higher than an etch resistance at the midpoint of the spacer between the first surface and the second surface, as taught by Kuo, for the transistor of Kim. One would have been motivated to do this with a reasonable expectation of success because the resistance difference between the middle and outer spacers provides considerable selectivity in the oxygen-based etch process, particularly during the wet etching process (reactive ion etching) the outer spacers can protect the middle spacer from being over-etched, as suggested by Kuo (¶¶[0033, 0041]).
16. Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo, Chia-Ming et al. (Pub No. US 20170243952 A1) (hereinafter, Kuo), and further in view of Song, Hyun-Seung (Pub No. US 20160020205 A1) (hereinafter, Song).
Re Claim 24, (Currently Amended) Kuo teaches a die which comprises: a channel region (Fin type active pattern; 110; Fig 8; ¶[0030]);
a gate stack (Metal gate structure; 170; Fig 8; ¶[0044]) over the channel region;
a first spacer (Right hand spacer; 130; Fig 8; ¶[0035]) on a first end (Right side) of the gate stack; and
a second spacer (Left hand spacer; 130; Fig 8; ¶[0035]) on a second end (Left side) of the gate stack, wherein the first spacer and the second spacer comprise:
a first layer (Spacer film; 131a; Fig 8; ¶[0035]) adjacent to the gate stack;
a second layer (Blocking film; 150; Fig 8; ¶[0035]) spaced away from the gate stack; and
a bulk layer (Spacer film; 132a; Fig 8; ¶[0035]) between the first layer and the second layer, wherein a dielectric constant (Dielectric constant of SiOCN; ¶[0035]) of the bulk layer is lower (Dielectric constant of SiCN is higher than SiOCN due to the lack of oxygen composition in SiCN) than dielectric constants (Dielectric constant from value of 4 to 6, SiCN; ¶[0035]) of the first layer and the second layer.
wherein the second layer is along an outer sidewall (Blocking film 150 is on outer sidewall of spacer 132; Fig 8) of the bulk layer.
However, Kuo does not teach an electronic system, comprising:
a board;
a package substrate coupled to the board;
a die coupled to the package substrate.
In the same field of endeavor, Song teaches an electronic system, comprising:
a board (Printed Circuit Board; 2310; Fig 8B; ¶[0118]);
a package substrate (Module substrate; 2210; Fig 8A; ¶[0117]) coupled to the board;
a die (Semiconductor module; 2200; Fig 8A; ¶[0117]) coupled to the package substrate.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an electronic system comprising of a board, package substrate coupled to the board, and a die coupled to the package substrate, as taught by Song, for the transistor of Kuo. One would have been motivated to do this with a reasonable expectation of success because the electronic system of Song may be incorporated into a mobile apparatus, such as a mobile phone or a tablet PC, or a portable apparatus such as a portable computer (e.g., a laptop computer), an MPEG-1 Audio Layer 3 (MP3) player, an MP4 player, a navigation system, a solid state disk (SSD), a desktop computer, automobile appliances, or home appliances, as well as a mobile phone or a tablet PC, as suggested by Song (¶[0120]).
Re Claim 25, (Currently Amended) Kuo teaches the electronic device of claim 24, wherein the first surface (Surface of spacer film 131a adjacent to gate; Fig 8; ¶[0035]) and the second surface (Surface of spacer film 131a away from gate; Fig 8; ¶[0035]) have an etch resistance (Per ¶[0032]) 131 has higher etch resistance than oxygen-based etch process) that is greater than an etch resistance (Per ¶[0033] 132 has poor etch resistance against the oxygen-based etch process in comparison to SiCN) of the bulk layer (Spacer film; 132a; Fig 8; ¶[0035]).
Allowable Subject Matter
17. Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The closest prior art Harada, Kazuhiro et al. (Pub No. US 20210040609 A1) (hereinafter, Harada) either singularly or in combination fails to anticipate or render obvious
“The method of claim 15, wherein the flow rate of the oxygen source is non-uniform through iterations of the deposition cycle.”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, Re claim 16, Harada discloses a flow rate of oxygen which is uniform throughout each iteration of the deposition cycle. Furthermore, the related prior art does not disclose an oxygen source having a non-uniform flow rate of the deposition cycle as disclosed in claim 15.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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