DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 3/13/2026, has been entered. The Applicant has amended claims 1 and 9, and canceled claims 23-25. Claims 18-22 were withdrawn previously due to restriction requirement. Accordingly, claims 1-17 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The Applicant has amended claim 1 to state “wherein the second access hole and the first access hole are not laterally intervening between the source region and the drain region in a plan view” which is unclear. In particular, it is unclear what the particular term “not laterally intervening” means. The phrase is not specifically described in the Specification, therefore the term is not clear what “lateral” indicates in regard to “intervening”. For example, is “lateral” limited to structures in the same plane or on the same line, or from another perspective, does “lateral intervening” mean complete shadowing the drain from the source or vice versa? For the purpose of examination, “are not laterally intervening between the source and the drain” will be broadly interpreted as that “do not completely shadow the source and drain from each other”.
The Applicant has amended claim 9 in a similar way by stating “wherein the first extension and the second extension are not laterally intervening between the source region and the drain region in a plan view”, which is again unclear due to same reasons detailed above. For the purpose of examination, “are not laterally intervening between the source and the drain” will be broadly interpreted as that “do not completely shadow the source and drain from each other”.
Claims 2-8 and 10-17 are also rejected, because these claims directly or indirectly depend on either claim 1 or claim 9.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The Applicant has amended claim 1 to include the limitation “the second access hole and the first access hole are not laterally intervening between the source region and the drain region in a plan view” which is not described in sufficient detail to show possession in the original disclosure. The closest support Examiner can identify would be in FIG. 4 which shows the access holes in a way where they are not between the source and drain regions, however there is no corresponding discussion in the specification to indicate that this drawing is to scale or that positioning is specific where one could conclude that this was specifically intended and not merely a convenience or choice in illustrating the figure (see MPEP 2163). To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention.
Similarly, the Applicant has amended claim 9 to include the limitation “the first extension and second extension are not laterally intervening between the source region and the drain region in a plan view”, and similar to claim 1 above, this limitation is not described in sufficient detail to show possession in the original disclosure.
Claims 2-8 and 10-17 are also rejected, because these claims directly or indirectly depend on either claim 1 or claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, and 9-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung (US 2023/0029046 A1).
Regarding claim 1, Chung teaches a transistor (MRAM access transistor 104, Fig. 10A-C, [0059]), comprising:
a source region (epitaxial source/drain regions 208 (the left one, not labeled in figure)), Fig. 10B, [0064]);
a drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B, [0064]);
a first semiconductor channel (channel layer 204A, Fig. 10B (see Fig. 10C for the label), [0060]) between the source region (epitaxial source/drain regions 208 (the left one, not labeled in figure), Fig. 10B) and the drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B);
a second semiconductor channel (channel layer 204B, Fig. 10B (see Fig. 10C for the label), [0060]) between the source region (epitaxial source/drain regions 208 (the left one), Fig. 10B) and the drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B) over the first semiconductor channel (channel layer 204A, Fig. 10B (see Fig. 10C for the label);
an insulator (interlayer dielectric (ILD) layer 242, Figs. 10B-C, [0066]) around the source region (epitaxial source/drain regions 208 (the left one), Fig. 10B), the drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B), the first semiconductor channel (channel layer 204A, Fig. 10B-C), and the second semiconductor channel (channel layer 204B, Fig. 10B-C);
a first access hole (the region filled with gate fill metal 220, Fig. 10C (see first hole in Illustrative Fig. 1, which is an annotated version of Figs. 10A and 10C) in the insulator adjacent (interlayer dielectric (ILD) layer 242, Illustrative Fig. 1) to a first edge (first edge, Illustrative Fig. 1) of the first semiconductor channel (channel layer 204A, Illustrative Fig. 1); and
a second access hole (second access hole, Illustrative Fig. 1) in the insulator (interlayer dielectric (ILD) layer 242, Illustrative Fig. 1) adjacent to a second edge (second edge, Illustrative Fig. 1) of the first semiconductor channel (channel layer 204A, Illustrative Fig. 1), wherein the second access hole (second access hole, Illustrative Fig. 1) and the first access hole (first access hole, Illustrative Fig. 1) are not laterally intervening between the source region (epitaxial source/drain regions 208 (the left one), Fig. 10B; corresponding a region labeled S in Illustrative Fig. 1) and the drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B; corresponding a region labeled D in Illustrative Fig. 1) in a plan view (see the lateral line X’-X between the source S and drain D in Illustrative Fig. 1 which corresponds to cross-section in Fig. 10B and is not laterally intervened by the first access hole and the second access hole).
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Regarding claim 2, Chung teaches the transistor of claim 1, wherein the first access hole (first access hole, Illustrative Fig. 1) and the second access hole (second access hole, Illustrative Fig. 1) are filled with a dielectric liner (high-k dielectric layer 216 for the first access hole and high-k dielectric layer 224 for the second access hole, Illustrative Fig. 1, [0063]) and a conductive material (gate fill metal 220 for the first access hole and gate fill metal 228 the second access hole, Illustrative Fig. 1, [0063]).
Regarding claim 3, Chung teaches the transistor of claim 1, wherein the first access hole (first access hole, Illustrative Fig. 1) is offset from the second access hole (second access hole, Illustrative Fig. 1: first access hole and the second access hole are offset from each other in the Y direction).
Regarding claim 4, Chung teaches the transistor structure of claim 3, wherein a sidewall (see first sidewall as labeled in Illustrative Fig. 1) of the first access hole (first access hole, Illustrative Fig. 1) is offset from a sidewall (see second sidewall as labeled in Illustrative fig. 1) of the second access hole (second access hole, Illustrative Fig. 1) by 1nm or more (Illustrative Fig. 1, the first and second sidewalls are offset more than the thickness of the semiconductor layers, which are about 5nm to about 50 nm thick ([0081])).
Regarding claim 5, Chung teaches the transistor of claim 1, wherein a shape (Illustrative Fig. 1) of the first access hole (first access hole, Illustrative Fig. 1) is different from a shape of the second access hole (second access hole, Illustrative Fig. 1: first access hole is wider in the Y direction).
Regarding claim 6, teaches the transistor of claim 1, wherein the first semiconductor channel (channel layer 204A, Fig. 10C) and the second semiconductor channel (channel layer 204B, Fig. 10C) are nanoribbon channels or nanowire ([0060]: “… the channel layers 204A-C are nanosheets, nanowires, nanorings, nanoslabs, or other structures having nano-scale size (e.g., a few nanometers).”) channels.
Regarding claim 9, Chung teaches a transistor (MRAM access transistor 104, Fig. 10A-C, [0059]), comprising:
a source region (epitaxial source/drain regions 208 (the left one, not labeled in figure)), Fig. 10B, [0064]);
a drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B, [0064]);
a semiconductor channel (channel layer 204B, Fig. 10B-C, [0060]) between the source region (epitaxial source/drain regions 208 (the left one, not labeled in figure), Fig. 10B) and the drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B); and
a gate stack (independent gate terminal G1 and G2, Fig. 10C, [0063]) over the semiconductor channel (channel layer 204B, Fig. 10B-C), wherein the gate stack (independent gate terminal G1 and G2, Fig. 10C) comprises a first extension (see first extension in Illustrative Fig. 2, which is an annotated version of Chung’s Figs. 10A and 10C) along a first edge (left edge of the channel layer 204B, labeled as first edge in Illustrative Fig. 2) of the semiconductor channel (channel layer 204B, Illustrative Fig. 2) and a second extension (second extension, Illustrative Fig. 2) along a second edge (right edge of the channel layer 204B, labeled second edge in Illustrative Fig. 2) of the semiconductor channel (channel layer 204B, Illustrative Fig. 2), wherein the first extension (first extension, Illustrative Fig. 2) and the second extension (second extension, Illustrative Fig. 2) are not laterally intervening between the source region (epitaxial source/drain regions 208 (the left one), Fig. 10B; corresponding a region labeled S in Illustrative Fig. 2) and the drain region (epitaxial source/drain regions 208 (the right one), Fig. 10B; corresponding a region labeled D in Illustrative Fig. 1) in a plan view (see the lateral line X’-X between the source S and drain D in Illustrative Fig. 2 which corresponds to cross-section in Fig. 10B and is not laterally intervened by the first extension and the second extension).
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Regarding claim 10, Chung teaches the transistor of claim 9, wherein the first extension (first extension, Illustrative Fig. 2) is offset from the second extension (second extension, Illustrative Fig. 2: first extension and second extension are offset in the Y direction (up-down) direction in 10A).
Regarding claim 11, Chung teaches the transistor of claim 10, wherein the first extension (first extension, Illustrative Fig. 2) is offset from the second extension (second extension, Illustrative Fig. 2) by 1nm or more (the first and second extensions are offset more than the thickness of the semiconductor layer 204B, which is about 5nm to about 50 nm thick ([0081])).
Regarding claim 12, Chung teaches the transistor of claim 9, wherein a shape of the first extension (first extension, Illustrative Fig. 2) is different than a shape of the second extension (second extension, Illustrative Fig. 2).
Regarding claim 13, Chung teaches the transistor of claim 9, wherein the gate stack (independent gate terminal G1 and G2, Fig. 10C) comprises:
a dielectric liner (interfacial layer 222, Fig. 10C, [0104]: silicon oxide); and
a metal (gate fill metal 220 and gate fill metal 228, Fig. 10B, [0105]: “the gate fill metal 228 has a same metal as the gate fill metal 220.”) over the dielectric liner (interfacial layer 222, Fig. 10B, [0063]).
Regarding claim 14, Chung teaches the transistor of claim 13, wherein the first extension (first extension, Illustrative Fig. 2) and the second extension (first extension, Illustrative Fig. 2) are lined by the dielectric liner (interfacial layer 222, Illustrative Fig. 2) and are filled with the metal (metal composition of gate fill metal 220 and gate fill metal 228, Illustrative Fig. 2).
Regarding claim 15, Chung teaches the transistor of claim 9, wherein the semiconductor channel (channel layer 204B, Illustrative Fig. 2) is a nanoribbon channel or a nanowire ([0060]: “… the channel layers 204A-C are nanosheets, nanowires, nanorings, nanoslabs, or other structures having nano-scale size (e.g., a few nanometers).”) channel.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2023/0029046 A1) as applied to claims 1-6 and 9-15 above, and further in view of Chen (US 2016/0141427 A1).
Regarding claim 7, while Chung teaches the transistor of claim 6,
Chung does not teach that the first semiconductor channel and the second semiconductor channel comprises a transition metal dichalcogenide (TMD), wherein the TMD takes the form of MX2, where M is transition metal atom including molybdenum or tungsten, and wherein X is a chalcogen atom including sulfur, selenium, or tellurium.
Chen, on the other hand, teaches a transistor (2D transition metal dichalcogenide (TMD) FET, Fig. 16, [0039]) with multiple semiconductor channels (TMD layers 30A-C, Fig. 16, [0028]) over each other (Fig. 16), wherein the first semiconductor channel (TMD layer 30A, Fig. 16, [0019]) and the second semiconductor channel (TMD layer 30B, Fig. 16, [0028]) comprises a transition metal dichalcogenide (TMD) ([0019]), wherein the TMD takes the form of MX2 ([0019]), where M is transition metal atom ([0019]) including molybdenum or tungsten ([0019]: “The transition metal may include tungsten (W), molybdenum (Mo), Ti, or the like.”), and wherein X is a chalcogen atom including sulfur, selenium, or tellurium ([0019]: “The group VIA element may be sulfur (S), selenium (Se), tellurium (Te), or the like.”).
It is known in the field of semiconductor devices that stacked channels formed from transition metal dichalcogenides in transistors reduces the device size without increasing the leakage current, as evidenced by Li (US 2020/0235098 A1, [0007]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the first and second semiconductor channels in the transistor of Chung from transition metal dichalcogenides, as taught by Chen, to be able reduce the device size without compromising the leakage current.
Regarding claim 16, while Chung teaches the transistor of claim 15, wherein
Chung does not teach that the semiconductor channel comprises a transition metal dichalcogenide (TMD).
Chen, on the other hand, teaches a transistor (2D transition metal dichalcogenide (TMD) FET, Fig. 16, [0039]) wherein the semiconductor channel (TMD layers 30B, Fig. 16, [0028]) comprises a transition metal dichalcogenide (TMD) ([0019]).
It is known in the field of semiconductor devices that channels formed from transition metal dichalcogenides in transistors reduces the device size without increasing the leakage current, as evidenced by Li (US 2020/0235098 A1, [0007]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the semiconductor channel in the transistor of Chung from transition metal dichalcogenides, as taught by Chen, to be able reduce the device size without compromising the leakage current.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2023/0029046 A1) as applied to claims 1-6 and 9-15 above, and further in view of Zhao (CN 109309004 A).
Regarding claim 8, Chung teaches the transistor of claim 1, wherein (during manufacturing of the transistor) the first sacrificial layer (second sacrificial layer SL2 (304), Fig. 16B, [0075]) is etch selective to the second sacrificial layer (first sacrificial layer SL1 (302), Fig. 16B, [0075]; [0095]: “the etching step selectively etches the first sacrificial layers 302 at a faster etch rate than it etches the second sacrificial layers 304 and the channel layers 204.”)
Chung is silent about that a remnant of a first sacrificial layer is between the first semiconductor channel and the second semiconductor channel, and wherein a remnant of a second sacrificial layer is above the second semiconductor channel.
Zhao, on the other hand, teaches a method for manufacturing a nanowire transistor (Fig. 19, [0129]) wherein the sacrificial layer (sacrificial layer 207, Fig. 15, [0120]) under the nanowire channel (nanowire 209, Fig. 15, [0120]) is removed by a selective etching process ([0120]). Zhao, further discloses that it is permissible for a portion of the sacrificial layer 207 to remain on the surface of the nanowire 209, which would minimize the damage to the nanowire during the etching process ([0120]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to slightly underetch the sacrificial layers in the manufacturing of the transistor of Chung (see Figs. 16B-17B for etching first sacrificial layer SL1, and Figs. 19B-20B for etching the second sacrificial layer SL2) to minimize the damage to the first and second semiconductor channel layers, as taught by Zhao.
Thus, the combination of Chung and Zhao leads to a transistor wherein a remnant of a first sacrificial layer is between the first semiconductor channel and the second semiconductor channel, and wherein a remnant of a second sacrificial layer is above the second semiconductor channel.
Regarding claim 17, Chung teaches the transistor of claim 9, wherein (during manufacturing of the transistor)
the first sacrificial layer (first sacrificial layer SL1 (302), Fig. 16B, [0075]) is etch selective to the second sacrificial layer (second sacrificial layer SL2 (304), Fig. 16B, [0075]; [0095]: “the etching step selectively etches the first sacrificial layers 302 at a faster etch rate than it etches the second sacrificial layers 304 and the channel layers 204.”)
Chung does not teach that the transistor further comprises
a first sacrificial layer remnant above the semiconductor channel; and
a second sacrificial layer remnant below the semiconductor channel, wherein the first sacrificial layer remnant is etch selective to the second sacrificial layer remnant.
Zhao, on the other hand, teaches a method for manufacturing a nanowire transistor (Fig. 19, [0129]) wherein the sacrificial layer (sacrificial layer 207, Fig. 15, [0120]) under the nanowire channel (nanowire 209, Fig. 15, [0120]) is removed by a selective etching process ([0120]). Zhao, further discloses that it is permissible for a portion of the sacrificial layer 207 to remain on the surface of the nanowire 209, which would minimize the damage to the nanowire during the etching process ([0120]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to slightly underetch the sacrificial layers in the manufacturing of the transistor of Chung (see Figs. 16B-17B for etching first sacrificial layer SL1, and Figs. 19B-20B for etching the second sacrificial layer SL2) to minimize the damage to the semiconductor channel layer, as taught by Zhao.
Thus, the combination of Chung and Zhao leads to a transistor further comprising
a first sacrificial layer remnant above the semiconductor channel; and
a second sacrificial layer remnant below the semiconductor channel, wherein the first sacrificial layer remnant is etch selective to the second sacrificial layer remnant.
Response to Arguments
It has been acknowledged that the applicant amended claims 1 and 9, and canceled claims 23-25 per response dated on 3/13/2025. Applicant's arguments with respect to claims have been fully considered.
Thus, Chung does not disclose a transistor including a source region, a drain region, an insulator, a first access hole in the insulator, and a second access hole in the insulator, where the second access hole and the first access hole are not laterally intervening between the source region and the drain region in a plan view, as is required by Applicant's claims. As such, with respect to amended independent claims 1 and 9, Chung fails to disclose each and every feature of Applicant's claims.
The Examiner respectfully disagrees with the Applicant. As noted above in the 112 rejection for claim 1, the limitation in question is interpreted as the access holes not shadowing the source and drain regions. Chung shows the access holes located coplanar to the source and drain regions but there is a clear line between the source and drain regions that does not go through the first or second access hole (see annotated FIG. 1 above). Similarly for the first and second extension as per claim 9 (see annotated FIG. 2 above).
For the purpose of compact prosecution, the Examiner notes, however, that clarifying the spatial relation between the first access hole/first extension and the second access hole/second extension further as described in the disclosure, such along the lateral direction from the drain to the source or along another direction, might render independent claims 1 and 9 inventive and non-obvious. Alternatively, the Applicant may consider clarifying the offset between the first access hole/first extension and the second access hole/second extension introduced in claims 3 and 10.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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