DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Responses to Amendments and Arguments
The amendments filed 4/6/2026 have been entered. Claims 1, 9, and 17 are amended. Claims 1-20 remain pending in the application.
Applicant's argument and amendments filed 4/6/2026 with respect to
the rejection of claim 1-20 under 35 U.S.C. 101 have been fully considered but are not persuasive.
On pages 7-10 of Applicant’s response, Applicant alleges that “… Amended claim 1 does not recite any formula, equation, coefficient, lookup table, or other mathematical operation. …The amended claim also is not reasonably characterized as a mental process. … The claim therefore is not fairly reduced to a mental evaluation divorced from the claimed hardware context. … amended claim I integrates any such concept into a practical application. … The claim expressly requires that the power-performance state be changed by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to a detected change in the estimated power delivery network loss. Thus, amended claim I no longer recites an unspecified "apply it" result. … Amended claim I also recites a specifically defined physical quantity. The estimated loss is not a generic "power loss," but rather power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits. … This is a technological use of the estimate in the operation of the computing system itself, not an abstract use of information. … Amended claim I does exactly that by using the estimated delivery path loss to control physical operation of a circuit through frequency and/or voltage changes. That is not insignificant extra-solution activity. It is the claimed technological application. … amended claim 1 integrates any such exception into a practical application under Step 2A, Prong Two. … amended claim 1 also recites significantly more than any such exception. … These limitations, considered in combination, amount to more than merely using a generic computer as a tool to perform a calculation. Rather, they define a particular technological control arrangement for managing power-delivery loss in a computing system and therefore amount to significantly more than any alleged judicial exception under Step 2B.
Examiner respectfully disagrees.
Note that “generate, based on the monitored operating conditions, an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits” may encompass mathematical calculations by using mathematical algorithm (model 430) which is represented as mathematical equation/function or inferring the power loss using mathematical algorithm (model 430), where the excluding of the consumed power is indicative of a mathematical calculation (Para 0037-0039, especially paragraph 0037. Further, note that “an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits” itself is not a meaningful limitation to improvements to the functioning of the circuits, but just indicative of a field of use to apply under the user’s preference/interest. The feature related to “change a power-performance state of one of the plurality of circuits …” is not a meaningful limitation to improvements to the functioning of the circuits, but just a “apply it” element of the circuits to perform an insignificant post-solution activity for merely performing a generic computer function of a generic computer component without any specific or tangible feature/operation/act as to what the power-performance state is indicative of and/or how/what a specific or tangible element/act may be changed for power-performance state with what tangible/specific structure/component the changing process is performed. (See MPEP 2106.05(f) and 2106.05(g)). Further, the limitation of “change a power-performance state of one of the plurality of circuits by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to a detected change in the estimated power delivery network loss” is an insignificant post-solution activity to perform the abstract idea based on the mathematical calculations using mathematical algorithm (model 430), and this limitation is well-understood, routine, conventional activities previously known to the industry, as the PARK reference (US 20160179164 A1) and Eckert reference (US 20150370311 A1) teach modifying a clock frequency or a voltage level and adjusting a power limit (see at least paragraphs 0005, and 0023-0024, 0046 in PARK, and paragraph 0016 in Eckert). See MPEP 2106.05(d).
Note that the claims do not present a meaningful limitation to improvements to the functioning in a power management system or process without any specific or tangible feature/operation/act as to how and/or with, for example, what factors/values/parameter/frequency/characteristic the generation/estimation of the power loss is performed and/or how/what a specific or tangible element/act may be involved with the generation/estimation of the power loss, but are indicative of mathematical calculations (or algorithm) to calculate or infer the power loss using mathematical algorithm (model 430). (See at least at paragraphs 0037-0039 of the instant application). The system management circuit and the plurality of circuits are additional elements recited at a high-level of generality to perform general computer functions of a generic computer component without improvements to the functioning and/or specific structure/configuration of their circuits or to other technology or technical field. (MPEP 2106.05(a)). Therefore, this judicial exception is abstract ideal itself and not integrated into a practical application, and also has no significant more beyond the abstract idea. (See the details in the modified action set forth below).
Applicant's argument and amendments filed 4/6/2026 with respect to
the rejection of claim 1-20 under 35 U.S.C. 103 have been fully considered but not persuasive.
On pages 10 -13 of Applicant’s response, Applicant alleges that amended claim I recites limitations not taught or suggested by the applied combination. For example, claim I does not merely recite an estimated "power loss." Rather, amended claim I requires generating an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits. Amended claim I further requires changing a power-performance state of one of the plurality of circuits by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to a detected change in the estimated power delivery network loss. The applied combination does not teach or suggest these amended limitations. … Park paragraph [0006] does not disclose the amended claimed delivery-path loss. … In contrast, amended claim 1 requires an estimated loss in a power delivery path between a power supply and the plurality of circuits and expressly requires that the estimated loss exclude power consumed by the plurality of circuits.
Examiner respectfully disagrees.
Note that, under the broadest reasonable interpretation, the claimed feature of “change a power-performance state of one of the plurality of circuits of the computing system by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to the estimated power loss” is indicative of a process to adjust/allocate a state/amount/threshold related to a power management by modifying/adjusting a clock frequency, a voltage level and/or a power limit for avoiding power-performance state (degradation and/or outright device failure) based on the monitored power level/voltage/current. Further, note that, under the broadest reasonable interpretation, the “estimated power loss” is indicative of “estimated power leakage” in view of a general meaning in the art and a leakage power level may result in a power loss in a power system. Under this interpretation, at least paragraphs 0005-0006 and 0024 in Park teaches estimating leakage power level based on the monitored operating conditions such as temperature and voltage levels. At least paragraphs 0023-0024 of Park teach modifying a clock frequency or a voltage level and adjusting a power limit which is equivalent to and applied to the claimed feature related to “by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to a detected change in the estimated power delivery network loss” (Para 0023, “modify a clock frequency or voltage level to one or more processing components such that an overall current demand is adjusted and the peak current level”; Para 0024, “…dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change”; Para 0046, “The amount of power provided to the power domain for processing workloads is dictated by the dynamic power budget threshold such that, if the threshold is exceeded, a DCVS module 26 may be triggered to adjust down frequency settings and/or voltage settings of one or more function blocks”).
Note that, under the broadest reasonable interpretation, "a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits" itself is not critical to be distinctly result-effective features but merely indicative of a place or parts in circuits where the estimated power loss is detected/generated, which is indicative of a field of use that the claimed invention may apply as per the user interest/preference. If the “a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits” itself is believed to be a key aspect for generating the estimated power delivery network loss and/or changing the power-performance state, as Applicant alleges, at a minimum the claims describe some specific features, structure and/or actions, for example, how and/or with what the estimated power delivery network loss is detected from the path and the power consumed by the circuits is excluding. Respectfully note that MPEP § 2145(VI) discusses arguments about limitations that are not claimed. MPEP § 2145(VI) states that “Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims”. In response to applicant’s argument that the references fail to show certain features of applicant’s invention, the features upon which applicant relies (i.e., “attribute”) to determine the “attribute”, which is indicative of “a physical or chemical characteristic of a structure which may be a size, shape, complexity, concentration, and chemical composition”, are not recited in the rejected claim(s) with sufficiently definite structure or acts. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). (FP 7.37.08). (See the details in the modified action set forth below).
On page 13 of Applicant’s response, Applicant further alleges that claim 4 further recites … the cited Park disclosures do not identify decreased power losses associated with operation of a memory subsystem as the basis for increasing a power-performance state of a computation circuit. Park paragraph [0006] addresses an estimated leakage power level calculated from monitored temperature and voltage levels, and paragraphs [0005], [0024], and [0025] address dynamic power thresholds, workloads, and power supply capability. Those disclosures do not teach the specific relationship recited in claim 4, namely using decreased power losses associated with operation of a memory subsystem as the basis for increasing the power-performance state of a computation circuit.
Examiner respectfully disagrees.
Note that, under the broadest reasonable interpretation, the claimed feature of “detection of decreased power losses associated with operation of a memory subsystem” is indicative of detecting a power loss which is equivalent to an operation for monitoring a power loss (voltage levels) is monitored.
On pages 13-14 of Applicant’s response, Applicant further alleges that claim 7 recites … increase power consumption used by at least a portion of the system without reducing power consumed elsewhere in the system and without increasing estimated power consumption, in response to detection of a condition. The applied combination does not teach or suggest that limitation.
Applicant's argument with respect to the rejection of claim 7 under 35 U.S.C. 103 have been fully considered and persuasive. Therefore, the rejection of claim 7 under 35 U.S.C. 103 is withdrawn.
On page 14 of Applicant’s response, Applicant further alleges that claim 8 further recites that the recited condition is a detected decrease in the estimated power delivery network loss. The applied combination does not teach or suggest this limitation.
Examiner respectfully disagrees.
Note that, under the broadest reasonable interpretation, “the condition is a detected decrease in the estimated power delivery network loss” is indicative of a monitored/detected power loss which is taught by condition related to the monitored voltage levels and power supply capability change detected/estimated at least at paragraphs 0005-0006 and 0024.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The current 35 USC 101 analysis is based on the current guidance (Federal Register vol. 79, No. 241. pp. 74618-74633). The analysis follows several steps. Step 1 determines whether the claim belongs to a valid statutory class. Step 2A prong 1 identifies whether an abstract idea is claimed. Step 2A prong 2 determines whether any abstract idea is integrated into a practical application. If the abstract idea is integrated into a practical application the claim is patent eligible under 35 USC 101. Last, step 2B determines whether the claims contain something significantly more than the abstract idea. In most cases the existence of a practical application predicates the existence of an additional element that is significantly more.
The 35 USC 101 analysis between each element of claims and its combination is presented in the table below
Claim number and elements
Judicial exception (Step 2A Prong one)
Practical application (Step 2A Prong two)/ Significantly more (Step 2B)
Claim 1
Step 1: Yes, statutory class
Step 2A Prong two: No / Step 2B: No
A system comprising:
Step2A Prong one: Yes
a system management circuit configured to:
monitor one or more operating conditions of a plurality of circuits of the computing system;
abstract idea
“a system management circuit” and “a plurality of circuits” are high level of generalities to perform a generic function of a general computer.
“monitor ~” is insignificant pre-solution activity to collect the operating condition.
generate, based on the monitored operating conditions, an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits;
mental process or mathematical concept
“generate … an estimated power delivery power loss …” is a math process which is performed using mathematical algorithm such as model 430 in Fig. 4. (see para 0037).
change a power-performance state of one of the plurality of circuits by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit,
responsive to a detected change in the estimated power delivery network loss.
“change a power-performance state~” is insignificant extra-solution activity based on the result of mathematical calculation. (para 0037).
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Claims 1-20 are directed to an abstract idea. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception as addressed below and presented in the above table.
Step 2A: Prong One
Regarding Claim 1, the limitations recited in Claim 1, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mathematical calculations and/or the mind, as presented in the above table. Nothing in the claim elements precludes the step from practically being performed in the mind and/or the mathematical calculations. For example, “generate, based on the monitored operating conditions, an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits” in the context of this claim may encompass mathematical calculations by using mathematical algorithm (model 430) which is represented as mathematical equation/function or inferring the power loss using mathematical algorithm (model 430), where the excluding of the consumed power is indicative of a mathematical calculation (Para 0037-0039, especially paragraph 0037, “model 430 includes circuitry configured to perform a calculation representative of relationship between power loss and current based on parameters 420. … the power loss is represented using a simplified model expressed by the equation Pioss = c2 * Iout2 + cl* Iout+co … Based on the estimated power losses, the system management circuit 410 may change power-performance states of one or more circuits of the system. For example, in one implementation, circuits (e.g., computation circuits) are configured to operate at multiple power-performance states”).
Step 2A: Prong Two
This judicial exception is abstract ideal itself and not integrated into a practical application. In particular, the specification details use of processing circuitry of mathematical algorithm (model 430) to perform mathematical calculations of “generate, based on the monitored operating conditions, an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits”. (See paragraph 0037-0039). Note that “an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits” itself is not a meaningful limitation to improvements to the functioning of the circuits, but just indicative of a field of use to apply under the user’s preference/interest.
The system management circuit and the plurality of circuits are high-level of generalities recited as a generic computer component to perform mathematical calculations additional elements recited at a high-level of generality to perform general computer functions of a generic computer component without improvements to the functioning and/or specific structure/configuration of their circuits or to other technology or technical field. (MPEP 2106.05(a)). The limitations of “monitor one or more operating conditions of a plurality of circuits of the computing system” and “change a power-performance state of one of the plurality of circuits by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to a detected change in the estimated power delivery network loss” are insignificant extra-solution activities recited to collect routine data (i.e. operating conditions) and perform the abstract idea based on the mathematical calculations using mathematical algorithm (model 430). See MPEP 2106.05(g). Further, the limitation of “change a power-performance state of one of the plurality of circuits by changing at least one of: …” is not a meaningful limitation to improvements to the functioning of the circuits, but just a “apply it” element of the circuits to perform an insignificant post-solution activity for merely performing a generic computer function of a generic computer component without any specific or tangible feature/operation/act as to what the power-performance state is indicative of and/or how/what a specific or tangible element/act may be changed for power-performance state with what tangible/specific structure/component the changing process is performed. There is no showing of integration into a practical application such as an improvement to the functioning of a computer, or to any other technology or technical field, or use of a particular machine.
Step 2B:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The limitation of “monitor one or more operating conditions of a plurality of circuits of the computing system” is insignificant pre-solution activities to collect routine data (i.e. operating conditions) with which the mathematical process is perform using mathematical algorithm (model 430). The limitation of “change a power-performance state of one of the plurality of circuits by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to a detected change in the estimated power delivery network loss” is insignificant post-solution activities to perform the abstract idea based on the mathematical calculations using mathematical algorithm (model 430), and this limitation is well-understood, routine, conventional activities previously known to the industry, as the PARK reference (US 20160179164 A1) and Eckert reference (US 20150370311 A1) teach (see at least paragraphs 0005 and 0024 in PARK, and paragraph 0016). See MPEP 2106.05(d). As discussed above, with respect to integration of the abstract idea into a practical application, using the processing circuitry of mathematical algorithm to perform “monitor one or more operating conditions of a plurality of circuits of the computing system”, “generate, based on the monitored operating conditions, an estimated power delivery network loss comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits” and “change a power-performance state of one of the plurality of circuits by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to a detected change in the estimated power delivery network loss” amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept cannot provide statutory eligibility. Claim 1 is not patent eligible.
Regarding Claims 2-8, the limitations are further directed to an abstract idea, as described in claim 1. The additional elements of the second circuit recited in claim 3, and the graphics processing circuit and the computation circuit in claim 4 are high-level of generalities recited as a generic computer component to perform mathematical calculations. For the reasons described above with respect to Claim 1, the judicial exceptions are not meaningfully integrated into a practical application, or amount to significantly more than the abstract idea.
Regarding Claim 9, it is a method type claim having similar limitations as of claim 1 above. Therefore, it is rejected under the same rationale as of claim 1 above.
Regarding Claims 10-16, the limitations are further directed to an abstract idea, as described in claim 9. For the reasons described above with respect to Claims 2-8, the judicial exceptions are not meaningfully integrated into a practical application, or amount to significantly more than the abstract idea.
Regarding Claim 17, it is a system type claim having similar limitations as of claim 1 above. Therefore, it is rejected under the same rationale as of claim 1 above. The plurality of circuits, the central processing circuit, the graphics processing circuit, the memory subsystem, and the system management circuit are high-level of generalities recited as a generic computer component to perform mathematical calculations additional elements recited at a high-level of generality to perform general computer functions of a generic computer component without improvements to the functioning and/or specific structure/configuration of their circuits or to other technology or technical field. (MPEP 2106.05(a)).
Regarding Claims 18-20, the limitations are further directed to an abstract idea, as described in claim 17. For the reasons described above with respect to claims 2-8 the judicial exceptions are not meaningfully integrated into a practical application, or amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US 20160179164 A1, hereinafter referred to as “PARK”, cited in IDS dated 03/04/2024) in view of Eckert et al. (US 20150370311 A1, hereinafter referred to as “Eckert”).
Regarding Claim 1, PARK teaches a system (Fig. 3; a system 99A), comprising:
a system management circuit (Fig. 3; a power management integrated circuit (“PMIC”) 180) configured to:
monitor one or more operating conditions (temperatures, voltage level) of a plurality of circuits of the computing system (Para 0006, “monitors the operating temperatures of the one or more processing components, as well as voltage levels supplied to the one or more processing components”);
generate, based on the monitored operating conditions, an estimated power delivery network loss (an estimated leakage power level) comprising power lost in a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits (Para 0006, “With the monitored operating temperatures and active voltage levels, the method may then calculate an optimum level for the peak dynamic power threshold based on an estimated leakage power level calculated from the monitored temperature and voltage levels”; Note that, under the broadest reasonable interpretation, the “estimated power loss” is indicative of “estimated leakage” in view of a general meaning in the art and a leakage power level may result in a power loss in a power system.); and
change a power-performance state of one (Para 0006, the one or more processing components; Para 0025, a system on a chip (“SoC”)) of the plurality of circuits (Para 0005-0006; Para 0024, “dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change. In doing so, a PDP solution maximizes the amount of power allocated for workload processing while ensuring that the total power consumed does not exceed the power supply capacity”) by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, (Para 0023, “modify a clock frequency or voltage level to one or more processing components such that an overall current demand is adjusted and the peak current level”; Para 0024, “…dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change”; Para 0046, “The amount of power provided to the power domain for processing workloads is dictated by the dynamic power budget threshold such that, if the threshold is exceeded, a DCVS module 26 may be triggered to adjust down frequency settings and/or voltage settings of one or more function blocks”)responsive to a detected change in the estimated power delivery network loss (Para 0024, “…dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change”).
Note that, under the broadest reasonable interpretation, the claimed feature of “change a power-performance state of one of the plurality of circuits of the computing system by changing at least one of: (i) a clock frequency of the one circuit; and (ii) an operating voltage of the one circuit, responsive to the estimated power loss” is indicative of a process to adjust/allocate a state/amount/threshold related to a power management by modifying/adjusting a clock frequency, a voltage level and/or a power limit for avoiding power-performance state (degradation and/or outright device failure) based on the monitored power level/voltage/current. Under this interpretation, “change a power-performance state of one of the plurality of circuits” is taught by an operation to allocate a maximum amount (i.e., changing a power-performance state) of available power supply to dynamic power consumption for processing workloads or adjust the peak dynamic power limit and/or the operating frequency limit at least in paragraphs 0005 and 0024 of PARK, and “responsive to the estimated power loss” is taught by “based on an estimated leakage power level calculated from the monitored temperature and voltage levels associated with the one or more processing components” in paragraph 0006 of PARK.
Even though Park fails to explicitly disclose “change a power-performance state of the plurality of circuits”, Eckert teaches change a power-performance state of the plurality of circuits … (Para 0016, “The power management state of the component can be changed from the current power management state to a different power management state if the prospective performance and power gains exceed the prospective losses incurred by transitioning into the different power management state”).
Park and Eckert are both considered to be analogous to the claimed invention because they are in the same field of a power management and power management states of a component. Note that, under the broadest reasonable interpretation, "a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits" itself is not critical to be distinctly result-effective features but merely indicative of a place or parts in circuits where the estimated power loss is detected/generated, which is indicative of a field of use that the claimed invention may apply as per the user interest/preference. If the “a power delivery path between a power supply and the plurality of circuits and excluding power consumed by the plurality of circuits” itself is believed to be a key aspect for generating the estimated power delivery network loss and/or changing the power-performance state, as Applicant alleges, at a minimum the claims describe some specific features, structure and/or actions, for example, how and/or with what the estimated power delivery network loss is detected from the path and the power consumed by the circuits is excluding. Respectfully note that MPEP § 2145(VI) discusses arguments about limitations that are not claimed. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate the teachings of Eckert by providing operations for changing a power management state when a power loss/change in the power network/ a component is detected, taught by Eckert at least at paragraph 0016.
Regarding Claim 2, PARK teaches wherein the system management circuit is configured to estimate power consumption of each of the plurality of circuits (Para 0041, “As such the PMIC 180 may include a power supply capability estimator 181 that works with the monitor module 114 (not shown) or includes its own monitor module to monitor the factors and estimate an actual power supply level to the power domain based on the factor readings.”; Para 0005-0006, “systems for dynamically adjusting a peak dynamic power threshold are disclosed. Advantageously, embodiments of the solution for peak dynamic power management optimize a peak dynamic power threshold based on estimations of real-time leakage current levels …. method for managing power consumption in a power domain of a portable computing device (“PCD”) begins by setting a peak dynamic power threshold …. calculate an optimum level for the peak dynamic power threshold based on an estimated leakage power level”).
Regarding Claim 3, PARK teaches wherein the system management circuit is configured to increase a power-performance state of a second circuit (Para 0006, the one or more processing components; Para 0025, a system on a chip (“SoC”)) of the plurality of circuits (Para 0005-0006; Para 0024-0025, “dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change. In doing so, a PDP solution maximizes the amount of power allocated for workload processing while ensuring that the total power consumed does not exceed the power supply capacity … a total current consumption by a system on a chip (“SoC”) resulting from a leakage current consumption and a dynamic current consumption. … the dynamic power is a function of the workload(s) being processed by the function blocks. As a workload for a given function block increases, the amount of dynamic current consumed by the functional block must also increase. Similarly, as a workload decreases, so does the dynamic power being consumed by the function block that is processing the workload”), in response to detection of decrease in the estimated power delivery network loss (Para 0006, “the monitored temperature and voltage levels associated with the one or more processing components”).
Note that, under the broadest reasonable interpretation, “increase a power-performance state of a second circuit” is indicative of an operation of adjusting the peak dynamic power limit and/or the operating frequency limit, taught by in paragraphs 0005-0006 and 0024-0025 of PARK,
Regarding Claim 4, PARK teaches wherein the computing system is a graphics processing circuit (Fig. 3, 180; Fig. 7, the digital signal processor 110) and the system management circuit is configured increase a power- performance state of a computation circuit (Para 0005-0006; Para 0024-0025, “dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change. In doing so, a PDP solution maximizes the amount of power allocated for workload processing while ensuring that the total power consumed does not exceed the power supply capacity … a total current consumption by a system on a chip (“SoC”) resulting from a leakage current consumption and a dynamic current consumption. … the dynamic power is a function of the workload(s) being processed by the function blocks. As a workload for a given function block increases, the amount of dynamic current consumed by the functional block must also increase. Similarly, as a workload decreases, so does the dynamic power being consumed by the function block that is processing the workload.”), in response to detection of decreased power losses associated with operation of a memory subsystem (Para 0006, “the monitored temperature and voltage levels associated with the one or more processing components”).
Note that, under the broadest reasonable interpretation, the claimed feature of “detection of decreased power losses associated with operation of a memory subsystem” is indicative of detecting a power loss which is equivalent to an operation for monitoring a power loss (voltage levels) is monitored.
Regarding Claim 5, PARK teaches wherein the system management circuit is configured to estimate power consumption of the computing system based on a state (estimations of real-time leakage current levels) of the computing system,
wherein the state is based in part on the one or more operating conditions including one or more of an amount of current being drawn, an operating frequency, and operating temperature (Para 0041, “As such the PMIC 180 may include a power supply capability estimator 181 that works with the monitor module 114 (not shown) or includes its own monitor module to monitor the factors and estimate an actual power supply level to the power domain based on the factor readings.”; Para 0005-0006, “systems for dynamically adjusting a peak dynamic power threshold are disclosed. Advantageously, embodiments of the solution for peak dynamic power management optimize a peak dynamic power threshold based on estimations of real-time leakage current levels …. method for managing power consumption in a power domain of a portable computing device (“PCD”) begins by setting a peak dynamic power threshold …. calculate an optimum level for the peak dynamic power threshold based on an estimated leakage power level”; Para 0024, “dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change. In doing so, a PDP solution maximizes the amount of power allocated for workload processing while ensuring that the total power consumed does not exceed the power supply capacity”).
Regarding Claim 6, PARK teaches wherein the system management circuit is configured to estimate power consumption of the plurality of circuits based in part on a calculation representative of relationship between power delivery network loss, current, and one or more of voltage and temperature (Para 0005-0006, “systems for dynamically adjusting a peak dynamic power threshold are disclosed. Advantageously, embodiments of the solution for peak dynamic power management optimize a peak dynamic power threshold based on estimations of real-time leakage current levels and/or actual power supply levels to a power domain of a system on a chip (“SoC”). In this way, embodiments of the solution ensure that a maximum amount of available power supply is allocated to dynamic power consumption for processing workloads without risking that the total power consumption (leakage power consumption+dynamic power consumption) for the power domain exceeds the power supply capacity …. With the monitored operating temperatures and active voltage levels, the method may then calculate an optimum level for the peak dynamic power threshold based on an estimated leakage power level calculated from the monitored temperature and voltage levels associated with the one or more processing components”).
Regarding Claim 8, PARK teaches wherein the condition is a detected decrease in the estimated power delivery network loss (Para 0005-0006, “the monitored temperature and voltage levels associated with the one or more processing components”; Para 0024, “dynamically adjust the peak dynamic power limit and/or the operating frequency limit based on an estimated silicone leakage change and power supply capability change. In doing so, a PDP solution maximizes the amount of power allocated for workload processing while ensuring that the total power consumed does not exceed the power supply capacity”).
Note that, under the broadest reasonable interpretation, “the condition is a detected decrease in the estimated power delivery network loss” is indicative of a monitored/detected power loss which is taught by condition related to the monitored voltage levels and power supply capability change detected/estimated at least at paragraphs 0005-0006 and 0024.
Regarding Claim 9, it is a method type claim and has similar limitations as of claim 1 above. Therefore, it is rejected under the same rationale as of claim 1 above.
Regarding Claim 10, it is dependent on claim 9 and has similar limitations as of claim 2 above. Therefore, it is rejected under the same rationale as of claim 2 above.
Regarding Claim 11, it is dependent on claim 9 and has similar limitations as of claim 3 above. Therefore, it is rejected under the same rationale as of claim 3 above.
Regarding Claim 12, it is dependent on claim 10 and has similar limitations as of claim 4 above. Therefore, it is rejected under the same rationale as of claim 4 above.
Regarding Claim 13, it is dependent on claim 10 and has similar limitations as of claim 5 above. Therefore, it is rejected under the same rationale as of claim 5 above.
Regarding Claim 14, it is dependent on claim 9 and has similar limitations as of claim 6 above. Therefore, it is rejected under the same rationale as of claim 6 above.
Regarding Claim 16, it is dependent on claim 9 and has similar limitations as of claim 8 above. Therefore, it is rejected under the same rationale as of claim 8 above.
Regarding Claim 17, it is a system type claim having similar limitations as of claim 1 above. Therefore, it is rejected under the same rationale as of claim 1 above. The additional elements of a central processing circuit (Fig. 7, CPU 110), a graphics processing circuit (Fig. 7, the digital signal processor 110) and a memory subsystem (Fig. 8, memory 112) are taught by PARK at least at Figs. 7 and 8.
Regarding Claim 18, it is dependent on claim 17 and has similar limitations as of claim 3 above. Therefore, it is rejected under the same rationale as of claim 3 above.
Regarding Claim 19, it is dependent on claim 17 and has similar limitations as of claim 6 above. Therefore, it is rejected under the same rationale as of claim 6 above.
Regarding Claim 20, it is dependent on claim 17 and has similar limitations as of claim 7 above. Therefore, it is rejected under the same rationale as of claim 7 above.
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
ETTES et al. (US 20200117468 A1) teaches estimate the power loss by subtracting the reported received power from the transmitted power, where an estimate of the internal power losses in the power receiver (e.g. losses of the rectifier, the receiver coil, metal parts being part of the receiver etc.) is added. (See at least paragraph 0012).
Flynn et al. (US 20200117468 A1) teaches detect a power loss condition at a power receiver, wherein the power receiver is a universal serial bus type C connection; and initialize a shutdown sequence drawing power from a shutdown power source of a thin client in response to the detection of the power loss condition, where the shutdown power source is sized to store an amount of power for a shutdown sequence of the thin client.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BYUNG RO LEE/Examiner, Art Unit 2858 /LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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