DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 19 March 2026 of Applicants’ amendments in which claims 1 and 20 are amended.
Response to Arguments
Applicants argue on pages 5-9 and with respect to claim 1 (and similarly with respect to claim 20) that Kim, Majhi, and Gudala do not teach the subject matter newly added to claim 1 whereby “the power via comprises a conductive path from the power distribution network, at a plane including the signal pad, to the core.” This subject matter was discussed by the participants of a telephonic interview conducted on 13 March 2026; during the interview, the examiner requested that Applicants identify – within their next communication to the Office – where support for the immediately-above-quoted material exists within the original application. And while the Office greatly appreciates Applicants’ effort to do so within the Remarks of their submission, the Office respectfully submits the material cited by Applicants does not provide an adequate written description of the subject matter Applicants have amended the independent claims to recite. Instead, the original application discloses in Fig. 2 and paragraph [0072] a surface of the PDN 200 may be substantially coplanar with a surface of the pad areas 500. Thus, the application does not disclose that some portion of a power via (e.g., 300), or a conductive path therein, is coplanar with the signal pad (e.g., 500). For this reason, the Office has rejected the claims under 35 U.S.C. sections 112(a) and 112(b) and interpreted the newly-added subject matter in a way that comports with the original application. A discussion of how the interpreted subject matter is taught by Kim is discussed below with respect to the section 103 rejections of independent claims 1 and 20.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1, lines 14 and 15, recites “the power via comprises a conductive path from the power distribution network, at a plane including the signal pad, to the core,” which is not illustrated by the drawings. Page 7 of Applicants’ Remarks include an annotated drawing putatively illustrating the claimed subject matter. However, as best, both this annotated drawing and the original drawings illustrate that an upper surface of the power distribution network (e.g., 200) is coplanar with an upper surface of an input pad (e.g., 500). The drawings do not illustrate that some portion of a power via (e.g., 300), or a conductive path therein, is coplanar with the signal pad (e.g., 500).
Claim 20, lines 10 and 11, recites “the power via comprises a conductive path from the power distribution network, at a plane including the signal pad, to the core,” which is not illustrated by the drawings. Page 7 of Applicants’ Remarks include an annotated drawing putatively illustrating the claimed subject matter. However, as best, both this annotated drawing and the original drawings illustrate that an upper surface of the power distribution network (e.g., 200) is coplanar with an upper surface of an input pad (e.g., 500). The drawings do not illustrate that some portion of a power via (e.g., 300), or a conductive path therein, is coplanar with the signal pad (e.g., 500).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 4, 10, 20, and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, lines 14 and 15, recites “the power via comprises a conductive path from the power distribution network, at a plane including the signal pad, to the core,” which is new matter because it is unsupported by the original application. Page 7 of Applicants’ Remarks include an annotated drawing putatively illustrating the claimed subject matter. However, as best, both this annotated drawing and the original application disclose that an upper surface of the power distribution network (e.g., 200) is coplanar with an upper surface of an input pad (e.g., 500). See, e.g., [0072] of the original application – a surface of the PDN 200 may be substantially coplanar with a surface of the pad areas 500. The original application does not disclose that some portion of a power via (e.g., 300), or a conductive path therein, is coplanar with the signal pad (e.g., 500). Claims 2 and 4-10 are rejected due to their dependency from base claim 1.
Claim 20, lines 10 and 11, recites “the power via comprises a conductive path from the power distribution network, at a plane including the signal pad, to the core,” which is new matter because it is unsupported by the original application. Page 7 of Applicants’ Remarks include an annotated drawing putatively illustrating the claimed subject matter. However, as best, both this annotated drawing and the original application disclose that an upper surface of the power distribution network (e.g., 200) is coplanar with an upper surface of an input pad (e.g., 500). See, e.g., [0072] of the original application – a surface of the PDN 200 may be substantially coplanar with a surface of the pad areas 500. The original application does not disclose that some portion of a power via (e.g., 300), or a conductive path therein, is coplanar with the signal pad (e.g., 500). Claim 21 is rejected due to its dependency from base claim 20.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4, 10, 20, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 14 and 15, recites “the power via comprises a conductive path from the power distribution network, at a plane including the signal pad, to the core,” which is indefinite for the reason identified with respect to the section 112(a) new matter rejection of claim 1. For the purpose of compact prosecution and to better comport with the original application, the claim will be interpreted to recite “the power via comprises a conductive path from the power distribution network to the core.” Claims 2 and 4-10 are rejected due to their dependency from base claim 1.
Claim 20, lines 10 and 11, recites “the power via comprises a conductive path from the power distribution network, at a plane including the signal pad, to the core,” which is indefinite for the reason identified with respect to the section 112(a) new matter rejection of claim 1. For the purpose of compact prosecution and to better comport with the original application, the claim will be interpreted to recite “the power via comprises a conductive path from the power distribution network to the core.” Claim 21 is rejected due to its dependency from base claim 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US20220130761A1) in view of Majhi et al. (US20230197612A1) and Gudala et al. (US20180342460A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Kim teaches in Fig. 1 a system for routing connections to a logic circuit, the system comprising:
a first wafer (10) having a backside and a frontside opposite the backside {¶0030};
a power distribution network (PDN) at the backside of the first wafer (10), and comprising a power conductor (one of 44 connected to 17) {¶0047};
a core (CEL) at the frontside of the first wafer (10) {¶0037};
a power via (one of 12 connecting 44 to 17) having a first width (implicit), and being electrically connected to the power conductor (one of 44 connected to 17) and to the core (CEL) {¶0036, 0047};
a signal pad (pad 58 above 60 connected to 30) at the backside of the first wafer (10) {¶0047, 0048};
a first frontside signal-routing metal (one of 30 connected to one of 60) at the frontside of the first wafer (10) {¶0043}; and
a signal via (combination of 12 & 28 connecting one of 60 connected to 30) having a second width (implicit), and being connected (directly/indirectly) to the signal pad (pad 58 above 60 connected to 30) and the first frontside signal-routing metal (one of 30 connected to one of 60) {¶0042},
wherein the power via (one of 12 connecting 44 to 17) comprises a conductive path from the power distribution network (PDN) to the core (CEL).
Kim does not teach:
the signal pad being spaced apart from the power distribution network;
the signal via having a second width greater than the first width of the power via.
In an analogous art, Majhi teaches in Fig. 6F and paragraphs [0041, 0044, 0054] a signal pad (182a) being spaced apart from a power distribution network (124b, 144b, 182b) and a signal via (144a) having a second width greater than a first width of a power via (124b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s system based on the teachings of Majhi – such that the signal pad is spaced apart from the power distribution network; and the signal via has a second width greater than the first width of the power via – so: (1) all three interconnect structures … and the interconnect feature … participate in the inter-chip logic signal routing {Majhi [0080]} and (2) routing congestion in the frontside interconnect structure is reduced {[Majhi [0017]}. Moreover, this structure achieves the benefit whereby resistance is lowered in the signal via. Gudala ¶0032. Furthermore, Gudala teaches in paragraphs [0030] and [0031] that the width of a via is a result-effective variable for optimizing the resistance of the via. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to discover the optimal or workable ranges of via resistance for each of Kim’s power via and signal via – such that Kim’s signal via has a second width greater than the first width of Kim’s power via – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A). Still further, all the claimed elements (e.g., signal pad, power distribution network, power via, signal via) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Majhi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 2, Kim as modified by Majhi and Gudala teaches the system of claim 1, and Kim further teaches wherein a height of the signal via (combination of 12 & 28 connecting one of 60 connected to 30) is larger than a height of the power via (one of 12 connecting 44 to 17) {Fig. 1}.
Regarding claim 4, Kim as modified by Majhi and Gudala teaches the system of claim 1, and Kim further teaches further comprising a second wafer (SBL2) at the frontside of the first wafer (10), and located above the core (CEL) {¶0042}.
Regarding claim 20, as interpreted in view of the indefiniteness rejection, Kim teaches in Fig. 1 an integrated circuit, comprising:
a first wafer (10) having a backside and a frontside {¶0030};
a core (CEL) at the frontside of the first wafer (10) {¶0037};
a power distribution network (PDN) at the backside of the first wafer (10), and connected to the core (CEL) through a power via (one of 12 connecting 44 to 17) having a first width (implicit) {¶0047};
a frontside signal-routing metal (WIL) at the frontside of the first wafer (10) {¶0043}; and
a signal pad (pad 58 above 60 connected to 30) at the backside of the first wafer (10), and connected to the frontside signal-routing metal (WIL) through a signal via (combination of 12 & 28 connecting one of 60 connected to 30) having a second width (implicit) {¶0047, 0048},
wherein the power via (one of 12 connecting 44 to 17) comprises a conductive path from the power distribution network (PDN) to the core (CEL).
Kim does not teach the signal via having a second width greater than the first width of the power via.
Majhi teaches in Fig. 6F and paragraphs [0041, 0044, 0054] a signal via (144a) having a second width greater than a first width of a power via (124b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s system based on the teachings of Majhi – such that the signal via has a second width greater than the first width of the power via – so resistance is lowered in the signal via. Gudala ¶0032. Furthermore, Gudala teaches in paragraphs [0030] and [0031] that the width of a via is a result-effective variable for optimizing the resistance of the via. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to discover the optimal or workable ranges of via resistance for each of Kim’s power via and signal via – such that Kim’s signal via has a second width greater than the first width of Kim’s power via – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A). Still further, all the claimed elements (e.g., power via, signal via, width) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Majhi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 21, Kim as modified by Majhi and Gudala teach the integrated circuit of claim 20, but Kim does not teach wherein the signal pad is spaced apart from the power distribution network.
Majhi teaches in Fig. 6F and paragraphs [0041, 0044, 0054] a signal pad (182a) being spaced apart from a power distribution network (124b, 144b, 182b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s system as modified by Majhi and Gudala based on the further teachings of Majhi – such that the signal pad is spaced apart from the power distribution network – so: (1) all three interconnect structures … and the interconnect feature … participate in the inter-chip logic signal routing {Majhi [0080]} and (2) routing congestion in the frontside interconnect structure is reduced {[Majhi [0017]}. Moreover, all the claimed elements (e.g., signal pad, power distribution network) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Majhi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Majhi and Gudala as applied to claim 1 above, and further in view of Li et al. (US20220020665A1).
Regarding claim 5, Kim as modified by Majhi and Gudala teaches the system of claim 1, but Kim does not teach further comprising a package at the backside of the first wafer.
In an analogous art, Li teaches in Fig. 4 a package (455) at the backside of the first wafer (420). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s system as modified by Majhi and Gudala based on the teachings of Li – such that a package is disposed at the backside of the first wafer – for the purposes of: (1) providing mechanical support for the system and (2) interconnecting signal/power leads within the package to corresponding signal/power pads of the system so that signals and power may be conveyed among multiple interconnected systems by the package.
Moreover, the modification would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because all the claimed elements (e.g., package, wafer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Li) with no change in their respective functions and with the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 6, Kim as modified by as modified by Majhi, Gudala, and Li teaches the system of claim 5, and Kim further teaches further comprising a pad area (area of 58s directly above 60s) at the backside of the first wafer (10) {Fig. 1}.
Regarding claim 7, Kim as modified by as modified by Majhi, Gudala, and Li teaches the system of claim 6, and Kim further teaches wherein the pad area (area directly above 60s) comprises:
a first pad area comprising a supply voltage pad and a first signal pad {see annotated copy of Kim’s Fig. 1 below}; and
a second pad area comprising a second signal pad {see annotated copy of Kim’s Fig. 1 below}.
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Regarding claim 8, Kim as modified by as modified by Majhi, Gudala, and Li teaches the system of claim 7, and Kim further teaches further comprising:
a conductive path configured to route a supply voltage:
from the package (see modification discussed in claim 5) to the supply voltage pad (supply voltage pad) {¶0048; see annotated copy of Kim’s Fig. 1 below};
from the supply voltage pad (supply voltage pad) to the power distribution network (PDN) {¶0048}; and
from the power distribution network (PDN) to the core (10) {¶0047, PDN may include lower multi-layer interconnect layers 44, 48, 54, 58, and 59 connected to the rail [17a, 17b] through via 12 and lower vias 46, 50, 52, and 56 connecting the lower multi-layer interconnect layers 44, 48, 54, 58, and 59 to each other}.
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Regarding claim 9, Kim as modified by as modified by Majhi, Gudala, and Li teaches the system of claim 7, and Kim further teaches further comprising a conductive path configured to route a signal {“configured to route a signal” is a manner of employment limitation}:
from the package (see modification discussed in claim 5) to the first signal pad (first signal pad) {through external connection terminal 60};
from the first signal pad (first signal pad) to the first frontside signal-routing metal (one of 30 connected to one of 60) {see annotated copy of Kim’s Fig. 1 below}; and
from the first frontside signal-routing metal (one of 30 connected to one of 60) to the core (CEL) {¶0059, the source and drain regions SD1 and SD2 [of transistors within the cell portion CEL] may be connected to the upper multi-layer interconnect layers 26, 30, and 34 (FIG. 1) via the local interconnect 22}.
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Regarding claim 10, Kim as modified by as modified by Majhi, Gudala, and Li teaches the system of claim 7, and Kim further teaches further comprising a conductive path configured to route a signal {“configured to route a signal” is a manner of employment limitation}:
from the core (CEL) to a second frontside signal-routing metal (another one of 30 connected to one of 60) {¶0059, the source and drain regions SD1 and SD2 [of transistors within the cell portion CEL] may be connected to the upper multi-layer interconnect layers 26, 30, and 34 (FIG. 1) via the local interconnect 22};
from the second frontside signal-routing metal (other one of 30 connected to one of 60) to the second signal pad (second signal pad); and
from the second signal pad (second signal pad) to the package (see modification discussed in claim 5).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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