DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 29 April 2025 of Applicants’ amendments in which claims 1, 2, and 20 are amended and claim 3 is cancelled.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US20220130761A1) in view of Chou (US20200395273A1) and Gudala et al. (US20180342460A1).
Regarding claim 1, Kim teaches in Fig. 1 a system for routing connections to a logic circuit, the system comprising:
a first wafer (10) having a backside and a frontside opposite the backside {¶0030};
a power conductor (one of 44 connected to 17) at the backside of the first wafer (10) {¶0047};
a core (CEL) at the frontside of the first wafer (10) {¶0037};
a power via (one of 12 connecting 44 to 17) having a first width (implicit), and being electrically connected to the power conductor (one of 44 connected to 17) and to the core (CEL) {¶0036, 0047};
a signal pad (pad 58 above 60 connected to 30) at the backside of the first wafer (10) {¶0047};
a first frontside signal-routing metal (one of 30 connected to one of 60) at the frontside of the first wafer (10) {¶0043}; and
a signal via (combination of 12 & 28 connecting one of 60 connected to 30) having a second width (implicit), and being connected (directly/indirectly) to the signal pad (pad 58 above 60 connected to 30) and the first frontside signal-routing metal (one of 30 connected to one of 60) {¶0042}.
Kim does not teach the signal via having a second width greater than the first width of the power via.
In an analogous art, Chou teaches in Fig. 4 and paragraph [0042] a second width (336) of a second via (330) is greater than a first width (346) of a first via (340). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s system based on the teachings of Chou – such that Kim’s signal via has a second width greater than the first width of Kim’s power via – so resistance is lowered in the signal via. Gudala ¶0032.
Moreover, Gudala teaches in paragraphs [0030] and [0031] that the width of a via is a result-effective variable for optimizing the resistance of the via. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to discover the optimal or workable ranges of via resistance for each of Kim’s power via and signal via – such that Kim’s signal via has a second width greater than the first width of Kim’s power via – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A).
Regarding claim 2, Kim as modified by Chou and Gudala teaches the system of claim 1, and Kim further teaches wherein a height of the signal via (combination of 12 & 28 connecting one of 60 connected to 30) is larger than a height of the power via (one of 12 connecting 44 to 17) {Fig. 1}.
Regarding claim 4, Kim as modified by Chou and Gudala teaches the system of claim 1, and Kim further teaches further comprising a second wafer (SBL2) at the frontside of the first wafer (10), and located above the core (CEL) {¶0042}.
Regarding claim 20, Kim teaches in Fig. 1 an integrated circuit, comprising:
a first wafer (10) having a backside and a frontside {¶0030};
a core (CEL) at the frontside of the first wafer (10) {¶0037};
a power distribution network (PDN) at the backside of the first wafer (10), and connected to the core (CEL) through a power via (one of 12 connecting 44 to 17) having a first width (implicit) {¶0047};
a frontside signal-routing metal (WIL) at the frontside of the first wafer (10) {¶0043}; and
a signal pad (pad 58 above 60 connected to 30) at the backside of the first wafer (10), and connected to the frontside signal-routing metal (WIL) through a signal via (combination of 12 & 28 connecting one of 60 connected to 30) having a second width (implicit) that is greater than the first width {¶0047}.
Kim does not teach the signal via having a second width greater than the first width of the power via.
In an analogous art, Chou teaches in Fig. 4 and paragraph [0042] a second width (336) of a second via (330) is greater than a first width (346) of a first via (340). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s system based on the teachings of Chou – such that Kim’s signal via has a second width greater than the first width of Kim’s power via – so resistance is lowered in the signal via. Gudala ¶0032.
Moreover, Gudala teaches in paragraphs [0030] and [0031] that the width of a via is a result-effective variable for optimizing the resistance of the via. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to discover the optimal or workable ranges of via resistance for each of Kim’s power via and signal via – such that Kim’s signal via has a second width greater than the first width of Kim’s power via – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A).
Claim(s) 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chou and Gudala as applied to claim 1 above, and further in view of Li et al. (US20220020665A1).
Regarding claim 5, Kim as modified by Chou and Gudala teaches the system of claim 1, but Kim does not teach further comprising a package at the backside of the first wafer.
In an analogous art, Li teaches in Fig. 4 a package (455) at the backside of the first wafer (420). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s system as modified by Chou and Gudala based on the teachings of Li – such that a package is disposed at the backside of the first wafer – for the purposes of: (1) providing mechanical support for the system and (2) interconnecting signal/power leads within the package to corresponding signal/power pads of the system so that signals and power may be conveyed among multiple interconnected systems by the package.
Moreover, the modification would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because all the claimed elements (e.g., package, wafer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Li) with no change in their respective functions and with the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 6, Kim as modified by as modified by Chou, Gudala, and Li teaches the system of claim 5, and Kim further teaches further comprising a pad area (area of 58s directly above 60s) at the backside of the first wafer (10) {Fig. 1}.
Regarding claim 7, Kim as modified by as modified by Chou, Gudala, and Li teaches the system of claim 6, and Kim further teaches wherein the pad area (area directly above 60s) comprises:
a first pad area comprising a supply voltage pad and a first signal pad {see annotated copy of Kim’s Fig. 1 below}; and
a second pad area comprising a second signal pad {see annotated copy of Kim’s Fig. 1 below}.
PNG
media_image1.png
708
664
media_image1.png
Greyscale
Regarding claim 8, Kim as modified by as modified by Chou, Gudala, and Li teaches the system of claim 7, and Kim further teaches further comprising:
a power distribution network (PDN) at the backside of the first wafer (10), and comprising the power conductor (one of 44 connected to 17) {¶0047}; and
a conductive path configured to route a supply voltage:
from the package (see modification discussed in claim 5) to the supply voltage pad (supply voltage pad) {¶0048; see annotated copy of Kim’s Fig. 1 below};
from the supply voltage pad (supply voltage pad) to the power distribution network (PDN) {¶0048}; and
from the power distribution network (PDN) to the core (10) {¶0047, PDN may include lower multi-layer interconnect layers 44, 48, 54, 58, and 59 connected to the rail [17a, 17b] through via 12 and lower vias 46, 50, 52, and 56 connecting the lower multi-layer interconnect layers 44, 48, 54, 58, and 59 to each other}.
PNG
media_image1.png
708
664
media_image1.png
Greyscale
Regarding claim 9, Kim as modified by as modified by Chou, Gudala, and Li teaches the system of claim 7, and Kim further teaches further comprising a conductive path configured to route a signal {“configured to route a signal” is an intended use limitation}:
from the package (see modification discussed in claim 5) to the first signal pad (first signal pad) {through external connection terminal 60};
from the first signal pad (first signal pad) to the first frontside signal-routing metal (one of 30 connected to one of 60) {see annotated copy of Kim’s Fig. 1 below}; and
from the first frontside signal-routing metal (one of 30 connected to one of 60) to the core (CEL) {¶0059, the source and drain regions SD1 and SD2 [of transistors within the cell portion CEL] may be connected to the upper multi-layer interconnect layers 26, 30, and 34 (FIG. 1) via the local interconnect 22}.
PNG
media_image1.png
708
664
media_image1.png
Greyscale
Regarding claim 10, Kim as modified by as modified by Chou, Gudala, and Li teaches the system of claim 7, and Kim further teaches further comprising a conductive path configured to route a signal {“configured to route a signal” is an intended use limitation}:
from the core (CEL) to a second frontside signal-routing metal (another one of 30 connected to one of 60) {¶0059, the source and drain regions SD1 and SD2 [of transistors within the cell portion CEL] may be connected to the upper multi-layer interconnect layers 26, 30, and 34 (FIG. 1) via the local interconnect 22};
from the second frontside signal-routing metal (other one of 30 connected to one of 60) to the second signal pad (second signal pad); and
from the second signal pad (second signal pad) to the package (see modification discussed in claim 5).
PNG
media_image1.png
708
664
media_image1.png
Greyscale
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891