DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 12/16/2025, responding to the Office action mailed on 9/19/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-8, 10-18, 20-24, and new claims 25-26 are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/16/2025 and 2/4/2026 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Frougier (US 20200287046 A1) and Abhijith (US 20220123152 A1).
Re Claim 1 Lilak teaches an integrated circuit comprising:
an upper body (106) [0036] extending in a first direction (horizontal) from an upper source region (120 on left in 106) to an upper drain region (120 on right in 106), and a lower body (108) extending in the first direction (vertical) from a lower source region (120 on left in 108) to a lower drain region (120 on right in 108), the upper body spaced vertically from the
lower body in a second direction orthogonal to the first direction (FIG. 2A), each of the upper body and the lower body comprising semiconductor material [0054],
a gate spacer structure (146, use middle portion of FIG. 4A between 120 regions) adjacent to the upper source region (top left 120 in FIG. 4A) and the lower source region (bottom left 120 in FIG. 4A)
Lilak does not teach the gate spacer structure comprising (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction, wherein the first dimension is different from the second dimension by at least 1 nanometer (nm)
Frougier teaches the gate spacer structure comprising (i) a first section (202) having a first dimension (bottom cross section of 202) in the first direction, and (ii) a second section (204) having a second dimension (cross section area of part labeled 204, FIG. 4) in the first direction, wherein the first dimension is different from the second dimension by at least 1 nanometer (nm) ([0043][0050] teach 130 is up to 10 nm thick. It is clear the cross sectional areas of the dimensions identified are at least 1nm in difference.)
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Frougier into the structure of Lilak since Frougier teaches a gate all around device.
The ordinary artisan would have been motivated to modify Frougier in combination with Lilak in the above manner for the motivation of having the first and second sections having different dimensions to allow the integrate circuit to function optimally. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal first and second dimension values.
Lilak in view of Frougier does not teach the first section directly contacts the second section at an interface, the interface being a seam or grain boundary.
Abhijith teaches the first section (spacer 800 [0046] above 900 in FIG. 9) directly contacts the second section (800 below 900 in FIG. 9) at an interface (900), the interface being a seam (900) [0047].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Abhijith into the structure of Lilak in view of Frougier since Abhijith teaches a gate all around device.
The ordinary artisan would have been motivated to modify Abhijith in combination with Lilak in view of Frougier in the above manner for the motivation of optimally integrating the first section together with the second section with a seam to reduce the dielectric constant of the spacer. [0047] states, “For example, seam 900 reduces the dielectric constant (k value) of spacer layer 800 and the parasitic capacitance formed between gate structures 115 and S/D epitaxial layers 125 in CAA FM's 100 and 105 shown in FIG. 1.”
Re Claim 2 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 1, wherein each of the first section (Frougier, 202) and the second (204, [0054] states, “The inner spacers 204 and the bottom isolation regions 202 can be formed of silicon nitride, silicoboron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material…”) comprises dielectric material.
Re Claim 3 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 2, wherein the dielectric material of the first section (Frougier, 202) and the dielectric material of the second section (204, [0054] states, “The inner spacers 204 and the bottom isolation regions 202 can be formed of silicon nitride, silicoboron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material…”) are elementally same.
Re Claim 5 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 1, wherein:
the first section extends (Lilak 146 on left in direct contact with 150, FIG. 3A ) in the second direction, the first section (i) separating the upper source region (120 top left) from an upper gate stack (144 on top of 150) [0037] and (ii) separating the lower source region (120 bottom left) from a lower gate stack (144 right under 150, FIG. 3A); and
the second section (146 layers directly above and below 1st section) extends in the first direction (FIG. 3A).
Re Claim 6 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 5, wherein the gate spacer structure is a first gate spacer structure, and wherein the integrated circuit further comprises:
a second gate spacer structure (146 directly above and below 1st sections, FIG. 4A, see image fragment below) comprising a third section (146 directly above and below 2nd sections) that extends in the second direction, and separates the upper (120, top right) and lower drain regions (120, bottom left) from the upper (144 over 150) and lower gate stacks (144 under 150, FIG. 4A), respectively.
FIG. 4A fragment shown below to clearly identify parts
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Re Claim 12 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 1, further comprising:
an additional body (Lilak, 144, [0037], FIG. 1A) comprising semiconductor material ([0092] mentions 144 can be tantalum nitride) that is in contact with the second section (use claim 6 image), the additional body (144) extending in the first direction, wherein the additional body is not in contact with any of the upper source region (top left 120), the lower source region (bottom left 120), the upper drain region (top right 120), or the lower drain region (bottom right 120).
Re Claim 16 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 1, wherein:
the gate spacer structure has (i) a first sidewall facing the upper and lower source regions (Lilak, FIG. 4A, use left surface of 132,146 layers against right surface of upper and lower source regions 120)and (ii) a second sidewall opposite the first sidewall (use inner surface of 146);
a first portion of the first sidewall is within the first section (use first section identified in claim 6 image), a second portion of the first sidewall is within the second section (use second section identified in claim 6 image), and the first and second portions of the first sidewall are coplanar (FIG. 4A);
a third portion (inside edge of 146 on left in line with 150) of the second sidewall is within the first section (use claim 6 image), a fourth portion (inside edge of 146 on right in line with 150) of the second sidewall is within the second section,
Lilak in view of Frougier and Abhijith does not explicitly teach the third and fourth portions of the second sidewall are laterally offset from one another by at least 1 nm.
Lilak [0091] teaches the work function layer 145 is 1 nm to 15 nm thick. The third portion (inside edge of 146 on left in line with 150) and the fourth portion (inside edge of 146 on right in line with 150) are further apart than 145 is thick. Therefore, the lateral offset between the third and fourth section is at least 1 nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lilak into the structure of Lilak in view of Frougier and Abhijith.
The ordinary artisan would have been motivated to modify Lilak in combination with Lilak in view of Frougier and Abhijith in the above manner for the motivation of have a lateral offset between the third and fourth sections by at least 1nm to help the device function at an optimal level. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal lateral offset distance between the third and fourth portions of the second sidewall.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Frougier (US 20200287046 A1) and Abhijith (US 20220123152 A1) as applied to claim 1 above, and further in view of Chafik (US 20200098920 A1).
Re Claim 4 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 1, but does not teach the first section comprises a first dielectric material, and the second section comprises a second dielectric material that is compositionally different from the first dielectric material.
Chafik teaches the first section (404a, FIG. 4) [0051] comprises a first dielectric material, and the second section (406a) comprises a second dielectric material that is compositionally different from the first dielectric material ([0052] states, “A material (e.g., a nitride, a fluoride, a carbide, an oxide or a boride) of the first inner gate spacer 406a and/or the second inner gate spacer 406b is different from a material (e.g., oxide) of the first middle gate spacer 404a and/or the second middle gate spacer 404b.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chafik into the structure of Lilak in view of Frougier and Abhijith since Chafik teaches a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Chafik in combination with Lilak in view of Frougier and Abhijith in the above manner for the motivation of insulating dielectric layers are critical for optimal device performance as semiconductors continue to scale down in size. [0002] states, “As integrated circuit (IC) technology advances, device (e.g., semiconductor device) geometries are reduced. Reducing the geometry and “pitch” (spacing) between devices may cause devices to interfere with each other and affect proper operation.”
Claims 7-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Frougier (US 20200287046 A1) and Abhijith (US 20220123152 A1) as applied to claims 1, 5, and 6 above, and further in view of Ebrish (US 20200279913 A1).
Re Claim 7 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 6, but does not teach the second section extends in the first direction from the first section to the third section
Ebrish teaches the second section (502)[0046] extends in the first direction from the first section to the third section (see FIG. 8 fragment below with sections labeled).
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ebrish into the structure of Lilak in view of Frougier and Abhijith.
The ordinary artisan would have been motivated to modify Ebrish in combination with Lilak in view of Frougier and Abhijith in the above manner for the motivation of extending the fourth section from the third section towards the first section to help optimize the current in the device. [0001] states, “…nanosheet transistor barrier schemes configured and arranged to electrically isolate the transistor substrate such that unwanted leakage currents from the source or drain (S/D) region into the substrate are substantially prevented.”
Re Claim 8 Lilak in view of Frougier and Abhijith and Ebrish teaches the integrated circuit of claim 6, wherein the second gate spacer structure further comprises a fourth section that extends (Ebrish, use claim 7 FIG. 8 fragment with labels) in the first direction, from the third section and towards the first section (FIG. 8).
Lilak in view of Frougier and Abhijith and Ebrish does not explicitly teach the fourth section has a third dimension in the first direction that is different from the first dimension by at least 1 nm.
Frougier teaches the second gate spacer structure further comprises a fourth section (FIG. 4, use top left, unlabeled 204) that has a third dimension in the first direction that is different from the first dimension (the third dimension is equal to the 2nd dimension and is therefore different from the 1st dimension by at least 1 nm),
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Frougier into the structure of Lilak in view of Frougier and Abhijith and Ebrish since Frougier teaches a gate all around device.
The ordinary artisan would have been motivated to modify Frougier in combination with Lilak in view of Frougier and Abhijith and Ebrish in the above manner for the motivation of having the first and second sections having different dimensions to allow the integrate circuit to function optimally. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal length for the third dimension.
Re Claim 10 Lilak in view of Frougier and Abhijith and Ebrish teaches the integrated circuit of claim 8, wherein each of the first, second, third, and fourth sections (Ebrish, 502, see drawing under claim 6 for sections) comprise dielectric material ([0046] mentions 502 can be silicon nitride), and wherein the second section and the fourth section of the gate spacer structure are laterally separated (second and fourth sections are separated by 126B which is SiGe [0050]) by conductive material (Ebrish, FIG. 8).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Frougier (US 20200287046 A1) and Abhijith (US 20220123152 A1) as applied to claims 1 and 12 above, and further in view of Ando (US 20200403034 A1).
Re Claim 13 Lilak in view of Frougier and Abhijith teaches the integrated circuit of claim 12 but does not teach a first isolation structure comprising dielectric material between the upper source region and the lower source region; and
a second isolation structure comprising dielectric material between the upper drain region and the lower drain region;
wherein the additional body extends laterally between the first isolation structure and the second isolation structure.
Ando teaches a first isolation structure (112 on left, FIG. 1) comprising dielectric material [0032] between the upper source region (115 top left) and the lower source region (115 lower left); and
a second isolation structure (112 on right, FIG. 1) comprising dielectric material [0032] between the upper drain region (115 top right) and the lower drain region (115 top left);
wherein the additional body (140) extends laterally between the first isolation structure (112 on left) and the second isolation structure (112 on right, FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ando into the structure of Lilak in view of Frougier and Abhijith.
The ordinary artisan would have been motivated to modify Ando in combination with Lilak in view of Frougier and Abhijith in the above manner for the motivation of adding the dielectric isolation layer between the upper and lower source and drain regions as the isolation layers are needed for the device to function optimally. [0004] states, “The semiconductor device also includes isolation layers within stacked nanosheets of the two ReRAM devices and within source and drain regions of the two ReRAM devices.”
Re Claim 14 Lilak in view of Frougier and Abhijith and Ando teaches the integrated circuit of claim 13, wherein the second section (Ando, 130 next to 112) extends laterally between the first isolation structure (112 on left, FIG. 1) and the second isolation structure (112 on right, FIG. 1).
Re Claim 15 Lilak in view of Frougier and Abhijith and Ando teaches the integrated circuit of claim 12, but does not explicitly teach a height of the additional body is at least 2 nm less than a height of one or both the upper and lower bodies, the heights measured in the second direction.
Ando does teach a height of the additional body (Ando, 140, FIG. 1) is less than half the height of the upper body (height of top right 115) and therefore will be at least 2 nm less than a height of one or both the upper and lower bodies.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ando into the structure of Lilak in view of Frougier and Abhijith.
The ordinary artisan would have been motivated to modify Ando in combination with Lilak in view of Frougier and Abhijith and Ando in the above manner for the motivation of finding ideal body height. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal dimensions for the additional body.
Claims 17-18 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Ebrish (US 20200279913 A1).
Re Claim 17 Lilak teaches an integrated circuit structure comprising:
an upper device (106) comprising an upper source region (120 top left) [0036], an upper drain region (top right), an upper body of semiconductor material (132)[0036] laterally extending from the upper source region (120 top left) to the upper drain region (120 top right), and an upper gate structure (144 in 106) wrapping around at least a corresponding section of the upper body (132, FIG. 3B);
a lower device (108) comprising a lower source region (120 lower left), a lower drain region (lower right), a lower body of semiconductor material (132 under 150, FIG. 3A)[0036]) laterally extending from the lower source region (120 lower left) to the lower drain region (120 lower right), and a lower gate structure (144 in 108) wrapping around at least a corresponding section of the lower body (132, FIG. 3B); and
a gate spacer structure (146 on left, FIG. 3A) [0037] including (i) an upper portion (146 on left above 150, FIG. 3A) separating the upper gate structure (142 and 144 in 106) from the upper source region (120 top left), (ii) a lower portion (146 on left below 150) separating the lower gate (142 and 144 in 108) structure from the lower source region (120 left), and (iii) an intermediate portion (150) between the upper (106) and lower portions (108), the intermediate portion extending laterally between the upper (144 in 106) and lower gate structures (144 in 108, FIG. 3A and 3B).
Lilak does not teach the upper portion, the lower portion, and the intermediate portion comprise a continuous, monolithic dielectric material.
Ebrish teaches the upper portion, the lower portion, and the intermediate portion comprise a continuous, monolithic dielectric material (502 contains SiN, [0046], see modified FIG. 5 below).
Modified FIG. 5 below shows portions labelled
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ebrish into the structure of Lilak since Ebrish teaches a semiconductor device structure.
The ordinary artisan would have been motivated to modify Ebrish in combination with Lilak in the above manner for the motivation of optimally integrating the dielectric material to help prevent excess gauging during subsequent RIE processes. [0046] states, “The inner spacers 502 can be formed from a nitride containing material (e.g., silicon nitride (SiN)), which prevents excess gauging during subsequent RIE processes (e.g., sacrificial nanosheet removal) that are applied during the semiconductor device fabrication process.”
Re Claim 18 Lilak in view of Ebrish teaches the integrated circuit structure of claim 17, wherein the upper gate structure (Lilak, 142 on left in FIG. 4B and 144 in 106) comprises an upper gate electrode (144) [0037], the lower gate structure (bottom 142, 144 in 108) comprises a lower gate electrode (144), a section of the upper gate electrode (144 in 106) is above the intermediate portion (150), and a section of the lower gate electrode (144 in 108) is below the intermediate portion (150, FIG. 4A).
Re Claim 25 Lilak teaches the integrated circuit structure of claim 17, wherein the gate spacer structure (Lilak, 146 on left FIG. 3A) is a first gate spacer structure, and wherein the integrated circuit further comprises:
a second gate spacer structure (146 on right, FIG. 3A) comprising (i) an upper portion (146 on right above 150) separating the upper gate structure (142 and 144 in 106) from the upper drain region (120 top right), (ii) a lower portion (146 below 150) separating the lower gate structure (142 and 144 below 150) from the lower drain region (120 bottom right), and (iii) the intermediate portion (150).
Lilak does not teach of the upper portion of the first gate spacer structures, the lower portion of the first gate spacer structure, the upper portion of the second gate spacer structures, the lower portion of the second gate spacer structure, and the intermediate portion comprise the continuous, monolithic dielectric material.
Ebrish teaches of the upper portion of the first gate spacer structures (502 on top left of 118A, see modified FIG. 5 under claim 17), the lower portion (502 to left of 118A) of the first gate spacer structure, the upper portion of the second gate spacer structures (502 to upper right of 118A), the lower portion of the second gate spacer structure (502 to right of 118A), and the intermediate portion (502 above 118A and below 202) comprise the continuous, monolithic dielectric material (502 in FIG. 5 is a continuous/monolithic [0046], see modified FIG. 5 under claim 17).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ebrish into the structure of Lilak since Ebrish teaches a semiconductor device structure.
The ordinary artisan would have been motivated to modify Ebrish in combination with Lilak in the above manner for the motivation of optimally integrating the dielectric material to help prevent excess gauging during subsequent RIE processes. [0046] states, “The inner spacers 502 can be formed from a nitride containing material (e.g., silicon nitride (SiN)), which prevents excess gauging during subsequent RIE processes (e.g., sacrificial nanosheet removal) that are applied during the semiconductor device fabrication process.”
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Ebrish (US 20200279913 A1) as applied to claim 17 above, and further in view of Ando (US 20200403034 A1).
Re Claim 20 Lilak in view of Ebrish teaches the integrated circuit structure of claim 17, further comprising:
Lilak in view of Ebrish does not teach a first isolation structure between the upper source region and the lower source region; and
a second isolation structure between the upper drain region and the lower drain region,
wherein the intermediate portion is laterally between the first isolation structure and the second isolation structure
Ando teaches a first isolation structure (112) [0032] between the upper source region (top left 115)[0034] and the lower source region (lower left 115); and
a second isolation structure (112 on right) between the upper drain region (top right 115) and the lower drain region (bottom right 115),
wherein the intermediate portion (130 between 152 sections) [0036] is laterally between the first isolation structure and the second isolation structure (FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ando into the structure of Lilak in view of Ebrish.
The ordinary artisan would have been motivated to modify Ando in combination with Lilak in view of Ebrish in the above manner for the motivation of adding the dielectric isolation layer between the upper and lower source and drain regions as the isolation layers are needed for the device to function optimally. [0004] states, “The semiconductor device also includes isolation layers within stacked nanosheets of the two ReRAM devices and within source and drain regions of the two ReRAM devices.”
Re Claim 21 Lilak in view of Ebrish and Ando teaches the integrated circuit structure of claim 17, further comprising:
an intermediate body (Ando, 135 and 140 between 112 portions (and 105 below it) comprising semiconductor material (105 has Si [0033]) in contact with the intermediate portion (130 between 112 layers), wherein the intermediate body is not in contact with any of the upper
source region (upper left 115), the lower source region (lower left 115), the upper drain region (upper right 115), or the lower drain region (lower right 115, FIG. 1).
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Ebrish (US 20200279913 A1) and Abhijith (US 20220123152 A1).
Re Claim 22 Lilak teaches an integrated circuit structure comprising:
an upper source or drain region (120 top left, FIG. 1A) [0037], a lower source or drain region (bottom left 120) below the upper source or drain region, and
an isolation region (150 on left) [0037] between the upper source or drain region (120 top right) and the lower source or drain region (120 bottom right); and
a spacer structure (146) comprising dielectric material [0075] and having (i) an outer sidewall (outer edges of 146) adjacent to the upper source or drain region, the lower source or drain region, and the isolation region (FIG. 1A), and
(ii) an inner sidewall (inside edges of 146) opposite the outer sidewall, wherein an entirety of the outer sidewall that is adjacent to the upper source or drain region (120 top left), the lower source or drain region (120 bottom left), and the isolation region (150 left) is substantially coplanar (FIG. 1A, and
wherein the inner sidewall has (i) a first section (use inside edge of 146 next to the 150 on the left, FIG. 1A) and (ii) a second section (inside edge of 146 next to the 150 on the right, FIG. 1A).
Lilak does not teach the second section is laterally offset from the first section by at least 1 nanometer (nm).
Ebrush teaches the second section is laterally offset from the first section by at least 1 nanometer (nm) (see Fig. 8, sections labeled) (The nanosheets (124B from FIG. 8 shown below to left of 2nd section) are 3 nm to 20 nm [0037]. The nanosheet thickness is close to the offset between the left wall of the second section and the left wall of the 1st section making the lateral offset > 1 nm.)
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The ordinary artisan would have been motivated to modify Ebrish in combination with Lilak in the above manner for the motivation of finding the ideal length between the inner sidewalls. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal inner wall offset dimensions.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ebrish into the structure of Lilak.
Lilak in view of Ebrish does not teach the first section is a sidewall of a first portion of the spacer structure and the second section is a sidewall of a second portion of the spacer structure, the first portion of the spacer structure directly contacting the second portion of the spacer structure at an interface, the interface being a seam or grain boundary.
Abhijith teaches the first section (spacer 800 [0046] above 900 in FIG. 9) is a sidewall of a first portion of the spacer structure (800) and the second section (800 below 900 in FIG. 9) is a sidewall of a second portion of the spacer structure (800), the first portion of the spacer structure directly contacting the second portion of the spacer structure at an interface (FIG. 9), the interface being a seam(900) [0047].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Abhijith into the structure of Lilak in view of Ebrish since Abhijith teaches a gate all around device.
The ordinary artisan would have been motivated to modify Abhijith in combination with Lilak in view of Ebrish in the above manner for the motivation of optimally integrating the first section together with the second section with a seam to reduce the dielectric constant of the spacer. [0047] states, “For example, seam 900 reduces the dielectric constant (k value) of spacer layer 800 and the parasitic capacitance formed between gate structures 115 and S/D epitaxial layers 125 in CAA FM's 100 and 105 shown in FIG. 1.”
Re Claim 23 Lilak in view of Ebrish and Abhijith teaches the integrated circuit structure of claim 22, but does not explicitly teach the second section of the inner sidewall is laterally offset from the first section of the inner sidewall by at least 5 nm.
Lilak does teach the nanowires are spaced close to 5 nanometers apart [0044]. The second section of the inner sidewall (left edge of 146 next to the right 150, FIG. 1A) has a greater later offset than distance between nanowires making the lateral offset between the first and second inner wall >5nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lilak into the structure of Lilak in view of Ebrish and Abhijith.
The ordinary artisan would have been motivated to modify Lilak in combination with Lilak in view of Ebrish and Abhijith in the above manner for the motivation of finding the ideal length between the inner sidewalls. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal inner wall offset dimensions.
Re Claim 24 Lilak in view of Ebrish and Abhijith teaches the integrated circuit structure of claim 22, further comprising:
an upper body (Lilak, 106) comprising first semiconductor material [0082] and extending laterally from the upper source or drain region (120 top left), wherein an end portion of the upper body is in contact with the upper source or drain region (FIG. 1A);
a lower body (108) comprising second semiconductor material [0082] and extending laterally from the lower source or drain region (lower left 120), wherein an end portion of the lower body is in contact with the lower source or drain region (FIG. 1A); and
an intermediate body (144 between 150 layers) comprising third semiconductor material [0092] and extending laterally, wherein the upper body (106) is above the intermediate body and the lower body (108) is below the intermediate body, and wherein an end portion of the intermediate body is not in contact with any source or drain regions (FIG. 1A).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 20200098756 A1) in view of Ebrish (US 20200279913 A1) and Abhijith (US 20220123152 A1) as applied to claim 22 above, and further in view of Reznicek (US 10679890 B2).
Re Claim 26 Lilak in view of Ebrish and Abhijith teaches the integrated circuit structure of claim 22, but does not teach the first section comprises a first dielectric material, and the second section comprises a second dielectric material that is compositionally different from the first dielectric material.
Reznicek teaches the first section (190, col 7 line 21 mentions silicon nitride) comprises a first dielectric material, and the second section (152, col 5 line 67 mentions silicon oxide) comprises a second dielectric material that is compositionally different from the first dielectric material.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Reznicek into the structure of Lilak in view of Ebrish and Abhijith.
The ordinary artisan would have been motivated to modify Reznicek in combination with Lilak in view of Ebrish and Abhijith in the above manner for the motivation of forming the first and second section of optimal materials to allow for the device to function at a peak level. Col 1 line 15 states, “The use of non-planar semiconductor devices such as, for example, fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices.”
Allowable Subject Matter
Claims 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-10 and 12-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/28/26
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