DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 31 December 2025, regarding the prior art rejection of Claims 1 – 3, 5 – 6, 11 – 12, 19 – 20, 24 – 25 have been fully considered but they are not persuasive. Specifically, Applicant asserts the limitation “…a backside gate contact from the gate to the backside signal line, wherein a backside gate contact via associated with the backside gate contact is disposed within a shallow trench isolation (STI) region” is neither taught nor suggested by any of the cited references on page 10 of the response. The Examiner respectfully disagrees, as WEI (EP 3993062 A1/US 20220139911 A1) teaches in Fig. 4E that the backside gate contact (371-2/483; Par. 124/125) from the gate (483; Par. 125) to the backside signal line (482; Par. 128), wherein a backside gate contact via (The opening between the 364 sidewalls, containing 483) associated with the backside gate contact is disposed within a trench (The opening between the 380 sidewalls, containing the 364s and 483) of an isolation region (380, which is a dielectric, Par. 127). Therefore, the backside gate contact via associated with the backside gate contact is disposed in a trench of an isolation region. Further, under a broad but reasonable interpretation, this satisfies the requirement that the “backside gate contact via associated with the backside gate contact is disposed within a shallow trench isolation (STI) region”. As such, said prior art rejections are maintained and have also been remapped for the sake of clarity of record.
Applicant’s amendment to Claim 19 addressing the rejection under 35 U.S.C. 101 in the reply—filed 31 December 2025—is acknowledged. This rejection has been overcome by the amendment of said claim, and the associated rejection is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 11, 12, 19, 24, & 25 are rejected under 35 U.S.C. 103 as being unpatentable over WEI (US 20220139911 A1) in view of CHANG (US 20210375761 A1).
Regarding Independent Claim 1,
WEI discloses:
A semiconductor structure (Fig. 3S/4E: combined embodiment 338/438; Par. 121) comprising:
a backside power rail (Fig. 3S: 382; Par. 111);
a backside signal line (Fig. 4E: 482; Par. 128);
a frontside signal line (Fig. 3S/4E: 376; Par. 99);
a first source-drain region (Fig. 3S/4E: right 366; Par. 89);
a second source-drain region (Fig. 3S/4E: left 366; Par. 89);
at least one channel (Fig. 3S/4E: 375-1/475-1; Par. 95/124) coupling the first and second source-drain regions;
a gate (Fig. 3S/4E: 371-2; Par. 124) adjacent the at least one channel;
a frontside signal connection from the frontside signal line to [at least one other component of the semiconductor structure] (Par. 99);
a power connection (Fig. 3S: 383; Par. 108) from the backside power rail to the second source-drain region; and
a backside gate contact (Fig. 4E: 371-2/483; Par. 124/125) from the gate to the backside signal line,
wherein a backside gate contact via (Fig. 4E: the opening between the 364 sidewalls, containing 483) associated with the backside gate contact is disposed within a shallow trench isolation (STI) region (Fig. 4E: the opening between the 380 sidewalls, containing the 364s and 483. See “Response to Arguments” for further explanation.).
WEI does not disclose:
a frontside signal connection from the frontside signal line to the first source-drain region;
CHANG discloses:
a frontside signal connection (Fig. 28C: leftmost 112; Par. 67) from the frontside signal line (Fig. 28C: 120; Par. 67) to the first source-drain region (Fig. 28C: leftmost 92; Par. 92);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of WEI with those of CHANG to enable a frontside signal connection from the frontside signal line to the first source-drain region in WEI according to the teachings of CHANG, as WEI discloses a frontside signal line, a first source-drain region, and further discloses that the frontside signal line may connect to various components of the semiconductor structure (WEI Par. 99). However, WEI does not explicitly disclose the frontside signal line—or any other current-driving connection—may connect to the first source-drain region, which is known in the art to be required for a functional semiconductor device of this nature. Therefore, a person having ordinary skill in the art would look to the prior art for the details of such a connection recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the frontside signal connection of CHANG meets these criteria, as CHANG and WEI both disclose similar device structures.
Regarding Claim 2,
WEI discloses:
The semiconductor device of Claim 1,
the gate has a length (Fig. 4E: the length in the x-direction of 372) and wherein the backside gate contact has a bottom dimension (Fig. 4E: the length in the x-direction of 483) larger than the gate length.
Regarding Claim 5,
WEI discloses:
A semiconductor array structure (Fig. 5A; Par. 135) comprising:
a substrate (Fig. 5A: 2000; Par. 135);
a plurality of field effect transistors (Fig. 3S/4E: combined embodiment 338/438; Par. 121) located on the substrate (Par. 135), each comprising
a first source-drain region (Fig. 3S/4E: right 366; Par. 89),
a second source-drain region (Fig. 3S/4E: left 366; Par. 89),
at least one channel (Fig. 3S/4E: 375-1/475-1; Par. 95/124) coupling the first and second source-drain regions, and
a gate (Fig. 3S/4E: 371-2; Par. 124), having a gate length (Fig. 4E: the length in the x-direction of 372), and being adjacent to the at least one channel,
the plurality of field effect transistors being arranged in rows (Fig. 5A: the 2002s—which may each comprise a plurality of field effect transistors—Par. 135—are arranged in rows.);
a plurality of frontside signal lines (Fig. 3S/4E: 376; Par. 99) on a front side (Fig. 3S/4E: the bottom) of the plurality of field effect transistors;
a plurality of backside power rails (Fig. 3S: 382; Par. 111) on a back side (Fig. 3S: the top) of the plurality of field effect transistors;
a plurality of backside signal wires (Fig. 4E: 482; Par. 128) on the back side of the plurality of field effect transistors;
a plurality of frontside signal connections from the plurality of frontside signal lines to [at least one other component of the semiconductor structure] (Par. 99);
a plurality of power connections (Fig. 3S: 383; Par. 108) from the backside power rails to the second source-drain regions; and
a plurality of backside gate contact connections (Fig. 4E: 371-2/483; Par. 124/125) from the backside signal wires to the gates, the backside gate contact connections each having
a bottom dimension (Fig. 4E: the length in the x-direction of 483) larger than the gate length,
wherein a backside gate contact via (Fig. 4E: the opening between the 364 sidewalls, containing 483) associated with each backside gate contact connection of the plurality of backside gate contact connections is disposed within a shallow trench isolation (STI) region (Fig. 4E: the opening between the 380 sidewalls, containing the 364s and 483. See “Response to Arguments” for further explanation.).
WEI does not disclose:
a plurality of frontside signal connections from the plurality of frontside signal lines to the first source-drain regions;
CHANG discloses:
a frontside signal connection (Fig. 28C: leftmost 112; Par. 67) from the frontside signal line (Fig. 28C: 120; Par. 67) to the first source-drain region (Fig. 28C: leftmost 92; Par. 92);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of WEI with those of CHANG to enable a plurality of frontside signal connections from the plurality of frontside signal lines to the first source-drain regions in WEI according to the teachings of CHANG, as WEI discloses a plurality of frontside signal lines, first source-drain regions, and further discloses that the plurality of frontside signal lines may connect to various components of the semiconductor array structure (WEI Par. 99). However, WEI does not explicitly disclose the plurality of frontside signal lines—or any other current-driving connections—may connect to the first source-drain regions, which are known in the art to be required for a functional semiconductor array structure of this nature. Therefore, a person having ordinary skill in the art would look to the prior art for the details of such a connection recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the frontside signal connection of CHANG meets these criteria, as CHANG and WEI both disclose similar device structures of which the semiconductor array structure of WEI is comprised.
Regarding Claim 11,
WEI discloses:
The semiconductor array structure of claim 5,
wherein the channels comprise nanosheet channel regions (Fig. 4E: 475-1, 475-2, 475-3; Par. 124); and the gates comprise all-around gate (As seen in Fig. 3S/4E; Par. 96).
Regarding Claim 12,
WEI discloses:
The semiconductor array structure of claim 5, further comprising:
and a power supply coupled to the plurality of backside power rails.
(Par. 16 teaches 482 may provide power to 477. Therefore, a power supply may be coupled to the 482 of each of the plurality of 477s.)
WEI and CHANG do not disclose:
a first signal source coupled to the plurality of backside signal wires; a second signal source coupled to the plurality of frontside signal lines;
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to enable a first signal source to be coupled to the plurality of backside signal wires; a second signal source to be coupled to the plurality of frontside signal lines in WEI, as such connectivity is known in the art to be required for the standard operation of such field effect transistors.
Regarding Claim 19,
WEI discloses, just as for Claim 5:
[A semiconductor array structure comprising:]
a substrate;
a plurality of field effect transistors located on the substrate, each comprising
a first source-drain region,
a second source-drain region,
at least one channel coupling the first and second source-drain regions, and
a gate having a gate length adjacent the at least one channel,
the plurality of field effect transistors being arranged in rows;
a plurality of frontside signal lines on a front side of the plurality of field effect transistors;
a plurality of backside power rails on a back side of the plurality of field effect transistors;
a plurality of backside signal wires on the back side of the plurality of field effect transistors;
a plurality of frontside signal connections from the plurality of frontside signal lines to [at least one other component of the semiconductor structure];
a plurality of power connections from the backside power rails to the second source-drain regions; and
a plurality of backside gate contact connections from the backside signal wires to the gates, the backside gate contact connections each having
a bottom dimension larger than the gate length,
wherein a backside gate contact via associated with each backside gate contact connection of the plurality of backside gate contact connections is disposed within a shallow trench isolation (STI) region.
(Note, the claim mapping above is identical to Claim 5.)
WEI does not disclose:
A hardware description language (HDL) design structure encoded on a non-transitory machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a semiconductor array structure, wherein the HDL design structure comprises: [the claimed semiconductor array structure].
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to enable a hardware description language (HDL) design structure encoded on a non-transitory machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a semiconductor array structure, wherein the HDL design structure comprises: the claimed semiconductor array structure in WEI for the further advantage of aiding in the research and development of said claimed semiconductor array structure.
WEI does not disclose:
a plurality of frontside signal connections from the plurality of frontside signal lines to the first source-drain regions;
CHANG discloses:
a frontside signal connection (Fig. 28C: leftmost 112; Par. 67) from the frontside signal line (Fig. 28C: 120; Par. 67) to the first source-drain region (Fig. 28C: leftmost 92; Par. 92);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of WEI with those of CHANG to enable a plurality of frontside signal connections from the plurality of frontside signal lines to the first source-drain regions in WEI according to the teachings of CHANG, as WEI discloses a plurality of frontside signal lines, first source-drain regions, and further discloses that the plurality of frontside signal lines may connect to various components of the semiconductor array structure (WEI Par. 99). However, WEI does not explicitly disclose the plurality of frontside signal lines—or any other current-driving connections—may connect to the first source-drain regions, which are known in the art to be required for a functional semiconductor array structure of this nature. Therefore, a person having ordinary skill in the art would look to the prior art for the details of such a connection recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the frontside signal connection of CHANG meets these criteria, as CHANG and WEI both disclose similar device structures of which the semiconductor array structure of WEI is comprised.
Regarding Claim 24,
WEI discloses:
The design structure of Claim 19, wherein:
the channels comprise nanosheet channel regions (Fig. 4E: 475-1, 475-2, 475-3; Par. 124); and the gates comprise all-around gates (As seen in Fig. 3S/4E; Par. 96).
Regarding Claim 25,
WEI discloses:
The design structure of Claim 19, further comprising:
and a power supply coupled to the plurality of backside power rails.
(Par. 16 teaches 482 may provide power to 477. Therefore, a power supply may be coupled to the 482 of each of the plurality of 477s.)
WEI and CHANG do not disclose:
a first signal source coupled to the plurality of backside signal wires; a second signal source coupled to the plurality of frontside signal lines;
Regardless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to enable a first signal source to be coupled to the plurality of backside signal wires; a second signal source to be coupled to the plurality of frontside signal lines in WEI, as such connectivity is known in the art to be required for the standard operation of such field effect transistors.
Claims 3, 6, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over WEI in view of CHANG and in further view of THEN (US 20220102344 A1).
Regarding Claim 3,
WEI discloses:
The semiconductor device of Claim 2,
wherein the gate comprises a high-K metal gate and
(Fig. 4E: 372 is a metal—Par. 95—and 374 may be a high-K dielectric—Par. 95 & 47)
wherein the backside gate contact includes a…portion of the high-K metal gate.
(Fig. 4E: 371-2/483 includes 371-2, which includes 372 and 374)
WEI and CHANG do not disclose:
wherein the backside gate contact includes a T-shaped portion of the high-K metal gate.
THEN discloses:
wherein an exemplary gate contact (Fig. 1: 108/182; Par. 84/92) includes a T-shaped portion of the high-K metal gate (Fig. 1: 108; Par. 84).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of WEI with those of THEN to enable the backside gate contact to include a T-shaped portion of the high-K metal gate in WEI according to the teachings of THEN for the further advantage of reducing the electrical resistance of the gate (THEN Par. 83).
Regarding Claim 6,
WEI discloses:
The semiconductor array structure of claim 5,
wherein the gates of the plurality of field effect transistors comprise high-K metal gates
(Fig. 4E: 372 is a metal—Par. 95—and 374 may be a high-K dielectric—Par. 95 & 47)
and wherein the plurality of backside gate contact connections include…portions of the high-K metal gates (Fig. 4E: 371-2/483 includes 371-2, which includes 372 and 374).
WEI and CHANG do not disclose:
wherein the plurality of backside gate contact connections include T-shaped portions of the high-K metal gates.
THEN discloses:
wherein an exemplary gate contact (Fig. 1: 108/182; Par. 84/92) includes a T-shaped portion of the high-K metal gate (Fig. 1: 108; Par. 84).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of WEI with those of THEN to enable the plurality of backside gate contact connections to include T-shaped portion of the high-K metal gates in WEI according to the teachings of THEN for the further advantage of reducing the electrical resistance of the gates (THEN Par. 83).
Regarding Claim 20,
WEI discloses:
The design structure of claim 19,
wherein the gates of the plurality of field effect transistors comprise high-K metal gates
(Fig. 4E: 372 is a metal—Par. 95—and 374 may be a high-K dielectric—Par. 95 & 47)
and wherein the plurality of backside gate contact connections include…portions of the high-K metal gates (Fig. 4E: 371-2/483 includes 371-2, which includes 372 and 374).
WEI and CHANG do not disclose:
wherein the plurality of backside gate contact connections include T-shaped portions of the high-K metal gates.
THEN discloses:
wherein an exemplary gate contact (Fig. 1: 108/182; Par. 84/92) includes a T-shaped portion of the high-K metal gate (Fig. 1: 108; Par. 84).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of WEI with those of THEN to enable the plurality of backside gate contact connections to include T-shaped portion of the high-K metal gates in WEI according to the teachings of THEN for the further advantage of reducing the electrical resistance of the gates (THEN Par. 83).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898