Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-9 and 16-20 are objected to because of the following informalities: Claims 1, 6, 16, “S/D” is unclear whether it is being referred to “source/drain”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0342618 A1), in view of Ebrish et al. (US 2019/0296142 A1).
[Yang et al. (US 2015/0162405 A1), hereinafter referred to as Yang, is herein used as an evidentiary reference.]
Regarding claim 10, Chen et al. disclose a method for forming a fin field effect transistor (FinFET) device structure in figs. 1-4, comprising: forming an isolation structure [12] over a substrate [10]; forming a first dielectric layer [16] over the isolation structure; forming a gate structure [20] in the first dielectric layer; forming a first trench [42] in the first dielectric layer, wherein the first trench has a first depth; forming a first doped region [14] below the first trench [42]; forming a first contact structure[42a] in the first trench.
Chen et al. differs from the claimed invention by not showing a method of forming a second trench through the first dielectric layer and the isolation structure, wherein the second trench has a second depth, and the second depth is greater than the first depth; forming a second doped region below the second trench; and forming a deep contact structure in the second trench, wherein a bottom surface of the deep contact structure is lower than a bottom surface of the gate structure, and the bottom surface of the deep contact structure is coplanar with an interface between the isolation structure and the substrate.
Ebrish et al. discloses a method of forming a second trench (a hole formed in [1004], [802], [602] and [502] which occupy by [1010]) through the first dielectric layer ([1004], [802]) and the isolation structure [502], wherein the second trench has a second depth, and the second depth is greater than the first depth (thickness of [1004, 802]); forming a second doped region [402] below the second trench; and forming a deep contact structure [1010] in the second trench, wherein a bottom surface of the deep contact structure [1010] is lower than a bottom surface of the gate structure [702, 704], and the bottom surface of the deep contact structure [1010] is coplanar with an interface between the isolation structure [502] and the substrate [102, 402] in fig. 10.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have deep contact structure of Ebrish et al. in Chen et al. because additional contact points can improve threshold voltage control and reducing dopant diffusion (see evidentiary reference Yang [0024] and [0036], additional contacts that are coupled to a doped region on a finFET may be used to "provide enhanced threshold voltage control and reduced dopant diffusion"). And the combination is simple substitution of one known element for another to obtain predictable results, i.e., one known peripheral region of a finFET transistor for another to obtain predictable results; see MPEP 2143 (I)(B).
Regarding claim 11, the combined device of Chen et al. and Ebrish et al. differs from the claimed invention by not showing a method of forming a metal silicide layer in the second doped region.
Chen et al. discloses a method of forming a metal silicide layer [48] in a doped region [14] in fig. 3.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have the metal silicide layer of Chen et al. in the second doped region of Ebrish et al. because it would reduce the contact resistance between the contact and doped region.
Regarding claim 15, the combination of Chen et al. and Ebrish et al. disclose the method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 10, further comprising (see Chen et al.): forming a fin structure (element 10a, see [0015] "the transistor shown in FIG. 1 is a p-type finFET, wherein the isolation structure 12 is recessed to be lower than the upper surface of the active area 10a") over the substrate; forming a source/drain (S/D) structure (element 14, see [0015] "source/drain region 14") in the fin structure (Fig. 1); and
forming the S/D contact structure [42a] over the S/D structure (Fig. 4), wherein the S/D contact structure is electrically connected to the S/D structure (Fig. 4).
Claims 12-14 are rejected under 35 USC 103 as obvious over Chen et al. (US 2018/0342618 A1) in view of Ebrish et al. (US 2019/0296142 A1), further in view of Wu et al. (US 2015/0332963 A1).
Regarding claim 12, the combination of Chen et al. and Ebrish et al. disclose the method for forming the fin field effect transistor (FinFET) device structure according to claim 10, further comprising: forming a second dielectric layer (see Chen 1: element 18a, see [0017] "buffer layer 18a or an additional dielectric layer comprising oxide or nitride) over the first dielectric layer (see Chen Fig. 1).
The combination of Chen et al. and Ebrish et al. fails to explicitly disclose forming an etching stop layer over the second dielectric layer; and forming a third dielectric layer over the etching stop layer, wherein the first trench and the second trench penetrates into and through the second dielectric layer.
Wu et al. discloses additional dielectric layers formed on top of existing dielectric layers (see Fig. 2 and [0020] "stack 112 includes bottom hard mask layer 114, a layer 118 of one or more dielectric materials over the bottom hard mask layer, and a top hard mask layer 120"; "possible materials for the bottom hard mask include [...] carbon doped oxide dielectric"), wherein first and second trenches penetrate into and through a second dielectric layer (elements 122 and 124, see fig. 6 and [0029] "trenches 122 and 124").
The dielectric layer stack and trench formations of Wu is incorporated as additional dielectric layer stack and trench formations of Chen et al. (Chen et al.: see Figs. 1-4 and [0015] "p-type finFET") and Ebrish et al. (element 1010, see Fig. 10, see [0064] "contacts 1006, 1008, and 1010 are formed by first patterning contact trenches in the ILD 1004, and then filling the contact trenches with a suitable contact metal. "), wherein the combination discloses forming an etching stop layer over the second dielectric layer; and forming a third dielectric layer over the etching stop layer, wherein the first trench and the second trench penetrates into and through the second dielectric layer.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Wu et al. with Chen et al. and Ebrish et al. because the combination allows for more selective etching control with more dielectric layers during the formation of the trenches. And the combination is simple substitution of one known element for another to obtain predictable results, i.e., one known dielectric layers of a finFET transistor for another to obtain predictable results; see MPEP 2143 (I)(B).
Regarding claim 13, the combination of Chen et al., Ebrish et al. and Wu et al. disclose the method for forming the fin field effect transistor (FinFET) device structure according to claim 12, further comprising (see Wu et al.): forming a first opening (element 124, see [0029] "trenches 122 and 124") through the etching stop layer and the third dielectric layer (see annotated Figs. below), wherein the second dielectric layer is exposed by the first opening (see annotated Figs. below); forming a second opening (element 122, see [0029] "trenches 122 and 124") through the third dielectric layer, the etching stop layer and the second dielectric layer (see annotated Fig. 6); enlarging the first opening to form the first trench (element 130, see Fig. 7); and enlarging the second opening to form the second trench (element 134, see Fig. 7).
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Regarding claim 14, the combination of Chen et al., Ebrish et al. and Wu et al. disclose the method for forming the fin field effect transistor (FinFET) device structure according to claim 13, further comprising (see Wu et al.): wherein the first dielectric layer is exposed by the second opening (element 134, see Fig. 7).
Response to Arguments
Applicant’s arguments with respect to claims 10-15 have been considered but are moot because the new ground of rejection.
Claims 1-9 and 16-20 are objected but would be allowable if rewritten to overcome the objection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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