DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Response to Arguments
Applicant's arguments filed dated 11/28/2025 have been fully considered but they are not persuasive. In brief, said arguments allege that the cited prior fails to teach the newly introduced claim limitation that the previously claimed, and thus previously rejected, “a first reference memory cell and a second reference memory cell” now are claimed to be “in a same subarray of the memory array.” Whether or not the prior art teaches said first reference memory cell and a second reference memory cell in a same subarray of the memory array” is not the point. Firstly, it must be evident that the claim limitation finds support in the specification/drawings of the present Application. The arguments presented dated 11/28/2025 do not offer any guidance pointing to an specific location in the specification and/or drawings where this in a same subarray of the memory array claim limitations finds support. All of the drawings, except FIGS. 7A, 7B and 8, illustrate artistic renditions of schematics of the invention of the present Application. In fact, at least FIGS. 1-2 are block diagrams illustrating an artistic rendition of the invention. FIGS. 7A, 7B are illustrations of methodologies in flowchart rendition, while FIG. 8 is an artistic rendition of current distributions, certainly nothing to do with array or sub-arrays.
The specification is completely silent on any description of subarrays or sub-arrays, or any other similar descriptor that could even tangentially provide like meaning. The specification limits to disclose an integrated circuit (IC) comprising a memory array, and that the IC includes reference cells, as found in at least [0005]. Additionally, at east [0025-0026] disclose, as illustrated in FIG. 1, an NVM device 100 having a differential reference cell arrangement; plurality of memory cells 104-1 to 104-P organized into bitcell array 102; and that the NVM device 100 may be provided with differential reference cells 118-1 to 118-M. FIG. 1 itself illustrates an artistic rendition of the NVM device 100. It illustrates an array 102 that includes in the array memory cells 104-1 to 104-P and reference cells 118-1 to 118-M. FIG. 2 illustrates similarly. If the illustration and description thereof of FIGS. 1 and 2 are sufficient to provide support for the newly introduced claim limitation of “in a same subarray of the memory array, then, the previously cited prior art to Yang (US 20210350860), as found in at least FIGS. 2-3 provide evidence anticipating this newly introduced claim limitation. FIG. 2 of Yang discloses a memory array 200; it discloses that array 200 includes memory cell sub-array GC1-GC16 and reference cell sub-array Ref0-Ref1. While FIG. 3 provides much the same: memory cells GC1-1 and sub-array of reference cells Ref0 and Ref1 within the same circuit 300. As found in at least [0038] of Yang: “Circuit 300 is used to illustrate how circuit 100 in FIG. 1 is used in conjunction with memory array 200 in FIG. 2. For illustration, segment GC1-1 of segment GC1 of memory array 200 is used with segments Ref0 and Ref1, and is shown.”
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20210350860 to Yang (“Yang”).
Examiner’s Note: Analysis found in section (1) above is reference herein and made part integral of the claim rejection.
As to claim 1, Yang teaches An integrated circuit (As found in at least FIGS. 1-5), comprising: a memory array (As found in at least FIG. 2 and at least [0033]) including a plurality of bitcells addressable by wordlines and array bitlines (As found in at least FIG. 3 and at least [0040-0042]); a differential reference cell directly electrically connected to a corresponding one of the wordlines, the differential reference cell comprising a first reference memory cell and a second reference memory cell in a same subarray of the memory array (As found in at least FIGS. 1 and 3: differential CRef0 and CRef1 directly connected to a word line, one of plurality of WL, also see at least [0040], [0041]; as found in at least FIGS. 2-3, first and second reference cells are found in a sub-array, Ref0-Ref1, of the memory array 200), the first reference memory cell operable to produce a first current and the second reference memory cell operable to produce a second current (As found in at least FIGS. 1 and 3: first reference current Iref0 and second reference current IRef1); a reference current generator configured to receive the first and second currents via respective first and second current paths and to output a reference current that is a fraction less than unity of a sum of the first current and the second current (As found in at least FIGS. 1 and 3: reference current generator 110 receives IRef0 and IRef1, sums them up and produces reference current Iref; also see at least [0020-00250); and a differential sense amplifier configured to receive the reference current and a bit current corresponding to a selected one of the bitcells directly connected to the corresponding one of the wordlines, and to output a read bit value corresponding to the selected one of the bitcells in response to the reference current and the bit current (As found in at least FIGS. 1 and 3: differential sense amplifier 120 receives both Iref and bitcell current Icell, and outputs value at node N0 based on comparison of Iref and Icell; the bit current Icell corresponds to a selected bitcell, Fcell, directly connected to one of the wordlines WL).
As to claim 2, see rejection to at least claim 1; moreover, see at least FIG.1: Iref0 corresponds to cell Cef0 and Iref1 corresponds to cell CRef1; also see at least [0018-0021]; also see at least [0032]).
As to claim 3, Yang teaches wherein the reference current generator is configured to output the reference current as approximately one-half of the sum of the first current and the second current (As found in at least FIGS. 1 and 3, and corresponding text in the reference; also see at least [0024-0025]).
As to claim 4, Yang teaches wherein the corresponding one of the wordlines is a first one of the wordlines and the differential reference cell is a first differential reference cell, further comprising a second differential reference cell electrically connected to a corresponding second one of the wordlines, the second differential reference cell comprising a third reference memory cell and a fourth reference memory cell, the third reference memory cell operable to produce a third current and the fourth reference memory cell operable to produce a fourth current, the reference current generator configured to receive a sum of the first and third currents via the first current path and to receive a sum of the second and fourth currents via the second current path (As found in at least FIGS. 2-3; also see at least [0035-0036]).
As to claim 5, Yang teaches wherein the plurality of bitcells and the differential reference cell are formed from NMOS devices (As found in at least FIGS. 1 and 3: bitcells and corresponding reference cells formed from NMOS devices and PMOS devices; note that at least FIG. 6A of the drawings of the present Application disclose reference cells formed not only by NMOS devices, but also PMOS devices; similarly, [0038] of the specification of the present Application discloses “example reference current generators that may be deployed in association with PMOS-based and NMOS-based DRC arrangements”).
As to claim 6, Yang teaches wherein the plurality of bitcells and the first and second reference memory cells each comprise a corresponding floating gate storage device coupled in series with a wordline select device. (As found in at least FIGS. 1, 3 and 4, reference cells Cref0, Cref1 and bitcell Fcell comprise floating gate storage: flash floating gate cell as found in at least FIG. 4, in series with a wordline select device WL; also see [0050]: “When both word line WL and control gate CG are activated, for example with a high logical value, memory cell Fcell is activated.”).
As to claim 7, Yang teaches wherein the first and second reference memory cells of the differential reference cell are configured to alternate between the respective logic states for each erase and program cycle applied to at least a proper subset of the bitcells that are connected to the corresponding one of the wordlines (As found in at least [0018]; see the Abstract and at least [0041-004]).
As to claim 8, Yang teaches wherein the first and second reference memory cells and the bitcells connected to the corresponding wordline are formed contemporaneously in a same fabrication operation (As found in at least FIGS. 1-5 and as found at least in [0014], and inherent to the manufacturing of devices found in at least FIGS. 1 and 3, these are devices formed contemporaneously in a same fabrication operation of a semiconductor device).
As to claim 9, see rejection to at least claim 1; moreover, Yang teaches, inter alia, a plurality of memory cells organized into M wordlines and N array bitlines, as found in at least FIG. 3 and [0040]).
As to claim 10, see rejection to at least claim 2; moreover, Yang teaches wherein the reference current generator comprises a current mirror block configured to generate a scalable ratio of a total current from the differential reference cell as the reference current, the total current comprising a sum of a first current generated on the first reference bitline and a second current generated on the second reference bitline (As found in the rejection to at least claim 1; and moreover, as found in at least FIG. 1: current mirror as set forth by at least pair P10/P20 and P30/P40 generate scalable current reference Iref from Iref0 and Iref1).
As to claim 11, Yang teaches wherein the current mirror block comprises a current divider for providing the reference current as approximately half of the total reference cell current (As found in at least [0024-0025]).
As to claim 12, see rejection to at least claim 7.
As to claim 13, see rejection to at least claim 8.
As to claim 14, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus; moreover, the semiconductor device as found in at least FIGS.1 and 3 is formed, inherent in the art, upon a semiconductor substrate).
As to claim 15, see rejection to at least claim(s) 10-11.
As to claim(s) 16-17, see rejection to at least claim 5.
As to claim 18, see rejection to at least claim 6.
As to claim 19, see rejection to at least claim 7.
As to claim 20, see rejection to at least claim 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210350860 to Yang (“Yang”) in view of U.S. Patent/Publication No. 20200117836 to Garbe et al. (“Garbe”).
As to claim 6, Yang teaches substantially the claimed invention, including wherein the plurality of bitcells and the first and second reference memory cells each comprise a corresponding floating gate storage device coupled in series with a wordline select device (see at least FIG. 4 in Yang).
Moreover, and alternatively, Garbe also teaches wherein the plurality of bitcells and the first and second reference memory cells each comprise a corresponding floating gate storage device coupled in series with a wordline select device (As found in FIG. 3: memory cells comprising a floating gate storage device 322 in series with a wordline select device 302; also see at least [0039])
Yang and Garbe are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: flash memory devices that may include a floating device and a select device.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Yang as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Garbe also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: each of the cells, be it reference cells or bit cells in Yang may be replace by the pair of device 302 and 322 in FIG. 3 in Garbe. Note that the cell in FIG. 4 in Yang includes a select word line device WL, a flash memory device control gate CG; similarly, the cell in FIG. 3 of Garbe includes a select word device 302 having a word line WL, and a floating gate storage device 322 having a control gate 356.
Therefore, it would have been obvious to combine Yang with Garbe to make the above modification.
As to claim 18, see rejection to at least claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20210375333.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827