Prosecution Insights
Last updated: October 02, 2026

Examiner: HIDALGO, FERNANDO N

Tech Center 2800 • Art Units: 2825 2827

This examiner grants 93% of resolved cases

Analysis

Examiner Fernando N. Hidalgo is assigned to Art Unit 2825 within Tech Center 2800. The data shows 1227 resolved cases for this examiner. An allowance rate of 93.4 percent is recorded for these matters. The median time to allowance is 633 days. These statistics offer a perspective on the prosecution results and timelines associated with this examiner. The 1227 resolved cases provide the foundation for the metrics presented. This volume of work allows for a further review of examiner tendencies.

The interview lift is 1.3 percent. This 1.3 percent lift can be compared to the 93.4 percent allowance rate to evaluate the effect of interviews. Practitioners may use the 633 days median to plan for the length of the prosecution cycle. In Art Unit 2825, the interview lift indicates how outcomes change when an interview occurs. This analysis of resolved cases helps in understanding the examiner's historical patterns. The relationship between the grant frequency and the impact of verbal communication is a central element of this profile.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

93.4%
Allow Rate
+25.4% vs TC avg
1,240
Total Applications
+1.3%
Interview Lift
633
Avg Prosecution Days
Based on 1227 resolved cases, 2023–2026

Rejection Statute Breakdown

3.3%
§101 Eligibility
17.7%
§102 Novelty
37.0%
§103 Obviousness
24.1%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18967166 SCAN REGISTER CIRCUIT GENERATING POSITION INDEX SIGNAL THROUGH FAIL-BIT SCAN OPERATION AND MEMORY DEVICE INCLUDING THE SAME Non-Final OA Samsung Electronics Co., Ltd.
19062762 COMPUTATIONAL STORAGE SYSTEM, METHOD OF OPERATING THEREOF, AND ELECTRONIC SYSTEM Non-Final OA Yangtze Memory Technologies Co., Ltd.
19036332 IMPEDANCE CALIBRATION CIRCUIT, MEMORY CONTROLLER INCLUDING THE IMPEDANCE CALIBRATION CIRCUIT AND MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER Non-Final OA SK hynix Inc.
19033775 MEMORY DEVICE AND METHOD OF APPLYING PASS VOLTAGE Non-Final OA SK hynix Inc.
19033402 CONTROLLER, MEMORY DEVICE, AND ELECTRONIC DEVICE Non-Final OA SK hynix Inc.
18896156 METHOD OF PROCESSING METADATA AND MEMORY DEVICE PERFORMING THE METHOD Non-Final OA SK hynix Inc.
19042437 MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS Non-Final OA Micron Technology, Inc.
18975658 MEMORY SYSTEM REFRESH Non-Final OA Micron Technology, Inc.
18789059 UNIT CELL STRUCTURE FOR SPIN ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY Non-Final OA Micron Technology, Inc.
19043906 MEMORY CIRCUIT AND METHOD OF OPERATING SAME Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
19009148 BOOSTED WRITEBACK VOLTAGE Non-Final OA Rambus Inc.
19012158 EARLY PROGRAM TERMINATION FOR NAND SLC PROGRAM Non-Final OA Sandisk Technologies, Inc.
18986018 COMBINATION SINGLE-LEVEL CELL PROGRAM MODES TO IMPROVE CELL ENDURANCE Non-Final OA Sandisk Technologies, Inc.
18222735 PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO Non-Final OA SanDisk Technologies LLC
19033306 INTEGRATED IN-MEMORY COMPUTE CONFIGURED FOR EFFICIENT DATA INPUT AND RESHAPING Non-Final OA OpenAI Opco, LLC
18821885 A CONFIGURATION MEMORY CELL Final Rejection Microsemi SoC Corp.
18920207 3D Ferroelectric Memory Structure and Method for Reading-Out the Memory Structure Non-Final OA IMEC VZW

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