DETAILED ACTION
Claims 1, 4, 6-7, 9-11, 13-15, 17-21, and 23-27 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The original disclosure is objected to because of the following informalities:
Paragraphs 14-33 include language included in the claims. Thus, these paragraphs must be corrected in similar ways that the claims were (or are to be) corrected in response to past and/or present objections/112(b) rejections.
The amended disclosure is objected to because of the following informalities:
In paragraph 62 submitted on May 2, 2024, the amended sentence is grammatically incorrect and must be reworded. Specifically, “prioritize…distribute implementation” is grammatically incorrect.
Appropriate correction is required.
Claim Objections
Claim 18 is objected to because of the following informalities:
In the 2nd to last line, replace “unit” with --units--.
Appropriate correction is required.
Claim Interpretation
At least one claim is identified as including non-limiting contingent limitations. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding method claim 1, the profile generating step is based on (contingent upon) data collected from a plurality of compute units. Thus, prior to receiving/collecting this data, the generating step is not performed. If the profile generating step is not performed, then the processing step, which is based on the generated profile, is also not performed, which means that the method broadly only encompasses the receiving step. For this method claim, the examiner recommends claiming a first step of --collecting data from a plurality of different types of hardware compute units, the collected data describing operations of the plurality of types of hardware compute units in processing an intermediate representation primitive;-- and then subsequently claiming --generating, by an intermediate controller circuit, an implementation profile based on the collected data;--. This combination of amendments ensures that all claimed steps are performed by the method.
Regarding method claim 9, the updating step is not performed as part of the method if the data is not yet collected because a profile that is not yet generated cannot be updated. If the recommendation for claim 1 is adopted by applicant, then this interpretation would no longer be applicable.
Regarding method claim 10, the maintenance is not required as part of the method if the data is not yet collected because a profile that is not yet generated cannot be maintained. If the recommendation for claim 1 is adopted by applicant, then this interpretation would no longer be applicable.
Regarding method claim 18, the generating, forming, and processing steps are not required by the method for similar reasoning given for claim 1 above. The examiner recommends claiming a first step of --collecting data from a plurality of different types of hardware compute units, the collected data describing operations of the plurality of different types of hardware compute units in processing an intermediate representation primitive;-- followed by --generating an implementation profile, by an intermediate representation controller circuit, based on the collected data;-- followed by --collecting second data from an additional hardware compute unit made available by communicatively coupling the additional hardware compute unit to the intermediate representation controller circuit;-- followed by --forming an additional implementation profile by the intermediate representation controller circuit based on the collected second data;--. This combination of amendments ensures that all claimed steps are performed by the method.
Regarding method claim 19, as the forming and processing are not required by the method before respective data is collected, the claim covers only performing the processing in real time. If the recommendation for claim 18 is adopted by applicant, then this interpretation would no longer be applicable.
Regarding method claim 20, the limitation set forth therein is not part of the method prior to the data being collected. If the recommendation for claim 18 is adopted by applicant, then this interpretation would no longer be applicable.
Regarding method claims 23-24, the limitations set forth therein are not part of the method prior to the data being collected. If the recommendation for claim 1 is adopted by applicant, then this interpretation would no longer be applicable.
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 1, “hardware compute units in processing an intermediate representation primitive…processing the intermediate representation primitive by a specific hardware compute unit”. Per paragraph 11 of the specification, each of the hardware compute units encompasses a central processing unit, graphics processing unit, and/or floating-point grid array. While a generic parallel processing unit and tensor processing unit are also mentioned, there is no corresponding known or disclosed structure. As such, they are not encompassed by a claimed hardware compute unit unless deemed an equivalent of the other aforementioned structures.
In claims 11 and 18, the hardware compute units are similarly interpreted.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 6-7, 9-11, 13-15, 17-21, and 23-27 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 is directed to a process that recites limitations of generating an implementation profile based on data collected from, and describing operations of, a plurality of different types of hardware compute units in processing an intermediate representation primitive, as well as selecting a specific hardware compute unit from the plurality of different types of hardware compute units based on the implementation profile. These limitations encompass a mental process performed in one’s mind with or without the aid of pen and paper. These limitations are broad enough to encompass a human receiving some data (from some source), and generating a profile for multiple units. For instance, if there are two hardware compute units in a machine and data collected and presented on paper indicates that a first CPU consumed more power during execution and a second CPU consumed less power during execution, a human could profile/categorize the first CPU as a high power CPU and the second CPU as a low power CPU. Then, given a new task to perform having a known characteristic, a user can mentally evaluation/observe/judge which CPU would be desired to execute the new task. For instance, if the new task had high priority, then the user could mentally map this new task to the high power CPU so that more power would be used to complete the task sooner. In other words, the limitations in question amount to a human mentally matching a task to the appropriate resource that will operate in the desired way to execute the task.
This judicial exception is not integrated into a practical application because:a) the additional step of receiving input by a generic controller circuit from a generic
neural network may be seen as either mere instructions to implement the abstract idea or using a computer as a tool to perform an abstract idea. That is, as described above, a human must determine the characteristics of the new task so as to match the new task to a profile of a specific hardware compute unit. This determination involves receiving some input that can be analyzed to determine how the new task is to be performed (e.g. with high power/performance, etc.). Thus, applicant is implementing this receiving of input with generic computer components (controller circuit and neural network), which does not integrate the abstract idea into a practical application. Alternatively, the receiving is deemed to be insignificant extra-solution activity involving receiving data over a network and/or retrieving information from memory, both of which are incidental to the primary mental process and amount to merely a nominal or tangential addition to the claim. Such activity fails to integrate the abstract idea into a practical application. See MPEP 2106.04(d)(I).
b) the additional step of processing the intermediate representation primitive by a specific hardware compute unit amounts to mere instructions to implement the abstract idea and/or using a computer as a tool to perform an abstract idea. That is, while a human can mentally envision/map a task to a specific hardware unit, the corresponding implementation on a computer would be to actually execute/process that task on the specific hardware unit. Applicant is only claiming generic processing by a generic computer, which does not integrate the abstract idea into a practical application. Alternatively, the processing is deemed to be insignificant post-solution activity that would occur after the mental process takes place and amount to a nominal addition to the claim. As such, the processing does not integrate the abstract idea into a practical application for this reason as well.
Claim 1’s additional elements are insufficient to amount to significantly more than the judicial exception because, as stated above, the additional elements that amount to mere instructions or generic computer to implement do not amount to significantly more. With respect to the additional element of receiving the input, such receiving has been deemed by the courts to be well-understood, routine, and conventional activity that does not amount to significantly more (see MPEP 2106.05(d)(II)). Finally, with respect to the processing, Official Notice is taken that processing a task (primitive) with a specific compute unit was well known in the art before applicant’s invention as being well-understood, routine, and conventional. In fact, such is understood to be a fundamental operation of processors. For this reason, the processing also does not amount to significantly more. Thus, these elements, alone or in combination with each other, do not amount to significantly more.
Claim 4 is further expands on what data is received and the receiving, as described above, does not integrate or amount to significantly more.
Claim 6 is further directed to the abstract idea, where, for example, a human could detect the operating conditions of components in the system by analyzing the presented collected data. The fact this this is done by the generic controller circuit does not integrate the idea into a practical application, nor does it amount to significantly more than the abstract idea, alone or in combination with the other additional limitations.
Claim 7 is further directed to the abstract idea and recites no additional element and, thus, not significantly more than the abstract idea. That is, a human can pick from the claimed units.
Claim 9 is further directed to the abstract idea and, thus, not significantly more than the abstract idea. That is, a human can change a profile in any way without anything operating. Claim 9 recites the additional element of the controller circuit, but for similar reasoning set forth above, this element does not integrate the idea into a practical application, nor does it amount to significantly more than the abstract idea.
Claim 10 recites an additional element of maintaining/storing a profile in a control store. Storing a profile is both the use of generic instructions/computer to implement the abstract idea and also conventional extra-solution activity (transmitting data over a network and/or storing information in memory (MPEP 2106.05(d)(II)). Thus, it does not integrate the abstract idea into a practical application, nor does it amount to significantly more, alone or in combination with the other additional limitations.
Claim 11 is generally not patent-eligible for similar reasoning as claim 1. Claim 11 recites further recites various generic module circuits for performing the steps. The controller and modules amount to implementing the abstract idea with mere instructions or using generic computing parts as a tool. As such, these additional circuits, alone or in combination, do not integrate the abstract idea into a practical application, nor do they amount to significantly more.
Claims 13-14 are further directed to the abstract idea and recites no additional element. That is, a human can analyze histograms related to power/performance mentally.
Claim 15 is not eligible for similar reasoning as claims 1 and 6, but also because using the claimed module circuit to select the unit amounts to mere use of a generic computer/instructions to implement the abstract idea.
Claim 17 is not eligible for similar reasoning as claims 1 and 4, but also because using the claimed module circuit to select the unit amounts to mere use of a generic computer/instructions to implement the abstract idea.
Claim 18 is not eligible for similar reasoning as claim 1, where a user can form multiple profiles, one for each compute unit in the system.
Claim 19 is not eligible because applicant is merely claiming that each of the steps takes time. Everything takes time (mental steps, processing, etc.).
Claim 20 is not eligible because it merely expands on the abstract idea. The human can generate profiles mentally while the system unit is not operating, powered off, etc.
Claim 21 recites the additional element of receiving the input from machine learning software. This still amounts to the extra-solution activity described above in the rejection of claim 1, and also amounts to a generic computer/instructions to perform the idea. Thus, there is no integration, and not significantly more.
Claims 23-24 and 26-27 are not eligible because it merely expands the abstract idea by setting forth the types of compute units to be considered by a human.
Claim 25 is not eligible for similar reasoning the receiving step is not eligible in the rejection of claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 6-7, 9-11, 15, 17-20, and 23-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Rossem et al., “Profile-Based Resource Allocation for Virtualized Network Functions”.
Referring to claim 1, Van Rossem has taught a method comprising: generating, by an intermediate representation controller circuit, an implementation profile based on data collected from, and describing operations of, a plurality of different types of hardware compute units in processing an intermediate representation primitive (see the abstract and section III. A circuit generates profiles for various resource configurations by gathering data during operation. The graphs in FIG.3, for instance, show profiles for various CPU configurations while executing their network function primitives. Each different CPU configuration is a different type of hardware compute unit. For instance, from FIG.3, 1.0vCPU corresponds to a single core (or single processor) hardware compute unit, 2.0vCPU corresponds to a multi-core (or multi-processor) hardware compute unit, and 0.75vCPU corresponds to a core (or processor) portion hardware compute unit);
receiving, by the intermediate representation controller circuit, from a neural network, an input identifying how the intermediate representation primitive is to be processed, as specified by the neural network (see the abstract, and sections IV(A)-(B) and (E). An artificial neural network (ANN) can be trained to recommend a resource configuration for a given workload defined by a service level agreement. If the SLA dictates that the workload must be executed based on a set of given parameters, the ANN will output a recommended cheapest resource configuration to realize those parameters. Thus, the ANN will dictate how the workload is to be processed, i.e., using what hardware. Note that this is the only teaching required by Van Rossem to reject the claim whose generating and processing limitations are contingent method steps); invoking processing of the intermediate representation primitive by a specific hardware compute unit of the plurality of hardware compute units, wherein the specific hardware compute unit is selected from the plurality of different types of hardware compute units based on the implementation profile (again, based on the profiles, and the workload input and accompanying SLA, the ANN will cause processing of the workload primitive, when in production, to be processed using a particular hardware compute unit (CPU) configuration (for instance, FIG.3 shows that some networking functions could be executed with various numbers of CPU (from 0.25 CPUs to 8 CPUs)). If the ANN determines that 0.25 CPUs would satisfy the SLA for a given workload, then 0.25 CPUs would be used to process that workload. Thus, the ANN will select one of various types of units (a single core/processor unit, a multi-core/processor unit, a core/processor portion unit, etc.)).
Referring to claim 4, Van Rossem has taught the method of claim 1, wherein the input further identifies a device mask specifying a type of hardware circuitry to be used to process the intermediate representation primitive (because the ANN will output a recommended resource usage, this recommendation is a mask that indicated which CPUs are used, and which are not. For instance, if it is recommended that a particular primitive only needs a single CPU, then this recommendation is essentially masking the remaining CPUs in the system).
Referring to claim 6, Van Rossem has taught the method of claim 1, further comprising detecting, by the intermediate representation controller circuit, operating conditions of the plurality of different types of hardware compute units (as described above, this is part of the profiling process, where the circuit detects how the CPUs are operating (e.g. shown in FIG.3). The first column of section III also sets forth detecting delay, loss, throughput, etc., which relate to conditions experienced by the CPUs. Detecting this operation influences later decisions on appropriate configuration profile for a workload).
Referring to claim 7, Van Rossem has taught the method of claim 1, wherein the plurality of different types of hardware compute units comprise at least two of a central processing unit, a parallel processing unit, a floating point grid array, or a tensor processing unit (see FIG.3, for instance, where the compute units comprise at least two CPUs. Alternatively, multiple vCPUs correspond to multiple parallel CPUs (parallel processing units)).
Referring to claim 9, Van Rossem has taught the method of claim 1, further comprising updating, by the intermediate representation controller circuit, the implementation profile offline (at the top of p.1376, Van Rossem sets forth “profiling prior to deployment in production”. Additionally, section III on the same page (among others) makes it clear that the profile creation/updates are occurring during testing based “expected values possible in the production environment”. Hence, profile updates are occurring offline, during testing, before the system is actually used in production. Alternatively, due to contingent method steps, this limitation is not required by Van Rossem and claim 9 is rejected for similar reasoning as claim 1).
Referring to claim 10, Van Rossem has taught the method of claim 1. Due to contingent method steps, the limitation set forth by claim 10 is not required by Van Rossem and claim 10 is rejected for similar reasoning as claim 1.
Claims 11 and 15 are rejected for similar reasoning as claims 1 and 6, respectively.
Referring to claim 17, Van Rossem has taught the intermediate representation controller circuit of claim 11, wherein the input further identifies a device mask specifying a type of hardware circuitry to be used to process the intermediate representation primitive and the actuator module circuit is configured to select the specific hardware compute unit from the plurality of different types of hardware compute units based at least in part on the type (for similar reasoning given in the rejection of claim 4, the recommended resource configuration will indicate the type and how many of the type of resources that need to be provided. For instance, a resource of type CPU will be provided as will an amount thereof. Resources that do not need to be indicated will not be indicated and thus masked out).
Claim 18 is partly rejected for similar reasoning as claim 1. Van Rossem has further taught forming an additional implementation profile by the intermediate representation controller circuit based on data collected from an additional hardware compute unit made available by communicatively coupling the additional hardware compute unit to the intermediate representation controller circuit (for instance, FIG.3 shows multiple profiles that are tracked. One includes multiple hardware compute units (e.g. 2, 4, or 8 units)); and processing the intermediate representation primitive by a specific hardware compute unit from among the plurality of different types of hardware compute units and the additional hardware compute unit, wherein the specific hardware compute unit is selected from the plurality of different types of hardware compute unit based on the implementation profile and the additional implementation profile (again, the profile among all profiles would be selected. For instance, if only 1 CPU is needed, then that 1 CPU is selected from among all other computer units, including the additional one, and the 1-CPU profile is selected among all profiles including the additional profile). Alternatively, the examiner notes that claim 18 is rejected for similar reasoning as claim 1 due to contingent method steps (where only the receiving step is required and shared with claim 1).
Referring to claim 19, Van Rossem has taught the method of claim 18, wherein the forming, the receiving, and the processing are performed in real time (all of these steps take actual/real time. For example, see the last paragraph before section IV).
Referring to claim 20, Van Rossem has taught the method of claim 18, wherein the generating is performed offline while at least a portion of the plurality of different types of hardware compute units are idle (as described above, the generation would occur during testing, i.e., offline, when the CPUs are not used in a production environment, i.e., they are idle. Alternatively, the configurations are tested separately (see last paragraph before section IV). As such, when a 4-CPU configuration is tested, for instance, the remaining CPUs would be idle). Alternatively, due to contingent method steps, the limitation set forth by claim 20 is not required by Van Rossem and claim 20 is rejected for similar reasoning as claim 18.
Referring to claim 23, Van Rossem has taught the method of claim 1, wherein the plurality of different types of hardware compute unit include a central processing unit and a graphics processing unit (again, from FIG.3, CPUs are considered. Additionally, the compute units can include a GPU (see Table 1). Thus, there is a collection of hardware compute units of different types. And, data is collected from this overall group. The examiner notes that the claim is broad enough to not require that data be collected from the GPU. Instead, the data merely needs to be collected from the collective group of compute units, even if the data only comes from a subset of those units). Alternatively, due to contingent method steps, the limitation set forth by claim 23 is not required by Van Rossem and claim 23 is rejected for similar reasoning as claim 1.
Referring to claim 24, Van Rossem has taught the method of claim 1, wherein the plurality of different types of hardware compute units include a graphics processing unit (again, from Table 1, the compute units can include a GPU (see Table 1). Thus, along with CPUs, there is a collection of hardware compute units of different types. And, data is collected from this overall group. The examiner notes that the claim is broad enough to not require that data be collected from the GPU. Instead, the data merely needs to be collected from the collective group of compute units, even if the data only comes from a subset of those units). Alternatively, due to contingent method steps, the limitation set forth by claim 24 is not required by Van Rossem and claim 24 is rejected for similar reasoning as claim 1.
Referring to claim 25, Van Rossem has taught the method of claim 1, wherein the input further identifies a goal vector specifying a goal in the processing of the intermediate representation primitive (from the abstract, the SLA dictates the processing goal, e.g. a “targeted performance”. In other words, the SLA establishes a service providing goal that meets a user’s expectations for a given workload).
Claims 26-27 are rejected for similar reasoning as claims 23-24, respectively. However, the alternate rejections of claims 23-24 are not applicable to claims 26-27 because claims 26-27 do not include contingent limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 13-14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Van Rossem in view of the examiner’s taking of Official Notice.
Referring to claim 10 (where contingent steps are addressed), Van Rossem has taught the method of claim 1, but has not taught wherein the implementation profile is maintained as part of writeable microcode in a writeable control store. However, the examiner first notes that the idea of Van Rossem is to train a neural network to automate resource allocation for a given workload based on its SLA. As such, the various profiles correspond to different hardware configurations, which must be realized via software, i.e., hardware alone does not partition and allocate CPUs. This must be caused by instructions. For instance, one group of instructions would be used to assign 0.25 CPUs to the workload, whereas another group of instructions would be used to assign 8 CPUs to the workload. While the instructions are not taught as microcode, Official Notice is taken that microcode was well known in the art before applicant’s invention. Microcode is implemented in high-speed memory (writeable control store). Use of microcode allows for different hardware designs, spanning a wide range of cost and performance, to be architecturally compatible, which reduces the number of software programs that have to be written for each design. Additionally, microcode can reduce the cost to correct bugs in a system because a portion of the microcode could simply be replaced as opposed to changing the hardware itself. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Van Rossem such that the implementation profile is maintained as part of writeable microcode in a writeable control store.
Referring to claim 13, Van Rossem has taught the intermediate representation controller circuit of claim 11, but has not taught wherein the implementation profile describes the operation using histograms. Instead, FIG.3 shows line graphs. However, Official Notice is taken that histograms were well known in the art before applicant’s invention and amount to another representation of data. For example, FIG.3(e), a histogram could instead be made to track the number of packets lost in each range of kpps, instead of loss percentage. This could be done for other network functions and their line graphs as well. In either case, similar information would be available to help a system make a choice on best profile for a given workload. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Van Rossem such that the implementation profile describes the operation using histograms.
Referring to claim 14, Van Rossem, as modified, has taught the intermediate representation controller circuit of claim 13, wherein the histograms describe power consumption or performance (see the rejection of claim 13, where the number of packets lost per kpps range would be indicative of performance).
Referring to claim 21, Van Rossem has taught the method of claim 18, but has not taught wherein receiving the input comprises receiving the input from machine learning software. However, recall that a model can recommend a configuration based on what it has learned from testing. Thus, Van Rossem has taught a machine learning model that provides this input. However, Van Rossem does not explicitly say that it includes software. However, implementing a machine learning model at least partially in software was well known in the art before applicant’s invention. Software is a flexible implementation in that it can be more quickly changed (if desired) than hardware, which would have to be physically rebuilt/replaced. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Van Rossem such that receiving the input comprises receiving the input from machine learning software.
Response to Arguments
On page 9 of applicant’s response (hereafter “the response”), applicant asks that the 101 rejection be withdrawn based on amendments.
The examiner notes that applicant’s amendments do not make the claims subject matter eligible under 101.
On page 10 of the response, applicant argues that the network function virtualization context of Van Rossem is different from the intermediate representation primitive processing environment of claim 1, where the focus is on compiler-level intermediate representations rather than network service virtualization.
The examiner disagrees that there is a difference. The claimed primitive is broad and does not preclude mapping to Van Rossem.
On pages 10-11 of the response, applicant argues that Van Rossem selects different quantities of the same CPU type instead of selecting different types of hardware compute units.
The examiner notes that applicant’s claims are too broad to overcome Van Rossem. While resources of Van Rossem comprising different quantities of the same type is one view, the different quantities could also be viewed as different hardware compute units, such a multi-processor unit, single-processor unit, and processor portion unit.
On page 11 of the response, applicant argues that Van Rossem’s neural network operating to recommend configurations based on SLAs is not that same as the claims neural network identifying how the intermediate representation primitive is to be processed.
This is not persuasive since applicant has not explained why they are different, particularly given the breadth of the limitation in question.
Regarding applicant's traversal of the examiner's taking of Official Notice to reject claims 10 and 13-14, MPEP 2144.03 states that “To adequately traverse such a finding, an applicant must specifically point out the supposed errors in the examiner’s action, which would include stating why the noticed fact is not considered to be common knowledge or well-known in the art. See 37 CFR 1.111(b).” Such reasoning has not been provided by applicant. Therefore, before the examiner provides evidence supporting the Official Notice, the examiner hereby requests applicant provide reasoning why the noticed features were not well known in the art before applicant’s invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183