DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 03/30/2026.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "updating" in line 3. There is insufficient antecedent basis for this limitation in the claims. There is no prior mention of stored data in claim 16 itself or in claims 9 and 15 from which the claim depends. For the sake of compact prosecution, Examiner will interpret this to mean “updating”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 9-12, 14, 17-20 is/are rejected under 35 U.S.C. 102(1) as being anticipated by Nussbaum et al. US 2011/0022857 A1 (hereafter Nussbaum).
Regarding Claim 1, Nussbaum teaches:
A system comprising: a system management unit comprising circuitry configured to: change a power-performance state of a given unit of a plurality of units of a computing system, “The power allocation controller 109 is the functional element that controls allocation of the Thermal Design Point (TDP) power headroom to the on-die or on-platform components. The performance analysis control logic 111 analyzes performance sensitivity of the cores and other computational units as described further herein” [Nussbaum ¶ 19]. “The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state” [Nussbaum ¶ 6].
in response to detection of a condition indicating that a change in available power is required or possible; “The performance of the one or more processing cores may be limited in response to a graphics processing unit (GPU)-bounded application being executed” [Nussbaum ¶ 6]. “Assume a GPU-bounded application is being executed. That is, the application being executed on the GPU is limited by the performance of the GPU, because, e.g., a current performance state is lower than needed for the particular application” [Nussbaum ¶ 43].
wherein the given unit is selected based at least in part on data that indicates, for a given change in power allocated to a respective unit, the given unit is expected to exhibit a change in performance that is greater than or less than a change in performance of one or more other units of the plurality of units. “… responsive to a GPU-bounded application being executed, limiting performance of a first group of one or more of the processing cores forming the subset, the first group having lower performance sensitivity as compared to a second group of one or more of the processing cores, by restricting operation of the first group to a first performance state and allowing operation of the second group in a second performance state higher than the first performance state” [Nussbaum, Claim 8]. “Alternatively, only those cores with the lowest performance sensitivity on frequency may be throttled to the P-state limit. For example, in a four-core system, the two cores with the lowest IPS sensitivity to core frequency change, according to the boost sensitivity table, may be throttled by imposing a P-state Limit=P2, while the state of the other cores may be left unchanged” [Nussbaum ¶ 44].
Regarding Claim 2, Nussbaum teaches:
The system as recited in claim 1, as referenced above.
wherein the data associates workload types with corresponding indications of expected changes in performance for respective unit types in response to changes in power. “The availability of boost sensitivity information can be utilized in various ways by the SOC. CPU throttling is one example of such utilization. Assume a GPU-bounded application is being executed. That is, the application being executed on the GPU is limited by the performance of the GPU, because, e.g., a current performance state is lower than needed for the particular application. In that case, the CPU cores may be throttled (limit their performance) by imposing a P-state limit on all of the cores (for example, P-state Limit=P2 state). That will release power margin available to the GPU. In an embodiment, a GPU-bounded or CPU-bounded application is identified based data indicating how busy a particular core or GPU is” [Nussbaum ¶ 43]. “This numerical difference represents the boost sensitivity for the core. That is, it represents the sensitivity of the core, running that particular process context, to a change in frequency” [Nussbaum ¶ 26].
Regarding Claim 3, Nussbaum teaches:
The system as recited in claim 2, as referenced above.
wherein in response to the condition indicating a decrease in power: “The performance of the one or more processing cores may be limited in response to a graphics processing unit (GPU)-bounded application being executed” [Nussbaum ¶ 6]. “Assume a GPU-bounded application is being executed. That is, the application being executed on the GPU is limited by the performance of the GPU, because, e.g., a current performance state is lower than needed for the particular application” [Nussbaum ¶ 43].
the given unit is selected based at least in part on the data indicating that, for a given decrease in power allocated to a respective unit, the given unit is expected to exhibit a smaller change in performance than one or more other units of the plurality of units when the type of workload is being executed; “This numerical difference represents the boost sensitivity for the core. That is, it represents the sensitivity of the core, running that particular process context, to a change in frequency. The greater the sensitivity, the more performance increase is to be gained by increasing the frequency. The same training shown in FIG. 2 is applied to each of the processor cores and to any other component that can be boosted (over-clocked) above its nominal maximum power value and the values are stored in the boost sensitivity table” [Nussbaum ¶ 26]. “In other embodiments, frequency sensitivity training is applied to all computational units whose frequency can be changed to implement various performance states, regardless of whether they can be clocked (or overclocked) above a nominal power level. In that way, systems can still allocate power budget to cores (or other computational units) that are more sensitive to frequency change and away from cores that are less sensitive to a change in frequency” [Nussbaum ¶ 27].
and a power-performance state of the given unit is decreased. “The availability of boost sensitivity information can be utilized in various ways by the SOC. CPU throttling is one example of such utilization. Assume a GPU-bounded application is being executed. That is, the application being executed on the GPU is limited by the performance of the GPU, because, e.g., a current performance state is lower than needed for the particular application. In that case, the CPU cores may be throttled (limit their performance) by imposing a P-state limit on all of the cores (for example, P-state Limit=P2 state). That will release power margin available to the GPU” [Nussbaum ¶ 43].
Regarding Claim 4, Nussbaum teaches:
The system as recited in claim 2, as referenced above.
wherein in response to the condition indicating an increase in power: “Core0 and Core1 are allocated 16.75 w to improve overall CPU throughput. The operational point (F,V) of both cores may be increased to fill the new power headroom (16.75w instead of 8w ). Alternatively, the power budget of only one core can be increased to 25.5 w, while the other core can be left with an 8w power budget. In such a case, the core with the increased power budget may be boosted to an even higher operational point (F,V), so that the new power headroom (25.5 w) can be exploited. In this specific case, the decision whether to equally boost two cores or provide all available power headroom to one core is dependent on what is the best way to improve the overall SOC performance” [Nussbaum ¶ 23].
the given unit is selected based at least in part on the data indicating that, for a given increase in power allocated to a respective unit, the given unit is expected to exhibit a greater change in performance than one or more other units of the plurality of units when the type of workload is being executed; “This numerical difference represents the boost sensitivity for the core. That is, it represents the sensitivity of the core, running that particular process context, to a change in frequency. The greater the sensitivity, the more performance increase is to be gained by increasing the frequency. The same training shown in FIG. 2 is applied to each of the processor cores and to any other component that can be boosted (over-clocked) above its nominal maximum power value and the values are stored in the boost sensitivity table” [Nussbaum ¶ 26]. “In other embodiments, frequency sensitivity training is applied to all computational units whose frequency can be changed to implement various performance states, regardless of whether they can be clocked (or overclocked) above a nominal power level. In that way, systems can still allocate power budget to cores (or other computational units) that are more sensitive to frequency change and away from cores that are less sensitive to a change in frequency” [Nussbaum ¶ 27].
and a power-performance state of the given unit is increased. “Thus, one embodiment has been described for allocating power to those computational units in the PO state when there is sufficient margin and finding that margin by eliminating those computational units that are less sensitive to a frequency boost. In other embodiments, the frequency boost is only provided, e.g., to those computational units with a sufficiently high boost sensitivity, e.g., above a predetermined or programmable threshold, to warrant the extra power. In that way, increased performance can be provided while still trying to maintain reduced power consumption where possible.” [Nussbaum ¶ 41].
Regarding Claim 6, Nussbaum teaches:
The system as recited in claim 1, as referenced above.
further comprising stored data that indicates, for one or more of the plurality of units and for a given type of workload, an expected change in performance resulting from a change in power allocated to the one or more other units. “The performance analysis control logic again samples and averages core IPC (as reported by the core) in 207. The performance analysis control logic determines a second instructions per second (IPS) metric based on the IPCxCore frequency (the high frequency) and stores the second IPS metric in a temporary register "B". The performance analysis control logic determines the numerical difference between A and B in 209 and stores the result in a performance or boost sensitivity table along with the core number being analyzed and the process context number running on the CPU core during the analysis” [Nussbaum ¶ 25]. “The context number may be determined by the content of the CR3 register or a hash of the CR3 register to allow for a shorter number to be stored. This numerical difference represents the boost sensitivity for the core. That is, it represents the sensitivity of the core, running that particular process context, to a change in frequency” [Nussbaum ¶ 26].
Regarding Claim 9, it is a method type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale.
Nussbaum further teaches A method comprising: changing, by power management circuitry, a power-performance state of a given unit of a plurality of units of a computing system, “The power allocation controller 109 is the functional element that controls allocation of the Thermal Design Point (TDP) power headroom to the on-die or on-platform components. The performance analysis control logic 111 analyzes performance sensitivity of the cores and other computational units as described further herein” [Nussbaum ¶ 19]. “The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state” [Nussbaum ¶ 6].
Regarding Claim 10, it is a method type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale.
Regarding Claim 11, it is a method type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale.
Regarding Claim 12, it is a method type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale.
Regarding Claim 14, it is a method type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale.
Regarding Claim 17, it is a system type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale.
Nussbaum further teaches A system comprising: one or more processors; “For example, while the computational units may be part of a multi-core processor, in other embodiments, the computational units are in separate integrated circuits that may be packaged together or separately. For example, a graphical processing unit (GPU) and processor may be separate integrated circuits packaged together or separately” [Nussbaum ¶ 50].
and a system management unit comprising circuitry configured to: change a power-performance state of a given unit of a plurality of units of the system, “The power allocation controller 109 is the functional element that controls allocation of the Thermal Design Point (TDP) power headroom to the on-die or on-platform components. The performance analysis control logic 111 analyzes performance sensitivity of the cores and other computational units as described further herein” [Nussbaum ¶ 19]. “The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state” [Nussbaum ¶ 6].
Regarding Claim 18, it is a system type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale.
Regarding Claim 19, Nussbaum teaches:
The system as recited in claim 18, as referenced above.
wherein the given unit is one of a central processing unit, a graphics processing unit, and a memory subsystem. “In one embodiment, only two on-die components: core processors and the GPU, may be boosted to a higher performance point. The I/O module and the memory controller may contribute to the boosting process of the cores or the GPU by reallocating their "unused" power budget to these components, but they cannot be boosted themselves” [Nussbaum ¶ 34]. “The availability of boost sensitivity information can be utilized in various ways by the SOC. CPU throttling is one example of such utilization. Assume a GPU-bounded application is being executed. That is, the application being executed on the GPU is limited by the performance of the GPU, because, e.g., a current performance state is lower than needed for the particular application” [Nussbaum ¶ 43].
Regarding Claim 20, it is a system type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Nussbaum et al. US 2011/0022857 A1 (hereafter Nussbaum) in view of Bircher US 2012/0297232 A1 (hereafter Bircher).
Regarding Claim 5, Nussbaum teaches the system as recited in claim 2, as referenced above. Nussbaum fails to explicitly teach wherein the type of workload being executed is determined based at least in part on performance counters in the computing system.
However, Bircher teaches wherein the type of workload being executed is determined based at least in part on performance counters in the computing system. “The measurements obtained by these hardware performance counters may be used to create the frequency sensitivity feedback model during the characterization stage and to determine the value of various metrics during run-time (the run-time stage) … In the characterization stage, various methods of matching the hardware metrics to the frequency sensitivity values of the various workloads may be applied” [Bircher ¶ 73, 74]. “Whether the processing unit is compute-bounded, memory-bounded, or somewhere in between may be determined based on a frequency sensitivity value calculated in real-time. A compute-bounded workload may be defined as a processing workload that is computationally intensive, with infrequent accesses to main memory” [Bircher ¶ 58]. “For example, consider a situation when a compute-bounded workload (i.e., highly frequency sensitive application) …” [Bircher ¶ 77].
Bircher is considered to be analogous to the claimed invention because it is in the same field of power consumption optimization. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nussbaum to incorporate the teachings of Bircher and include that the type of workload being executed is determined based at least in part on performance counters in the computing system. Doing so would allow for the system to track real-time metrics. “In various embodiments, the hardware performance counters and the one or more coefficients from the best-fit regression model may be utilized to calculate the frequency sensitivity of an application executing on the processing unit in real-time” [Bircher ¶ 12]. “While each of workloads 116 and 117 are being executed by processor 105 during a training session, one or more hardware performance counters may also be monitored and measured. The one or more hardware performance counters may measure data and provide feedback related to the performance and operation of processor 105” [Bircher ¶ 35].
Regarding Claim 13, it is a method type claim having similar limitations as claim 5 above. Therefore, it is rejected under the same rationale.
Claims 7, 8, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nussbaum et al. US 2011/0022857 A1 (hereafter Nussbaum) in view of Nasle US 2019/0332073 A1 (hereafter Nasle).
Regarding Claim 7, Nussbaum teaches the system as recited in claim 1, as referenced above. Nussbaum fails to teach wherein subsequent to changing a power-performance state of the given unit, the system management unit is configured to compare an expected performance of the computing system to an actual performance of the computing system.
However, Nasle teaches wherein subsequent to changing a power-performance state of the given unit, the system management unit is configured to compare an expected performance of the computing system to an actual performance of the computing system. “The design stage models, which may be calibrated and updated based on real-time monitored data, are used as a basis for the predicted performance of the system. The real-time monitored data can then provide the actual performance over time. By comparing the real-time time data with the predicted performance information, difference can be identified a tracked by, e.g., the analytics engine 118. Analytics engines 118 can then track trends, determine alarm states, etc., and generate a real-time report of the system status in response to the comparison” [Nasle ¶ 94].
Nasle is considered to be analogous to the claimed invention because it is in the same field of energy efficient computing. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nussbaum to incorporate the teachings of Nasle and include subsequent to changing a power-performance state of the given unit, the system management unit is configured to compare an expected performance of the computing system to an actual performance of the computing system. Doing so would allow for improvement on system monitoring and operational decisions. “Greater efforts at real-time operational monitoring and management would provide more accurate and timely suggestions for operational decisions, and such techniques applied to failure analysis would provide improved predictions of system problems before they occur. That is, an electrical network model that can age and synchronize itself in real-time with the actual facility's operating conditions is critical to obtaining predictions that are reflective of the system's reliability, availability, health and performance in relation to the life cycle of the system” [Nasle ¶ 4, 5].
Regarding Claim 8, Nussbaum teaches the system as recited in claim 7, as referenced above. Nussbaum fails to teach wherein in response to the actual performance being different from the expected performance, the system management unit is configured to update the data.
However, Nasle teaches wherein in response to the actual performance being different from the expected performance, the system management unit is configured to update the data. “Determine whether a difference between the real-time data output and the predicted system data falls between a set value and an alarm condition value, wherein, if the difference falls between the set value and the alarm condition value, a virtual system model calibration request is generated… Determine a difference between a real-time sensor value measurement from a sensor integrated with the monitored system and a predicted sensor value for the sensor. Adjust operating parameters of the virtual system model to minimize the difference.” [Nasle Fig. 6, 7, and 8].
Regarding Claim 15, it is a method type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale.
Regarding Claim 16, it is a method type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale.
Response to Arguments
Applicant's arguments filed 03/30/2026 have been fully considered but they are not persuasive. Applicant argues in substance:
I. Claims 8 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as allegedly being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims have been amended to address the rejections.
a) While the antecedent basis issue within claim 8 has been resolved, the issue persists within claim 16. As detailed in the rejection above, there is no prior mention in the claim or in the claims from which it depends of “the stored data”.
II. As amended, claim 1 recites selection of a unit for a power-performance state change based on a comparison of how changes in power allocated to different units affect system performance. The cited art, taken alone or in combination, does not teach or suggest these features.
In the Office Action, it is admitted that Eckert does not explicitly disclose selection of a unit based on relative power sensitivity to changes in power. The Office Action relies on Dhanwada for teaching "power sensitivity characteristics" and comparison among regions (Office Action at pp. 4-5).
Dhanwada does not disclose this whether taken singly or in combination with Eckert. Dhanwada is directed to analyzing device regions in order to identify regions suitable for power optimization in a design context. Its discussion concerns symbolic analysis, workloads initialized with parameters, modified parameters, power consumption values, modified power consumption values, and determination of a "power sensitivity characteristic" of a region. The cited discussion culminates in identifying a region as a target region for power optimization by a designer. That is fundamentally different from the amended claim's requirement of selecting one of a plurality of units of a computing system for a power-performance state change based on comparative data indicating the expected performance response of multiple units to a given power change.
Stated differently, Dhanwada may discuss whether a region is "power sensitive," but it does not disclose data indicating that, for a specified power change, unit A is expected to undergo a greater or lesser performance change than unit B, and then selecting the unit on that comparative basis. The Office Action effectively equates Dhanwada's "power sensitivity characteristics" with the amended claim's comparative expected performance- change data. That equation is unsupported by the cited text. The amended claim is not satisfied by merely knowing that different regions have different power characteristics, or even that they can be compared generally. The claim requires comparative data tied to: a given power change, and the resulting expected performance change of multiple units. Nothing in the cited portions of Dhanwada discloses that relationship. Nor does the combination cure the deficiency. Eckert provides the system-level power-management context, but Eckert's decision logic is based on operational heuristics such as task readiness, queue state, critical memory requests, and bandwidth-related conditions. Dhanwada, in turn, does not supply the claimed comparative expected perfornance- response data. Combining Eckert's heuristic reallocation approach with Dhanwada's design-time region sensitivity analysis still does not yield the claimed mechanism of10
selecting among multiple units based on data indicating which unit is expected to experience a greater or lesser change in performance for a given power change.
The present amendment therefore narrows the claim in a manner directly responsive to the rejection. The amended claim no longer reads on a generic comparison of "sensitivity" characteristics. Instead, it requires a specific comparative performance- response criterion across multiple units. Because the cited references do not teach or suggest that criterion, the rejection of claim 1 should be withdrawn.
Accordingly, Applicant submits the claims are patentable over the cited art and the application is in condition for allowance, and an early notice to that effect is requested.
a) Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARI F RIGGINS whose telephone number is (571)272-2772. The examiner can normally be reached Monday-Friday 7:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached on (571) 272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.F.R./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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