DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Embodiment 1 of Figures 1A-5A, Claims 1-2 and 4-13 in the reply filed on 11/10/2025 is acknowledged.
Claims 3 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/10/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2020/0006221).
Regarding claim 1, Zhang et al. discloses, as shown in Figures, a microelectronic assembly comprising:
a plurality of vertically stacked dies (102,124);
a trench (114) of dielectric material (120) through the plurality of vertically stacked dies; and
a plurality of conductive vias (130, see Figures 15) extending through the trench of dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies (through 116 of 102,124, [0040]).
Regarding claim 2, Zhang et al. discloses the trench of dielectric material is within an interior portion of the plurality of vertically stacked dies (Figures).
Regarding claim 4, Zhang et al. discloses the trench of dielectric material is one of a plurality of trenches of dielectric material through the plurality of vertically stacked dies (Figures).
Regarding claim 5, Zhang et al. discloses the dielectric material (120) includes silicon and one or more of oxygen, nitrogen, and carbon; a polyimide material; or a low-k or ultra low-k dielectric (polymers, [0026]).
Regarding claim 6, Zhang et al. discloses a material of the plurality of conductive vias includes one or more of copper, nickel, molybdenum, ruthenium, cobalt, polysilicon, and tungsten [0038].
Regarding claim 12, Zhang et al. discloses the plurality of vertically stacked dies includes between 2 and 32 dies [0036].
Regarding claim 13, Zhang et al. discloses the plurality of vertically stacked dies includes between 32 and 128 dies [0036].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0006221) in view of Chen (PN 9,147,672).
Zhang et al. discloses the claimed invention including the assembly as explained in the above rejection. Zhang et al. does not disclose a cross-section dimension of an individual one of the plurality of conductive vias is between 40 nanometers and 5 microns. However, Chen discloses a cross-section dimension of an individual one of the plurality of conductive vias is 2 micron (which is between 40 nanometers and 5 microns). Note Col. 7, lines 54-57 of Chen. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the individual one of the plurality of conductive vias of Zhang et al. having a cross-section dimension as claimed, such as taught by Chen in order to have the desired structure.
Further, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, diameter, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, diameter, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0006221) in view of Veches (PN 10,134712).
Regarding claim 8, Zhang et al. discloses the claimed invention including the assembly as explained in the above rejection. Zhang et al. further discloses the plurality of vertically stacked dies has a first surface and a second surface opposite the first surface. Zhang et al. does not disclose a base die at the first surface of the plurality of vertically stacked dies, the base die electrically coupled to an individual one of the plurality of conductive vias. However, Veches discloses an assembly comprising a base die (not shown, or 120, Col. 2, lines 43-56) at a first surface of a plurality of vertically stacked dies (middle two 110), the base die electrically coupled to an individual one of a plurality of conductive vias. Note Figure 1 of Veches. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the assembly of Zhang et al. having a base die at the first surface of the plurality of vertically stacked dies, the base die electrically coupled to an individual one of the plurality of conductive vias, such as taught by Veches in order to integrate a plurality of die to perform the desired function.
Regarding claim 9, Zhang et al. and Veches disclose the base die is a controller die with logic elements, and the plurality of vertically stacked dies are memory dies (Col. 2, line 43 – Col. 3, line 11 of Veches).
Regarding claim 10, Zhang et al. and Veches disclose the base die (not shown, or 120, Col. 2, lines 43-56) is a first base die, and the microelectronic assembly further including: a second base die (a very top 110, see Figure 1 of Veches) at the second surface of the plurality of vertically stacked dies, the second base die electrically coupled to an individual one of the plurality of conductive vias.
Regarding claim 11, Zhang et al. and Veches disclose the base die (not shown, Col. 2, lines 43-56) includes a first surface and an opposing second surface, wherein the plurality of vertically stacked dies is at the second surface of the base die, and the microelectronic assembly further including: a package substrate (120, Col. 2, lines 43-56) electrically coupled to the first surface of the base die.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897