Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8, 9 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. No. 9653404 to Wang et al. (Wang).
Regarding Claim 1, Wang teaches in Figs. 2-4 at least, a semiconductor die, comprising:
a plurality of overlay marks 306/302, including:
a first overlay mark 302 in region 300G at a first position on the semiconductor die, wherein the first overlay mark includes a first set of patterns 304 in region 300G having a first orientation; and
a second overlay mark 306 in region 300F at a second position on the semiconductor die, wherein the second overlay mark includes a second set of patterns 308 in region 300F having a second orientation, wherein the second orientation is substantially orthogonal to the first orientation, and wherein the second position is non-overlapping with the first position (see Fig. 4 for example, marks/ patterns in region 300F orthogonal to those in 300G;).
Regarding Claim 2, Wang teaches the semiconductor die of Claim 1, further comprising a plurality of layers, wherein individual patterns of the first set of patterns and the second set of patterns are on one of the plurality of layers (see Fig. 3).
Regarding Claim 3, Wang teaches the semiconductor die of Claim 2, wherein:
the plurality of layers includes a first layer and a second layer;
the first set of patterns includes:
a first pattern on the first layer; and
a second pattern on the second layer; and
the second set of patterns includes:
a third pattern on the first layer; and
a fourth pattern on the second layer (see Figs. 3 and 4 for example; each region 300G/F have patterns 304/308 on two different levels).
Regarding Claim 4, Wang teaches the semiconductor die of Claim 3, wherein:
the first pattern, the second pattern, the third pattern, and the fourth pattern are grating patterns;
the first pattern and the second pattern are non-overlapping; and
the third pattern and the fourth pattern are non-overlapping (all patterns shown are grating patterns, none are overlapping).
Regarding Claim 6, Wang teaches the semiconductor die of Claim 2, wherein:
the plurality of layers includes a first layer and a second layer (see Fig. 3);
the first set of patterns includes a first pattern, a second pattern, a third pattern, and a fourth pattern, wherein:
the first pattern and the second pattern are on the first layer; and
the third pattern and the fourth pattern are on the second layer; and
the second set of patterns includes a fifth pattern, a sixth pattern, a seventh pattern, and an eighth pattern, wherein:
the fifth pattern and the sixth pattern are on the first layer; and the seventh pattern and the eighth pattern are on the second layer (each set of patterns corresponding to an overlay mark has patterns corresponding to a first through eighth on the two levels).
Regarding Claim 8, Wang teaches the semiconductor die of Claim 1, wherein individual patterns of the first set of patterns and the second set of patterns have 180° symmetry (see Fig. 2 for example).
Regarding Claim 9, Wang teaches the semiconductor die of Claim 1, wherein:
the first overlay mark and the second overlay mark are one-dimensional overlay marks;
the first overlay mark is for measuring overlay on a first axis corresponding to a first dimension; and
the second overlay mark is for measuring overlay on a second axis corresponding to a second dimension, wherein the second axis is substantially orthogonal to the first axis (the marks of Wang are identical as claimed and are considered one-dimensional, and intended use limitations do not bear weight).
Regarding Claim 17, Wang teaches an electronic device, comprising:
processing circuitry, memory circuitry 4:16-20, or communication circuitry on an integrated circuit die, wherein the integrated circuit die comprises:
a plurality of overlay marks, including:
a first overlay mark at a first position on the integrated circuit die, wherein the first overlay mark includes a first set of patterns having a first orientation; and
a second overlay mark at a second position on the integrated circuit die, wherein the second overlay mark includes a second set of patterns having a second orientation, wherein the second orientation is substantially orthogonal to the first orientation, and wherein the second position is non-overlapping with the first position (see above rejection of Claim 1).
Regarding Claim 18, Wang teaches the electronic device of Claim 17, wherein the integrated circuit die further comprises a plurality of layers, wherein individual patterns of the first set of patterns and the second set of patterns are on one of the plurality of layers (see above).
Regarding Claim 19, Wang teaches the electronic device of Claim 18, wherein: the plurality of layers includes a first layer and a second layer; the first set of patterns includes a first pattern, a second pattern, a third pattern, and a fourth pattern, wherein: the first pattern and the second pattern are on the first layer; and the third pattern and the fourth pattern are on the second layer; and the second set of patterns includes a fifth pattern, a sixth pattern, a seventh pattern, and an eighth pattern, wherein: the fifth pattern and the sixth pattern are on the first layer; and the seventh pattern and the eighth pattern are on the second layer (see above).
Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. No. 10795268 to Chen.
Regarding Claim 1, Chen teaches in Figs. 1A and 3A-3D at least, a semiconductor die, comprising:
a plurality of overlay marks (each grating set in every quadrant of Fig. 1A), including:
a first overlay mark (any set) at a first position on the semiconductor die, wherein the first overlay mark includes a first set of patterns (linear patterns within any set) having a first orientation; and
a second overlay mark (any adjacent grating set of Fig. 1A) at a second position on the semiconductor die, wherein the second overlay mark includes a second set of patterns (linear patterns of that same set) having a second orientation, wherein the second orientation is substantially orthogonal to the first orientation, and wherein the second position is non-overlapping with the first position (see Fig. 1A for example, marks/ patterns in each quadrant are orthogonal to an adjacent one).
Regarding Claim 2, Chen teaches the semiconductor die of Claim 1, further comprising a plurality of layers, wherein individual patterns of the first set of patterns and the second set of patterns are on one of the plurality of layers (see Figs. 3A-3D).
Regarding Claim 3, Chen teaches the semiconductor die of Claim 2, wherein:
the plurality of layers includes a first layer and a second layer;
the first set of patterns includes:
a first pattern on the first layer; and
a second pattern on the second layer; and
the second set of patterns includes:
a third pattern on the first layer; and
a fourth pattern on the second layer (see Figs. 3A-3D for example).
Regarding Claim 5, Chen teaches the semiconductor die of Claim 3, wherein:
the first pattern, the second pattern, the third pattern, and the fourth pattern are grating patterns;
the second pattern is superimposed above the first pattern; and
the third pattern is superimposed above the fourth pattern (see Figs. 3A-3D for example).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of U.S. Pat. Pub No. 20160247766 to Conklin et al. (Conklin).
Regarding Claim 7, Wang teaches the semiconductor die of Claim 6, but does not explicitly teach that:
the first set of patterns is a first set of grating patterns, wherein:
the first pattern has a different design than the second pattern; and
the third pattern has a different design than the fourth pattern; and
the second set of patterns is a second set of grating patterns, wherein: the fifth pattern has a different design than the sixth pattern; and the seventh pattern has a different design than the eighth pattern.
However, in analogous art, Conklin teaches that mark designs can be specifically tuned to be optimized for mark identification [0040] and are therefore result effective, and may be optimized by the person of ordinary skill to meet application specific requirements of overlay accuracy (MPEP 2144.05(II)(B)). It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Conklin to improve overlay measurement accuracy.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Regarding Claim 10, Wang teaches the semiconductor die of Claim 1, but does not explicitly teach that:
the semiconductor die is electrically coupled to a package substrate; and
the package substrate is electrically coupled to a board.
However, it would have been obvious to the person of ordinary skill in the art before the time of filing to do so in order to use the device in application.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of U.S. Pat. Pub No. 20190279940 to Shibazaki et al. (Shibazaki).
Regarding Claim 20, Wang teaches the electronic device of Claim 19, wherein:
the first set of patterns is a first set of grating patterns (patterns shown are grating patterns), but does not explicitly teach that:
the first pattern has a different pitch than the second pattern; and the third pattern has a different pitch than the fourth pattern; and the second set of patterns is a second set of grating patterns, wherein: the fifth pattern has a different pitch than the sixth pattern; and the seventh pattern has a different pitch than the eighth pattern.
However, in analogous art, Shibazaki teaches that the pitch among markings may be used for identification in a mark detection system and may be designed and optimized to meet application specific needs (MPEP 2144.05(II)(B)). It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Shibazaki for improved overlay metrology accuracy.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812