DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant's arguments filed 11/19/2025 with respect to the rejections of claims 21-25 under 35 U.S.C. 102 have been fully considered but they are not persuasive. The broadest reasonable interpretation of the claimed limitation “terminated within the n-type layer” is anticipated by Strachan, as the vertical sides of 320 and 374 are fully enclosed by the n-type layer 304. The claimed limitation is broad enough that 320 and 374 terminating at isolation structures 308 is irrelevant for determining if the p-type buried layers 320 and 374 terminate within n-type layer 304.
Applicant's arguments filed 05/29/2025 with respect to the rejections of claims 1-7 and 9-19 under 35 U.S.C. 103 have been fully considered but they are not persuasive. The broadest reasonable interpretation of the claimed limitation “terminated within the n-type layer” is anticipated by Strachan, as the vertical sides of 320 and 374 are fully enclosed by the n-type layer 304. The claimed limitation is broad enough that 320 and 374 terminating at isolation structures 308 is irrelevant for determining if the p-type buried layers 320 and 374 terminate within n-type layer 304. In response to applicant's argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 83 7 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the stated rationale to combine Strachan with Mallik came from the Examiner's own knowledge generally available to one of ordinary skill in the art.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 21-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Strachan et al. (US 20170200712 A1 – hereinafter Strachan).
Regarding claim 21, Strachan teaches a semiconductor device (Fig.3 300; ¶0032), comprising:
an n-type substrate (Fig.3 302; ¶0033);
an n-type layer (Fig.3 304; ¶0033) on the substrate (302);
a p-type layer (Fig.3 306; ¶0033) over the n-type layer (304), the p-type layer (306) including a first dopant concentration (inherent feature of p-type doped layer 306; ¶0012) and a surface (Fig.3 324; ¶0034) facing away from the substrate (302);
a first diode area (Fig.3 314; ¶0034) having a first side (left side of area 314) and a second side (right side of area 314) opposite to the first side (left side of area 314);
a second diode area (Fig.3 316; ¶0032) proximate to the first side (left side of area 314);
a third diode area (Fig.3 370; ¶0032) having a third side (right side of area 370) and a fourth side (left side of area 370) opposite to the third side (right side of area 370), the third diode area (370) located proximate to the second side (right side of area 314) having the fourth side (left side of area 370) facing the second side (right side of area 314); and
a fourth diode area (Fig.3 372; ¶0032) proximate to the third side (right side of area 370), wherein:
each of the first (314) and third (370) diode areas includes (1) a p-type buried region (Fig.3 320; ¶0034 and Fig.3 374; ¶0036) having a second dopant concentration (inherent feature of p-type buried regions 320 and 374, ¶0014) greater than the first dopant concentration (inherent feature of p-type doped layer 306; ¶0012), the p-type buried region (320 and 374) extended from the p-type layer (306) toward the substrate (302) and terminated within the n-type layer (Fig.3 buried regions 320 and 374 terminate within n-type layer 304 laterally), and (2) an n-type region (Fig.3 322; ¶0034 and Fig.3 376; ¶0036) extended from the surface (324) toward the substrate (302) and terminated within the p-type layer (306) above the p-type buried region (320 and 374), and each of the second (316) and fourth diode (372) areas include a p-type region (Fig.3 334; ¶0035 and Fig.3 378; ¶0037) extended from the surface (324) toward the substrate (302) and terminated within the p-type layer (306), wherein the p-type region (378) has a third dopant concentration (inherent feature of p-type doped regions 334 and 378; ¶0021) greater than the first dopant concentration (inherent feature of p-type doped layer 306; ¶0012).
Regarding claim 22, Strachan teaches the semiconductor device of claim 21, further comprising:
an isolation area (footprint of isolation structures 308) laterally surrounding the first, second, third, and fourth diode areas, respectively, wherein the isolation area includes a dielectric isolation structure (308) extended from the surface (324) past an interface (interface between 302 and 304) between the n-type layer (304) and the substrate (302).
Regarding claim 23, Strachan teaches the semiconductor device of claim 22, wherein the dielectric isolation Structure (308) includes:
a first dielectric isolation structure (308) extended between the first (314) and second (316) diode areas;
a second dielectric isolation structure (308) extended between the second (316) and third diode areas (370); and
a third dielectric isolation structure (308) extended between the third (370) and fourth (372) diode areas.
Regarding claim 24, Strachan teaches the semiconductor device of claim 23. Strachan does not teach wherein:
the n-type region of the first diode area extends between the first and second isolation structures; and
the n-type region of the third diode area extends between the second and third isolation structures.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the n-type region (322) of the first diode area (314) and the n-type region (376) of the third diode area (370) to fully extend between the corresponding isolation structures (308).
Shape differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the n-type regions (322 and 376) is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of forming a pn diode between the n-type layers (322 and 376) and the p-type layer (306) (In re Dailey, 149 USPQ 47 (CCPA 1976)). It appears that these changes produce no functional differences and therefore would have been obvious.
Regarding claim 25, Strachan teaches the semiconductor device of claim 23, wherein:
The n-type region (322) of the first diode area (314) is spaced away from the first and second isolation structures (308); and
the n-type region (376) of the third diode area (370) is spaced away from the second and third isolation structures (308).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-6 and 10-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strachan et al. (US 20170200712 A1 – hereinafter Strachan) in view of Mallikarjunaswamy et al. (US 20200135714 A1 – hereinafter Mallik).
Regarding claim 1, Strachan teaches a semiconductor device (Fig.3 300; ¶0032), comprising:
an n-type substrate (Fig.3 302; ¶0033);
an n-type layer (Fig.3 304; ¶0033) on the substrate (302);
a p-type layer (Fig.3 306; ¶0033) over the n-type layer (304), the p-type layer (306) including a surface (Fig.3 324; ¶0034) facing away from the substrate; and
a first bidirectional diode (Fig.3 318; ¶0033) including:
a first diode (Fig.3 314; ¶0034) having (1) a first p-type buried region (Fig.3 320; ¶0034) extended from the p-type layer (306) toward the substrate (302) and terminated within the n-type layer (Fig.3 buried region 320 terminates within n-type layer 304 laterally) to form a pn junction (interface between 320 and 302), the first p-type buried region (320) extended from the p-type layer (306) toward the substrate (302) and (2) a first n-type region (Fig.3 322; ¶0034) extended from the surface (324) toward the substrate (302) and terminated above the first p-type buried region (320).
Strachan does not teach wherein the pn junction is formed across the n-type layer.
Mallik teaches a TVS protection device having a buried layer (Fig.2 106; ¶0032 of Mallik) terminated on an epitaxial layer (Fig.2 104; ¶0032 of Mallik) which is on a substrate (Fig.2 102; ¶0032 of Mallik). The interface between the buried layer (106 of Mallik) and the epitaxial layer (104 of Mallik) forms a pn junction (located at the interface between 106 and 104). The device disclosed in Mallik has a buried layer of a first doping type on an epitaxial layer of a second doping type further on a substrate of the second doping type, wherein the substrate is of a greater doping concentration than the epitaxial layer (Fig.2 of Mallik).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the second pn junction at the interface between 320 and 304 instead of the interface between 320 and 302 so layer 304 can serve as a less doped intermediate between 320 and 302 as taught by Mallik. To make this modification, the first p-type buried layer (320 of Strachan) would have to be vertically terminated within the n-type layer (304 of Strachan). A practitioner of ordinary skill would be motivated to make this modification because doing so would smoothen the transition from one doping type to another doping type for an electric current flowing through the pn junction.
Regarding claim 2, Strachan teaches the semiconductor device of claim 1, wherein the first bidirectional diode (318) further comprises a first isolation structure (Fig.3 308; ¶0032) laterally surrounding the first diode (314), the first isolation structure (308) extended from the surface (324) past an interface (interface between 302 and 304) between the n-type layer (304) and the substrate (302), and
wherein the first n-type region (322) touches the first isolation structure (308).
Regarding claim 3, Strachan teaches the semiconductor device of claim 2, wherein the first bidirectional diode (318) further comprises:
a first bypass diode (Fig.3 316; ¶0032) having a first p-type region (Fig.3 334; ¶0035) extended from the surface (324) toward the substrate (302) and terminated within the p-type layer (306); and
a second isolation structure (308; the reference isolation structures are all labeled 308, however Figure 3 clearly shows a match to part 141 of Fig.1B of application) laterally surrounding the first bypass diode (316), the second isolation structure (308) extended from the surface (324) past the interface (interface between 302 and 304).
Regarding claim 4, Strachan teaches the semiconductor device of claim 3, wherein the first bypass diode (316) lacks the first p-type buried region (320 is not a layer within 316).
Regarding claim 5, Strachan teaches the semiconductor device of claim 3, further comprising a second bidirectional diode (Fig.3 368; ¶0032) including:
a second diode (Fig.3 370; ¶0032) having (1) a second p-type buried region (Fig.3 374; ¶0036) extended from the p-type layer (306) toward the substrate (302) and terminated within the n-type layer (Fig.3 buried region 374 terminates within n-type layer 304 laterally) and (2) a second n-type region (Fig.3 376; ¶0036) extended from the surface (324) toward the substrate (302) and terminated above the second p-type buried region (374);
a third isolation structure (308) laterally surrounding the second diode (370), the third isolation structure (308) extended from the surface (324) past the interface (interface between 302 and 304);
a second bypass diode (Fig.3 372; ¶0032) having a second p-type region (Fig.3 378; ¶0037) extended from the surface (324) toward the substrate (302) and terminated within the p-type layer (306);
and a fourth isolation structure (308) laterally surrounding the second bypass diode (372), the fourth isolation structure (308) extended from the surface (308) past the interface (interface between 302 and 304).
Regarding claim 6, Strachan teaches the semiconductor device of claim 5, wherein the substrate (302) provides a common node (Substrate 302 electrically connects all 4 diodes and is therefore a common node) for the first (314) and second (370) diodes and the first (316) and second (372) bypass diodes.
Regarding claim 10, Strachan teaches the semiconductor device of claim 1, wherein:
the first n-type region (322) includes an inner portion with a first average dopant concentration (Fig.1 128; ¶0014) and an outer portion with a second average dopant concentration (Fig.1 126; ¶0014) less than the first average dopant concentration (¶0014);
the outer portion in contact with the p-type layer (306) forms a first pn junction (Fig.3 located at the interface between 306 and 322) at a first depth (Fig.3 depth not explicitly shown but a feature of first pn junction) from the surface (324); and
the pn junction (interface between 320 and 304) formed across the n-type layer (304) and the first p-type buried region (320) is a second pn junction.
Regarding claim 11, Strachan teaches the semiconductor device of claim 10, wherein:
the first average dopant concentration (Concentration of 128) ranges from 1x1017 cm-3 to 3x1019 cm-3 (¶0014); and
the second average dopant concentration (Concentration of 126) ranges from 1x1016 cm-3 to 1x1017 cm-3 (¶0014).
Regarding claim 12, Strachan teaches the semiconductor device of claim 10, wherein the second pn junction is (Fig.3 located at 320/304 interface) at a second depth (depth not explicitly shown but a feature of second pn junction) from the surface (324) greater than the first depth (320/304 interface is farther from surface 324 than 322/306 interface).
Regarding claim 13, Strachan teaches the semiconductor device of claim 12, wherein a third pn junction (Fig.3 located at 306/304 interface in diode 316) is formed across the p-type layer (306) and the n-type layer (304) at a third depth (depth of 306/304 interface) from the surface (324) greater than the first depth and less than the second depth (Fig.3 depicts the third pn junction depth between the previously cited first and second depths).
Regarding claim 14, Strachan teaches the semiconductor device of claim 1, wherein:
the n-type substrate (302) has an average dopant concentration greater than 1x1018 cm-3 (¶0012);
The n-type layer (304) has an average dopant concentration less than 1x1016 cm-3 (¶0012);
the p-type layer (306) has an average dopant concentration less than 1x1015 cm-3 (¶0012);
the p-type buried region (320) has a dopant concentration of at least 1x1017 cm-3 (¶0014); and
the p-type region (334) has a dopant concentration of at least 1x1017 cm-3 (¶0021).
Regarding claim 15, Strachan teaches a semiconductor device (Fig.3 300; ¶0032), comprising:
an n-type substrate (Fig.3 302; ¶0033);
an n-type layer (Fig.3 304; ¶0033) on the substrate (302);
a p-type layer (Fig.3 306; ¶0033) over the n-type layer (304), the p-type layer (306) including a surface (Fig.3 324; ¶0034) facing away from the substrate (302); and
a first area (Fig.3 314; ¶0034) including a first side (left side of area 314) and a second side (right side of area 314) opposite to the first side (left side of area 314), wherein the first area (314) includes a first diode having a first pn junction (Fig.3 located at the interface between 306 and 322) at a first depth (Fig.3 depth not explicitly shown but a feature of first pn junction) from the surface (324), the first pn junction (located at the interface between 306 and 322) formed across the p-type layer (306) and a first n-type region (322) extended from the surface (324) to the first depth (depth not explicitly shown but a feature of first pn junction) and a second diode having a second pn junction (Fig.3 located at 320/302 interface) at a second depth (Fig.3 depth not explicitly shown but a feature of second pn junction) from the surface (324) greater than the first depth (Fig.3 second junction lower than the first).
Strachan does not teach wherein the second pn junction is formed across the n-type layer and a first p-type buried region extended from the p-type layer toward the substrate. Strachan does teach wherein the second pn junction is formed across the n-type substrate and a first p-type buried region extended from the p-type layer toward the substrate.
Mallik teaches a TVS protection device having a buried layer (Fig.2 106; ¶0032 of Mallik) terminated on an epitaxial layer (Fig.2 104; ¶0032 of Mallik) which is on a substrate (Fig.2 102; ¶0032 of Mallik). The interface between the buried layer (106 of Mallik) and the epitaxial layer (104 of Mallik) forms a pn junction (located at the interface between 106 and 104). The device disclosed in Mallik has a buried layer of a first doping type on an epitaxial layer of a second doping type further on a substrate of the second doping type, wherein the substrate is of a greater doping concentration than the epitaxial layer (Fig.2 of Mallik).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the second pn junction at the interface between 320 and 304 instead of the interface between 320 and 302 so layer 304 can serve as a less doped intermediate between 320 and 302 as taught by Mallik. To make this modification, the first p-type buried layer (320) would have to be vertically terminated within the n-type layer (304). A practitioner of ordinary skill would be motivated to make this modification because doing so would smoothen the transition from one doping type to another doping type for an electric current flowing through the pn junction.
Regarding claim 16, the aforementioned combination of Strachan in view of Mallik from claim 15 teaches the semiconductor device of claim 15, further comprising:
a first isolation structure (308) laterally surrounding the first area (314), the first isolation structure (308) including a first portion (left part of 308 around 322) on a first edge (left edge) of the first n-type region (322) and a second portion (right part of 308 around 322) on a second edge (right edge) of the first n-type region (322), the first n-type region (322) extending from the first portion (left part of 308 around 322) of the first isolation structure (308) to the second portion (right part of 308 around 322) of the first isolation structure (308) and the second edge (right edge) being opposite the first edge (left edge).
Regarding claim 17, the aforementioned combination of Strachan in view of Mallik from claim 16 teaches the semiconductor device of claim 16, further comprising:
a second area (316) located proximate to the first side (left side of area 314) of the first area (314), the second area (316) including a third pn junction (located at 306/304 interface in second area 316) at a third depth (depth of 306/304 interface) from the surface (324) greater than the first depth and less than the second depth (Fig.3 depicts the third pn junction depth between the previously cited first and second depths), wherein the third pn junction (located at 306/304 interface in second area 316) is formed across the p-type layer (306) and the n-type layer (304); and
a second isolation structure (308) laterally surrounding the second area (316), the second isolation structure (308) extended from the surface (324) past the interface (304 and 302 interface).
Regarding claim 18, the aforementioned combination of Strachan in view of Mallik from claim 17 teaches the semiconductor device of claim 17, further comprising:
a third area (370) including a third side (right side of the third area) and a fourth side (left side of the third area) opposite to the third side, the third area (370) located proximate to the first area (314) with the fourth side (left side of the third area) facing the second side (right side of the first area), wherein the third area (370) includes (1) a fourth pn junction (located at the interface between 306 and 376) at the first depth (depth not explicitly shown but a common feature of first and fourth pn junctions), the fourth pn junction (located at the interface between 306 and 376) formed across the p-type layer (306) and a second n-type region (376) extended from the surface (324) to the first depth and (2) a fifth pn junction (located at the interface between 304 and 374) at the second depth (depth not explicitly shown but a feature of second and fifth pn junctions);
a third isolation structure (308) laterally surrounding the third area (370), the third isolation structure (308) extended from the surface (324) past the interface (304 and 302 interface);
a fourth area (372) located proximate to the third side (right side of the third area) of the third area (370), the fourth area (372) including a sixth pn junction (located at 306/304 interface in fourth area 372) at the third depth (depth of 306/304 interface), wherein the sixth pn junction (located at 306/304 interface in fourth area 372) is formed across the p-type layer (306) and the n-type layer (304); and
a fourth isolation structure (308) laterally surrounding the fourth area (372), the second isolation structure (308) extended from the surface (324) past the interface (304 and 302 interface).
The aforementioned combination in view of Mallik does not teach the fifth pn junction formed across the n-type layer and a second p-type buried region extended from the p-type layer toward the substrate.
Mallik teaches a TVS protection device having a buried layer (Fig.2 106; ¶0032 of Mallik) terminated on an epitaxial layer (Fig.2 104; ¶0032 of Mallik) which is on a substrate (Fig.2 102; ¶0032 of Mallik). The interface between the buried layer (106 of Mallik) and the epitaxial layer (104 of Mallik) forms a pn junction (located at the interface between 106 and 104). The device disclosed in Mallik has a buried layer of a first doping type on an epitaxial layer of a second doping type further on a substrate of the second doping type, wherein the substrate is of a greater doping concentration than the epitaxial layer (Fig.2 of Mallik).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the fifth pn junction at the interface between 374 and 304 instead of the interface between 374 and 302 so layer 304 can serve as a less doped intermediate between 374 and 302 as taught by Mallik. To make this modification, the second p-type buried layer (374) would have to be vertically terminated within the n-type layer (304). A practitioner of ordinary skill would be motivated to make this modification because doing so would smoothen the transition from one doping type to another doping type for an electric current flowing through the pn junction.
Allowable Subject Matter
Claims 8, 20 and 27-31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, the most relevant prior art reference US-20170200712-A1 to Strachan et al. teaches most of the limitations of claim 8, but not the limitations of “during a first electrostatic discharge (ESD) event with a first polarity, first current flows between the first bypass diode and the second diode through a first portion of the substrate under the first diode; and
during a second ESD event with a second polarity opposite to the first polarity, second current flows between the second bypass diode and the first diode through a second portion of the substrate under the second diode” as recited. Therefore, claim 8 is deemed patentable over the prior art.
Regarding claim 20, the most relevant prior art reference US-20170200712-A1 to Strachan et al. teaches most of the limitations of claim 20, but not the limitations of “during a first electrostatic discharge (ESD) event with a first polarity, first current flows between the first p-type region and the second n-type region through a first portion of the substrate corresponding to the first area; and
during a second ESD event with a second polarity opposite to the first polarity, second current flows between the second p-type region and the first n-type region through a second portion of the substrate corresponding to the third area.” as recited. Therefore, claim 20 is deemed patentable over the prior art.
Regarding claim 27, the most relevant prior art reference US-20170200712-A1 to Strachan et al. teaches most of the limitations of claim 27, but not the limitations of “during a first electrostatic discharge (ESD) event with a first polarity, first current flows between the p-type region of the second diode area and the n-type region of the third diode area through a first portion of the substrate corresponding to the first diode area; and
during a second ESD event with a second polarity opposite to the first polarity, second current flows between the p-type region of the fourth diode area and the n-type region of the first diode area through a second portion of the substrate corresponding to the third diode area.” as recited. Therefore, claim 27 is deemed patentable over the prior art.
Regarding claim 28, the most relevant prior art reference US-20170200712-A1 to Strachan et al. teaches most of the limitations of claim 28, but not the limitations of “the second diode area is disposed on the first side of the first diode area without any other diode area being disposed between the first side of the first diode area and the second diode area;
the third diode area is disposed on the second side of the first diode area without any other diode area being disposed between the second side of the first diode area and the third diode area; and
the fourth diode area is disposed on the third side of the third diode area without any other diode area being disposed between the third side of the third diode area and the fourth diode area” as recited. Therefore, claim 28 is deemed patentable over the prior art.
Regarding claim 29, the most relevant prior art reference US-20170200712-A1 to Strachan et al. teaches most of the limitations of claim 29, but not the limitations of “during an electrostatic discharge event, current flows between the first bypass diode and the second diode through a portion of the substrate under the first diode” as recited. Therefore, claim 29 is deemed patentable over the prior art.
Claims 30-31 are also deemed patentable for depending from patentable claim 29.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817