DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 07/28/2026 amendments of claims 1, 21 and 25 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 8-15, filed 07/28/2026, with respect to the rejection of claims 1,10 and 12-27 under 35 U.S.C. 103 have been fully considered and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Kaskoun et al, US 20140131549 A1 (Kaskoun) and Su, CN 102736189 A (Su).
New Grounds of Rejection
New grounds of rejection, prior art references Kaskoun et al, US 20140131549 A1 (Kaskoun) and Su, CN 102736189 A (Su) appear below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 recites the limitation " the first electrical conduction posts " (emphasis added) in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation " the first electrical conduction posts " (emphasis added) in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in secondary reference(s).
Claims 1 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189).
Regarding claim 1; Kaskoun teaches a chip package structure comprising:
a substrate (Kaskoun: Annotated Fig (15) shared in this OA: 1520) comprising a first surface (First Surface) and a second surface (Second Surface) being opposite surfaces of the substrate (1520);
a chip set (1502+1503; 1500) disposed in a chip region on the first surface (First Surface) and electrically connected (1424a; 1524b are solder electric connections) to the substrate,
wherein the chip set (1502+1503; 1500) comprises a first chip (1500) and a second chip (1502+1503), and an active surface (1524) of the second chip (1502+1503) faces an active surface (1508) of the first chip (1500),
wherein the first chip (1503) emits radiation (1512) from the active surface (1508), and the second chip (1502+1503) receives radiation (1512) from the active surface (1508);
a housing disposed on the first surface of the substrate and enclosing the chip region, wherein the first chip is on the first surface,
the chip package structure further comprises a plurality of electrical conduction structures (1524a; 1524b), the electrical conduction structures penetrate the housing,
the housing has a height greater than a thickness of the first chip, and the second chip is on the housing and is electrically connected to the substrate through the electrical conduction structures; and
a plurality of conductive connection structures (Conductive Connection Structures) on the second chip (1502+1503), wherein the conductive connection structures (Conductive Connection Structures) are connected to the electrical conduction structures (1524a; 1524b), and the second chip (1502+1503) is electrically connected to the substrate (1520) through the conductive connection structures (Conductive Connection Structures) and the electrical conduction structures (1524a; 1524b), wherein the second chip is disposed over the housing and includes the conductive connection structures (Conductive Connection Structures), and
wherein the housing and the substrate define a space accommodating the first chip, the second chip (1502+1503) covering the space (Space) such that the active surface (1524) of the second chip (1502+1503) faces the active surface (1508) of the first chip (1500) across the space (Space).
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Kaskoun teaches a chip package structure but fails to disclose a housing for the chips. Thus, Kaskoun does not teach the chip package structure further comprising: a housing disposed on the first surface of the substrate and enclosing the chip region, wherein the first chip is on the first surface, the electrical conduction structures penetrate the housing, the housing has a height greater than a thickness of the first chip, and the second chip is on the housing and is electrically connected to the substrate through the electrical conduction structures, wherein the second chip is disposed over the housing.
Su ‘805 teaches further comprising: a housing (Su ‘805: Annotated Fig (11A) shared in this OA: 66+48+202) disposed on the first surface (First Surface) of the substrate (68) and enclosing the chip region (Area inside the dotted square in annotated Fig (11A)), wherein the first chip (58) is on the first surface (First Surface), the chip package structure (82) further comprises a plurality of electrical conduction structures (32+52+84+92), the electrical conduction structures penetrate the housing (66+48+202), the housing has a height (Housing Height) greater than a thickness of the first chip (58), wherein the second chip (234) is disposed over the housing (66+48+202).
Kaskoun and Su ‘805 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun by introducing the chip housing on the substrate as disclosed in Su ‘805 to achieve the predictable result of helping protect the chips in a better manner ensuring the longevity of the device and its resistance to external damaging factors.
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Kaskoun in view of Su ‘805 does not teach the chip package wherein the housing and the substrate define a space accommodating the first chip.
Su ‘189 teaches wherein the housing (Su ‘189: Annotated Fig (1) shared in this OA: 108) and the substrate (102) define a space accommodating the first chip (103).
Kaskoun in view of Su ‘805 and Su ‘189 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 by making the housing and the substrate define a space accommodating the first chip as disclosed in Su ‘189 to improve the protection of the chips leading to a more reliable device.
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Regarding claim 24; Kaskoun in view of Su ‘805 in further view of Su ‘189 teaches all the limitations of the chip package structure according to claim 1.
Kaskoun does not teach explicitly in what relates to first embodiment disclosed in Fig (15) wherein the second chip receives the radiation from the active surface to convert the radiation into electrical power output.
Kaskoun teaches explicitly in the second emobodiment disclosed in Fig (2) wherein the second chip (Kaskoun: Fig (2): 202) receives the radiation (220) from the active surface to convert the radiation (220) into electrical power output ([0091]: “…The optical signal is then transmitted to the second die 202, where the optical signal is converted back to an electrical signal.”).
The two embodiments of Kaskoun are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment of Kaskoun by constructing the receiver such that the second chip would produce an electric power output as disclosed in the second embodiment of Kaskoun achieve the predictable result of controlling the circuitry of the device efficiently.
Claims 10 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Pendse, US 20210013099 A1 (Pendse).
Regarding claim 10; Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse teach all the limitations of claim 22.
Kaskoun in view of Su ‘805 in further view of Su ‘189 does not teach wherein no electricity conduction is formed between the first aligning connection structures and the second aligning connection structures.
Pendse teaches wherein no electricity conduction is formed between the first aligning connection structures (Pendse: Fig (7D): 742) and the second aligning connection structures (422).
Kaskoun in view of Su ‘805 in further view of Su ‘189 and Pendse are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 by electrically isolating the first aligning connection structures and the second aligning connection structures from each other as disclosed in pendse to eliminate the possibility of electrical shorts between the different connections ensuring a more reliable operation of the device.
Regarding claim 22; Kaskoun in view of Su ‘805 in further view of Su ‘189 teaches all the limitations of claim 1.
Kaskoun teaches a plurality of conductive connection structures (Kaskoun: Annotated Fig (15) shared in this OA: Conductive Connection Structures); and a plurality of first aligning connection structures and a plurality of second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures, the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and a number of the first aligning connection structures is different from a number of the second aligning connection structures.
And while Kaskoun in view of Su ‘805 in further view of Su ‘189 teaches a plurality of conductive connection structures; it fails to teach a plurality of first aligning connection structures and a plurality of second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures, the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and a number of the first aligning connection structures is different from a number of the second aligning connection structures.
Pendse teaches a plurality of conductive connection structures (Pendse: Fig (7D): 624); and a plurality of first aligning connection structures (742) and a plurality of second aligning connection structures (422), wherein the first aligning connection structures (742) and the second aligning connection structures (422) are on the chip (414) and aligned with the conductive connection structures (624), the first aligning connection structures (742) and the second aligning connection structures (422) are adapted for alignment of the chip (414) in the chip package structure, and a number of the first aligning connection structures (742) is different from a number of the second aligning connection structures (422).
Kaskoun in view of Su ‘805 in further view of Su ‘189 and Pendse are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 by using the first and second aligning connections structures as disclosed in Pendse to achieve the predictable outcome of improving the accuracy of aligning the second chip in the package to make the device more reliable and the production process of the device more efficient.
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Claims 12-13, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Pendse, US 20210013099 A1 (Pendse) in further view of Huang et al, CN 112466868 A (Huang).
Regarding claim 12; Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse teaches all the limitations of claim 22.
Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse does not teach wherein the first chip comprises a plurality of blocks which are arranged orderly, at least two of the blocks comprise a plurality of columnar structures, and a number of the columnar structures in one of the at least two blocks is identical to a number of the columnar structures in any other one of the at least two blocks.
Huang teaches wherein the first chip comprises a plurality of blocks (Huang: Fig (1): 011; 012) which are arranged orderly (see Fig (1)), at least two of the blocks (011; 012) comprise a plurality of columnar structures (011; 012), and a number of the columnar structures in one of the at least two blocks is identical to a number of the columnar structures in any other one of the at least two blocks (011 and 012 contain the same number of columnar structures).
Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse by using the columnar structure of the chips as disclosed in Huang to save space in the chip package and to simplify the electrical connections between different block components of the chips making the device production more efficient.
Regarding claim 13; Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang teach all the limitations of claim 12.
Further, Kaskoun teaches wherein the second chip comprises a plurality of mesa structures which are arranged orderly, a groove separates any two neighboring ones of the mesa structures, and each of the mesa structures of the second chip (Kaskoun: Annotated Fig (15) shared in this OA: 1502+1503) is aligned with a corresponding one of the blocks of the first chip (1500)
Kaskoun in view of Su ‘805 in further view of Su ‘189 teaches the alignment of the mesa structures of the second chips with blocks of the first chip but fails to disclose the geometric structure and layout of the second chip. Thus, Kaskoun in view of Su ‘805 in further view of Su ‘189 does not teach wherein the second chip comprises a plurality of mesa structures which are arranged orderly, a groove separates any two neighboring ones of the mesa structures, and each of the mesa structures of the second chip is aligned with a corresponding one of the blocks of the first chip.
Pendse teaches wherein the second chip comprises a plurality of mesa structures (Pendse: Fig (2B): 106) which are arranged orderly (see Fig (2A) of Pendse), a groove (see the region between structures 202a and 202b in Fig (2A)) separates any two neighboring ones of the mesa structures (Fig (2B): 106).
Kaskoun in view of Su ‘805 in further view of Su ‘189 and Pendse are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 by introducing the block structure of the second chip as disclosed in Pendse to achieve the predictable outcome of improving the density of chips in the device thus leading to a better performing device.
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Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Pendse, US 20210013099 A1 (Pendse) in further view of Huang et al, CN 112466868 A (Huang) in further view of Miyaji et al, JP 2016100252 A (Miyaji).
Regarding claim 18; Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang teaches all the limitations of claim 12
However, Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang does not teach wherein control of the columnar structures in one of the blocks is independent of control of the columnar structures in another one of the blocks.
Miyaji teaches wherein control of the columnar structures (Miyaji: Fig (2): A-H) in one of the blocks is independent of control (Claims section: Claim 1; “The plurality of light emitting diodes are divided into a plurality of control units that can be controlled to turn on / off independently”) of the columnar structures (A-H) in another one of the blocks.
Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang and Miyaji are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang by introducing the independent control mechanism of the columnar structures of the chips disclosed in Miyaji to improve the ability to control the various parts of the device.
Claims 14, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Pendse, US 20210013099 A1 (Pendse) in further view of Huang et al, CN 112466868 A (Huang) in further view of Chen et al, US 20200020739 A1 (Chen).
Regarding claim 14; Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang teaches all the limitations of claim 13.
However, Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang does not teach wherein a first distance is a shortest distance between the columnar structures of two neighboring ones of the blocks of the first chip, the groove of the second chip has a first width, and the first distance is greater than the first width.
Chen teaches wherein a first distance (Chen: Annotated Fig (13) shared in this OA: First Distance) is a shortest distance between columnar structures (901) of two neighboring ones of the blocks of the first chip (20a), the groove (Groove) of the second chip (20b) has a first width, and the first distance (First Distance) is greater than the first width (First Width).
Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang and Chen are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang by introducing the distance between the blocks in the block structure of the chip as disclosed in Chen to achieve the predictable result of increasing the density of the devices on the chip thus leading to a better performing device.
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Regarding claim 17; Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang teaches all the limitations of claim 12.
However, Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse does not teach wherein in the at least two blocks, a distance between any two neighboring ones of the columnar structures is identical to a distance between any other two neighboring ones of the columnar structures.
Huang teaches wherein in the at least two blocks (Huang: Fig (1): 011; 012), a distance between any two neighboring ones of the columnar structures (011; 012) is identical to a distance between any other two neighboring ones of the columnar structures (011; 012).
Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse by making the distances between the chip blocks identical as disclosed in Huang to make the design of the layout of the device simpler and the production process more efficient.
Regarding claim 19; Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Pendse in further view of Huang teaches all the limitations of claim 12.
Further, Lim teaches wherein the first chip (Kaskoun: Annotated Fig (15) shared in this OA: 1500) has a first geometric center, the second chip (1502+1503) has a second geometric center, and the first geometric center and the second geometric center are substantially aligned with each other (see Fig (15) of Kaskoun).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in view of Su, CN 102736189 A (Su ‘189) in further view of Pendse, US 20210013099 A1 (Pendse)
Regarding claim 21; Kaskoun teaches a chip package structure comprising:
a substrate (Kaskoun: Annotated Fig (15) shared in this OA: 1520) comprising a first surface (First Surface) and a second surface (Second Surface) opposite the first surface (First Surface);
a chip set (1502+1503; 1500) disposed in a chip region on the first surface (First Surface) and electrically connected (1424a; 1524b are solder electric connections) to the substrate (1520),
wherein the chip set (1502+1503; 1500) comprises a first chip (1500) and a second chip (1502+1503), and an active surface (1524) of the second chip (1502+1503) faces an active surface (1508) of the first chip (1500),
wherein the first chip (1500) emits radiation (1512) from the active surface (1508), and the second chip (1502+1503) receives radiation (1512) from the active surface (1524);
a plurality of conductive connection structures (Conductive Connection Structures), wherein the second chip (1502+1503) is disposed over a housing and includes the conductive connection structures (Conductive Connection Structures), and
the housing has a height greater than a thickness of the first chip, and
the second chip is on the housing, wherein the housing and the substrate define a space accommodating the first chip,
the second chip (1502+1503) covering the space (Space) such that the active surface (1524) of the second chip (1502+1503) faces the active surface (1508) of the first chip (1500) across the space (Space); and
a plurality of first aligning connection structures and a plurality of second aligning connection structures,
wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures,
the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and
a number of the first aligning connection structures is different from a number of the second aligning connection structures,
wherein the first aligning connection structures and the second aligning connection structures are disposed on two opposite sides of the second chip.
While Kaskoun teaches a second chip (1502+1503), it fails to disclose wherein the second chip is disposed over a housing; the housing has a height greater than a thickness of the first chip, and the second chip is on the housing, wherein the housing and the substrate define a space accommodating the first chip.
Su ‘189 teaches wherein the second chip (Su ‘189: Annotated Fig (1) shared in this OA: 104) is disposed over a housing (108); the housing (108) has a height greater than a thickness of the first chip (103), and the second chip (104) is on the housing (108), wherein the housing (108) and the substrate (102) define a space accommodating the first chip (103).
Kaskoun and Su ‘189 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun by constructing the housing to have a height greater than the thickness of the first chip and to have a space that accommodates the first chip to protect the first chip from external environmental factors and thus leading to a more reliable device.
Kaskoun in further view of Su ‘189 does not teach a plurality of first aligning connection structures and a plurality of second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures, the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and a number of the first aligning connection structures is different from a number of the second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are disposed on two opposite sides of the second chip.
Pendse teaches a plurality of first aligning connection structures (Pendse: Fig (7D): 742) and a plurality of second aligning connection structures (422), wherein the first aligning connection structures (742) and the second aligning connection structures (422) are on the chip (414) and aligned with the conductive connection structures (624), the first aligning connection structures (742) and the second aligning connection structures (422) are adapted for alignment of the chip (414) in the chip package structure, and a number of the first aligning connection structures (742) is different from a number of the second aligning connection structures (422), wherein the first aligning connection structures (742) and the second aligning connection structures (422) are disposed on two opposite sides of the second chip (414).
Kaskoun in view of Su ‘805 in further view of Su ‘189 and Pendse are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 by using the first and second aligning connections structures as disclosed in Pendse to achieve the predictable outcome of improving the accuracy of aligning the second chip in the package to make the device more reliable and the production process of the device more efficient.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Chiba et al, WO 2021079862 A1 (Chiba) in further view of Beyer et al, US 20190044362 A1 (Beyer).
Regarding claim 20; Kaskoun in view of Su ‘805 in further view of Su ‘189 teaches all the limitations of claim 1.
However, Kaskoun in view of Su ‘805 in further view of Su ‘189 does not teach an automated external defibrillator comprising: a power module adapted to provide a constant-voltage input current; a high-voltage power module comprising the chip package structure according to claim 1 and adapted to receive the constant-voltage input current and output a high-voltage current; and an electrode pad module coupled to the high-voltage power module and adapted to output a high voltage so as to deliver a defibrillation shock.
Chiba teaches an automated external defibrillator comprising: a power module (Chiba: Fig (2): 19) adapted to provide a constant-voltage input current; a high-voltage power module (16) comprising the chip package structure according to claim 1 and adapted to receive the constant-voltage input current and output a high-voltage current; and an electrode pad module (Fig (3): 3A; 3B) coupled to the high-voltage power module (19) and adapted to output a high voltage so as to deliver a defibrillation shock (Abstract).
Kaskoun in view of Su ‘805 in further view of Su ‘189 and Chiba are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 to utilize the power module and electrode pad module in combination with the chip package as disclosed in Chiba to construct an efficient and reliable defibrillator.
Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Chiba teaches the details of the components of the defibrillator system however, it fails to disclose the characteristics of the input voltage and output currents of the device. Thus, Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Chiba fails to disclose adapted to receive constant-voltage input current and output a high-voltage current.
Beyer teaches to receive constant-voltage current and output a high-voltage current (Bayer: [0141]).
Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Chiba and Beyer are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 in further view of Chiba by introducing the high-voltage current converter disclosed in Beyer to improve the performance of the device.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Ostrowski, US 20080076993 A1 (Ostrowski).
Regarding claim 23; Kaskoun in view of Su ‘805 in further view of Su ‘189 teaches all the limitations of the chip package structure according to claim 1.
However, Kaskoun in view of Su ‘805 in further view of Su ‘189 does not teach wherein a distance between the active surface of the first chip and the active surface of the second chip is in a range from 1 μm to 30 μm.
Ostrowski teaches wherein a distance between the active surface of the first chip (Ostrowski: Fig (5): 12) and the active surface of the second chip (14) is in a range from 1 μm to 30 μm ([0012]).
Kaskoun in view of Su ‘805 in further view of Su ‘189 and Ostrowski are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Su ‘805 in further view of Su ‘189 by making the distance between the transmitter and the receiver in the range disclosed in Ostrowski to lower the losses of the signal during detection and thus improve the efficiency of the device.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in view of Huang et al, CN 112466868 A (Huang) in further view of Pendse, US 20210013099 A1 (Pendse).
Regarding claim 25; Kaskoun teaches a chip package structure comprising:
a substrate (Kaskoun: Annotated Fig (15) shared in this OA: 1520) comprising a first surface (First Surface) and a second surface (Second Surface) being opposite surfaces of the substrate (1520); and
a chip set (1502+1503; 1500) disposed in a chip region on the first surface (First Surface) and electrically connected to the substrate (1520),
wherein the chip set (1502+1503; 1500) comprises a first chip (1500) and a second chip (1502+1503), and
an active surface (1524) of the second chip (1502+1503) faces an active surface (1508) of the first chip (1500),
wherein the first chip comprises a plurality of blocks which are arranged orderly,
the second chip comprises a plurality of mesa structures which are arranged orderly, and
each of the mesa structures of the second chip (1502+1503) is aligned with a corresponding one of the blocks of the first chip (1500),
wherein each of the blocks of the first chip (1500) is a light-emitting region and each of the mesa structures of the second chip (1502+1503) is a light-receiving region, and each of the mesa structures receives radiation (1512) emitted by the corresponding aligned one of the blocks.
Kaskoun does not teach wherein the first chip comprises a plurality of blocks which are arranged orderly.
Huang teaches wherein the first chip comprises a plurality of blocks (Huang: Fig (1): 011; 012) which are arranged orderly (see Fig (1)).
Kaskoun and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun by using the first chip comprised of a plurality of blocks arranged orderly as disclosed in Huang to save space in the chip package and to simplify the electrical connections between different block components of the chips making the device production more efficient.
Kaskoun in view of Huang discloses the structure of the first chip but fails to disclose the structure of the second chip. Thus, Kaskoun in view of Huang fails to disclose the second chip comprises a plurality of mesa structures which are arranged orderly.
Pendse teaches the second chip (Pendse: Fig (2B): 202a; 202b; 202c) comprises a plurality of mesa structures (106) which are arranged orderly (see Fig (2B)).
Kaskoun in view of Huang and Pendse are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Huang by constructing the second chip in the manner disclosed in Pendse with a plurality of mesa structures arranged orderly to improve the organization of the different components on the chip and thus increase the number of components that can be placed on the chip leading to a higher performing device.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in view of Huang et al, CN 112466868 A (Huang) in further view of Pendse, US 20210013099 A1 (Pendse) in further view of Jacobs, US 20170224585 A1 (Jacobs).
Regarding claim 26; Kaskoun in view of Huang in further view of Pendse teaches all the limitations of the chip package structure according to claim 25
Kaskoun in view of Huang in further view of Pendse does not teach wherein the mesa structures of the second chip are connected in series.
Jacobs teaches wherein the mesa structures (Jacobs: Fig (3A): 305) of the second chip (Fig (5A): 505) are connected in series ([0035]).
Kaskoun in view of Huang in further view of Pendse and Jacobs are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Huang in further view of Pendse by connecting the mesa structures of the second chip in series as disclosed in Jacobs to limit the possible current surges in the device and thus improve the longevity and durability of the device.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Kaskoun et al, US 20140131549 A1 (Kaskoun) in view of Huang et al, CN 112466868 A (Huang) in further view of Pendse, US 20210013099 A1 (Pendse) in further view of Hollman et al, US 20190361098 A1 (Hollmann).
Regarding claim 27; Kaskoun in view of Huang in further view of Pendse teaches all the limitations of the chip package structure according to claim 25
Kaskoun in view of Huang in further view of Pendse does not teach wherein the mesa structures of the second chip are connected in parallel.
Hollmann teaches wherein the mesa structures (Hollmann: Fig (2B): 205) of the second chip (204) are connected in parallel ([0017]).
Kaskoun in view of Huang in further view of Pendse and Hollmann are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kaskoun in view of Huang in further view of Pendse by connecting the mesa structures of the second chip in parallel as disclosed in Hollmann to increase the detection ability of the device and thus improve the sensitivity of the device.
Allowable Subject Matter
Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15; Kaskoun alone or in combination with other available art does not teach the first chip comprises a third surface and a fourth surface, the third surface faces the first surface, the fourth surface faces away the first surface, and the third surface and the fourth surface are opposite surfaces of the first chip; the second chip comprises a fifth surface and a sixth surface, the fifth surface faces the fourth surface, the sixth surface faces away the fourth surface, and the fifth surface and the sixth surface are opposite surfaces of the second chip; the fourth surface is the active surface of the first chip, and the fifth surface is the active surface of the second chip; wherein the chip package structure further comprises: a first conduction structure and a second conduction structure, wherein the first conduction structure is on the third surface of the first chip and connected to one of the first electrical conduction posts, and the second conduction structure is on the third surface of the first chip and connected to another one of the first electrical conduction posts, so that the first chip is electrically connected to the first electrical conduction posts; and a first conductive connection structure and a second conductive connection structure, wherein the first conductive connection structure is on the sixth surface and connected to one of the second electrical conduction posts through a wire, and the second conductive connection structure is on the sixth surface and connected to another one of the second electrical conduction posts through another wire, so that the second chip is electrically connected to the second electrical conduction posts in a manner that can be reasonably combined with the rest of the limitations inherited by the claim from its base claim.
Regarding claim 16; Kaskoun alone or in combination with any other available art does not teach wherein the first chip comprises a third surface and a fourth surface, the third surface faces the first surface, the fourth surface faces away the first surface, and the third surface and the fourth surface are opposite surfaces of the first chip; the second chip comprises a fifth surface and a sixth surface, the fifth surface faces the fourth surface, the sixth surface faces away the fourth surface, and the fifth surface and the sixth surface are opposite surfaces of the second chip; the fourth surface is the active surface of the first chip, and the fifth surface is the active surface of the second chip; wherein the chip package structure further comprises: a first conduction structure and a second conduction structure, wherein the first conduction structure is on the third surface of the first chip and the second conduction structure is on the fourth surface of the first chip, the first conduction structure is connected to at least one of the first electrical conduction posts, and the second conduction structure is connected to at least another one of the first electrical conduction posts through a first wire, so that the first chip is electrically connected to the substrate; and a first conductive connection structure and a second conductive connection structure, wherein the first conductive connection structure is on the sixth surface and connected to one of the second electrical conduction posts through a second wire, and the second conductive connection structure is on the sixth surface and connected to another one of the second electrical conduction posts through another second wire, so that the second chip is electrically connected to the substrate in a manner that can be reasonably combined with the rest of the limitations inherited by the claim from its base claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
