DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/25/2026 has been entered.
Remarks
The 02/25/2026 amendments of claims 1 and 21 have been noted and entered.
The 02/25/2026 addition of new claims 23-27 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 9-18, filed 02/25/2026, with respect to the rejection(s) of claim(s) 1, 10 and 12-22 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Su et al, DE 102016015805 B3 (Su ‘805), Su, CN 102736189 A (Su ‘189), Ostrowski, US 20080076993 A1 (Ostrowski), Pendse, US 20210013099 A1 (Pendse), Jacobs, US 20170224585 A1 (Jacobs), Hollmann et al, US 20190361098 A1 (Hollmann) and Miyaji et al, (Miyaji).
Additionally, in response to the argument presented by the Applicant reciting “This disclosure indicates that after CMP planarization, the encapsulating material 48 is coplanar with the dies 34 – not higher than the dies. Therefore, Su ‘805 cannot teach the limitation “the housing has a height greater than a thickness of the first chip”” (emphasis added) (see Remarks pages 12 and 13 filed 02/25/2026). The examiner would like to attract the applicant’s attention to the fact that the examiner considers the housing components to be the elements (66+48+202) of Su ‘805 not just element (48) (see Fig(11A) of Su ‘805). Thus, the combined height of these components is greater than the thickness of the first chip (58). Also, the examiner considers the second chip to be (234) not (34) and consequently it can be concluded that the second chip (234) is on the “housing” which includes the element (202). Annotated Fig (11A) of Su ‘805 is included in this OA with clarifying markings to explain the examiner’s position.
New Grounds of Rejection
New grounds of rejection, prior art references Su et al, DE 102016015805 B3 (Su ‘805), Su, CN 102736189 A (Su ‘189), Ostrowski, US 20080076993 A1 (Ostrowski), Pendse, US 20210013099 A1 (Pendse) Jacobs, US 20170224585 A1 (Jacobs), Hollman et al, US 20190361098 A1 (Hollman) and Miyaji et al, (Miyaji), appear below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in secondary reference(s).
Claims 1 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189).
Regarding claim 1; Lim teaches a chip package structure (Lim: Annotated Fig (5) shared in this OA: 300) comprising:
a substrate (110) comprising a first surface (First Surface) and a second surface (Second Surface) being opposite surfaces of the substrate (110);
a chip set (120; 220) disposed in a chip region on the first surface (First Surface) and electrically connected to the substrate(110), wherein the chip set (120; 220) comprises a first chip (120) and a second chip (220), and an active surface of the second chip faces an active surface of the first chip, wherein the first chip emits radiation from the active surface, and the second chip receives radiation from the active surface;
a housing disposed on the first surface of the substrate and enclosing the chip region, wherein the first chip is on the first surface, the chip package structure further comprises a plurality of electrical conduction structures, the electrical conduction structures penetrate the housing, the housing has a height greater than a thickness of the first chip, and the second chip is on the housing and is electrically connected to the substrate through the electrical conduction structures; and
a plurality of conductive connection structures on the second chip, wherein the conductive connection structures are connected to the electrical conduction structures, and the second chip is electrically connected to the substrate through the conductive connection structures and the electrical conduction structures, wherein the second chip is disposed over the housing and includes the conductive connection structures.
PNG
media_image1.png
922
1220
media_image1.png
Greyscale
Lim does not teach an active surface of the second chip faces an active surface of the first chip.
Lee teaches an active surface of the second chip (Lee: Annotated Fig (4) shared in this OA:14) faces an active surface of the first chip (12; [0048]-[0049])
Lim and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim by introducing the active areas of the devices facing each other as disclosed in Lee to achieve the predictable result of improving the accuracy of the detection of the optical signal.
PNG
media_image2.png
731
762
media_image2.png
Greyscale
Lim in view of Lee teaches a chip package structure but fails to disclose a housing for the chips. Thus, Lim in view of Lee does not teach the chip package structure further comprising: a housing disposed on the first surface of the substrate and enclosing the chip region, wherein the first chip is on the first surface, the chip package structure further comprises a plurality of electrical conduction structures, the electrical conduction structures penetrate the housing, the housing has a height greater than a thickness of the first chip, and the second chip is on the housing and is electrically connected to the substrate through the electrical conduction structures, wherein the second chip is disposed over the housing and includes the conductive connection structures.
Su ‘805 teaches further comprising: a housing (SU ‘805: Annotated Fig (11A) shared in this OA: 66+48+202) disposed on the first surface (First Surface) of the substrate (68) and enclosing the chip region (Area inside the dotted square in annotated Fig (11A)), wherein the first chip (58) is on the first surface (First Surface), the chip package structure (82) further comprises a plurality of electrical conduction structures (32+52+84+92), the electrical conduction structures penetrate the housing (66+48+202), the housing has a height (Housing Height) greater than a thickness of the first chip (58), and the second chip (234) is on the housing and is electrically connected to the substrate (68) through the electrical conduction structures (32+52+84+92), wherein the second chip (234) is disposed over the housing (66+48+202) and includes the conductive connection structures (32+52+84+92).
Lim in view of Lee and Su ‘805 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee by introducing the chip housing on the substrate as disclosed in Su ‘805 to achieve the predictable result of helping protect the chips in a better manner ensuring the longevity of the device and its resistance to external damaging factors.
PNG
media_image3.png
840
1147
media_image3.png
Greyscale
Lim in view of Lee in further view of Su ‘805 does not teach the chip package wherein the first chip emits radiation from the active surface, and the second chip receives radiation from the active surface.
Su ‘189 teaches wherein the first chip (Su ‘189: Fig (1): 103) emits radiation (109) from the active surface, and the second chip (104) receives radiation (109) from the active surface.
Lim in view of Lee in further view of Su ‘805 and Su ‘189 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 by making the first chip emit radiation from the active surface and the second chip receives radiation from the active surface as disclosed in Su ‘189 to improve the communication efficiency between the chips leading to a more reliable device.
Regarding claim 24; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 teaches all the limitations of the chip package structure according to claim 1.
However, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 does not teach wherein the second chip receives the radiation from the active surface to convert the radiation into electrical power output.
Su ‘189 teaches the second chip (Su ‘189: Fig (1): 104) receives the radiation from the active surface to convert the radiation into electrical power output ([0022]-[0023]).
Lim in view of Lee in further view of Su ‘805 and Su ‘189 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 by constructing the receiver such that the second chip would produce an electric power output as disclosed in Su ‘189 to achieve the predictable result of controlling the circuitry of the device efficiently.
Claims 10 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Liao et al, US 20220308284 A1 (Liao).
Regarding claim 22; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 teaches all the limitations of claim 1.
Lim in view of Lee in further view of Su ‘805 teaches a plurality of conductive connection structures (32+52+84+92); and a plurality of first aligning connection structures and a plurality of second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures, the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and a number of the first aligning connection structures is different from a number of the second aligning connection structures.
And while Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 teaches a plurality of conductive connection structures; it fails to teach a plurality of first aligning connection structures and a plurality of second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures, the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and a number of the first aligning connection structures is different from a number of the second aligning connection structures.
Liao teaches a plurality of conductive connection structures (Liao: Annotated Fig (2I) shared in this OA: Conductive connection structures); and a plurality of first aligning connection structures (First aligning connection structures) and a plurality of second aligning connection structures (Second aligning connection structures), wherein the first aligning connection structures (First aligning connection structures) and the second aligning connection structures (Second aligning connection structures) are on the chip (192) and aligned with the conductive connection structures (Conductive connection structures), the first aligning connection structures (First aligning connection structures) and the second aligning connection structures (Second aligning connection structures) are adapted for alignment of the chip (192) in the chip package structure, and a number of the first aligning connection structures ((First aligning connection structures) is different from a number of the second aligning connection structures (Second aligning connection structures).
Lim in view Lee in further view of Su ‘805 in further view of Su ‘189 and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 by using the first and second aligning connections structures as disclosed in Liao to achieve the predictable outcome of improving the accuracy of aligning the second chip in the package to make the device more reliable and the production process of the device more efficient.
PNG
media_image4.png
589
820
media_image4.png
Greyscale
Regarding claim 10; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao teach all the limitations of claim 22.
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 does not teach wherein no electricity conduction is formed between the first aligning connection structures and the second aligning connection structures.
Liao teaches wherein no electricity conduction is formed between the first aligning connection structures (Liao: Annotated Fig (2I) shared in this OA: First aligning connection structures) and the second aligning connection structures (First aligning connection structures).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 by electrically isolating the first aligning connection structures and the second aligning connection structures from each other as disclosed in Liao to eliminate the possibility of electrical shorts between the different connections ensuring a more reliable operation of the device.
Regarding claim 21; Lim teaches a chip package structure (Lim: Annotated Fig (5) shared in this OA: 300) comprising:
a substrate (101) comprising a first surface (First Surface) and a second surface (Second Surface) opposite the first surface (First Surface);
a chip set (120;220) disposed in a chip region on the first surface (First Surface) and electrically connected to the substrate (110), wherein the chip set (120; 220) comprises a first chip (120) and a second chip (220), and an active surface of the second chip faces an active surface of the first chip, wherein the first chip emits radiation from the active surface, and the second chip receives radiation from the active surface;
a plurality of conductive connection structures (240; 112a),
wherein the second chip is disposed over a housing and includes the conductive connection structures, and the housing has a height greater than a thickness of the first chip, and the second chip is on the housing;
and a plurality of first aligning connection structures and a plurality of second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures, the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and a number of the first aligning connection structures is different from a number of the second aligning connection structures.
Lim does not teach an active surface of the second chip faces an active surface of the first chip.
Lee teaches an active surface of the second chip (Lee: Annotated Fig (4) shared in this OA:14) faces an active surface of the first chip (12; [0048]-[0049])
Lim and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim by introducing the active areas of the devices facing each other as disclosed in Lee to achieve the predictable result of improving the accuracy of the detection of the optical signal.
Lim in view of Lee teach a chip package with the geometric structure of the chip layout in the package but fails to disclose a housing. Thus, Lim in view of Lee fails to disclose wherein the second chip is disposed over a housing and includes the conductive connection structures, and the housing has a height greater than a thickness of the first chip, and the second chip is on the housing.
Su ‘805 teaches the second chip (Su ‘805: Annotated Fig (11A) shared in this OA: 234) is disposed over a housing (66+48+202) and includes the conductive connection structures (32+52+84+92), and the housing (66+48+202) has a height (Housing Height) greater than a thickness of the first chip (58), and the second chip (234) is on the housing (66+48+202).
Lim in view of Lee and Su ‘805 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee by introducing the chip housing on the substrate disclosed in Su ‘805 to achieve the predictable result of helping protect the chips in a better manner ensuring the longevity of the device and its resistance to external damaging factors.
Lim in view of Lee in further view of Su ‘805 discloses a chip package with chips of active surfaces but fails to explicitly disclose what each of the active surfaces do. Thus, Lim in view of Lee in further view of Su ‘805 fails to disclose the chip package wherein the first chip emits radiation from the active surface, and the second chip receives radiation from the active surface.
Su ‘189 teaches wherein the first chip (Su ‘189: Fig (1): 103) emits radiation (109) from the active surface, and the second chip (104) receives radiation (109) from the active surface.
Lim in view of Lee in further view of Su ‘805 and Su ‘189 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 by making the first chip emit radiation from the active surface and the second chip receives radiation from the active surface as disclosed in Su ‘189 to improve the communication efficiency between the ships leading to a more reliable device.
And while Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 teaches a plurality of conductive connection structures; it fails to teach a plurality of first aligning connection structures and a plurality of second aligning connection structures, wherein the first aligning connection structures and the second aligning connection structures are on the chip and aligned with the conductive connection structures, the first aligning connection structures and the second aligning connection structures are adapted for alignment of the chip in the chip package structure, and a number of the first aligning connection structures is different from a number of the second aligning connection structures.
Liao teaches a plurality of conductive connection structures (Liao: Annotated Fig (2I) shared in this OA: Conductive connection structures); and a plurality of first aligning connection structures (First aligning connection structures) and a plurality of second aligning connection structures (Second aligning connection structures), wherein the first aligning connection structures (First aligning connection structures) and the second aligning connection structures (Second aligning connection structures) are on the chip (192) and aligned with the conductive connection structures (Conductive connection structures), the first aligning connection structures (First aligning connection structures) and the second aligning connection structures (Second aligning connection structures) are adapted for alignment of the chip (192) in the chip package structure, and a number of the first aligning connection structures ((First aligning connection structures) is different from a number of the second aligning connection structures (Second aligning connection structures).
Lim in view Lee in further view of Su ‘805 in further view of Su ‘189 and Liao are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 by using the first and second aligning connections structures as disclosed in Liao to achieve the predictable outcome of improving the accuracy of aligning the second chip in the package to make the device more reliable and the production process of the device more efficient.
Claims 12, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Liao et al, US 20220308284 A1 (Liao) in further view of Huang et al, CN 112466868 A (Huang).
Regarding claim 12; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao teach all the limitations of claim 22.
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao does not teach wherein the first chip comprises a plurality of blocks which are arranged orderly, at least two of the blocks comprise a plurality of columnar structures, and a number of the columnar structures in one of the at least two blocks is identical to a number of the columnar structures in any other one of the at least two blocks.
Huang teaches wherein the first chip comprises a plurality of blocks (Huang: Fig (1): 011; 012) which are arranged orderly (see Fig (1)), at least two of the blocks (011; 012) comprise a plurality of columnar structures (011; 012), and a number of the columnar structures in one of the at least two blocks is identical to a number of the columnar structures in any other one of the at least two blocks (011 and 012 contain the same number of columnar structures).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao by using the columnar structure of the chips as disclosed in Huang to save space in the chip package and to simplify the electrical connections between different block components of the chips making the device production more efficient.
Regarding claim 17; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang teaches all the limitations of claim 12.
However, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao does not teach wherein in the at least two blocks, a distance between any two neighboring ones of the columnar structures is identical to a distance between any other two neighboring ones of the columnar structures.
Huang teaches wherein in the at least two blocks (Huang: Fig (1): 011; 012), a distance between any two neighboring ones of the columnar structures (011; 012) is identical to a distance between any other two neighboring ones of the columnar structures (011; 012).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao by making the distances between the chip blocks identical as disclosed in Huang to make the design of the layout of the device simpler and the production process more efficient.
Regarding claim 19; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang teaches all the limitations of claim 12.
Further, Lim teaches wherein the first chip (Lim: Fig (5): 120) has a first geometric center, the second chip (220) has a second geometric center, and the first geometric center and the second geometric center are substantially aligned with each other (see Fig (5) of Lim).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Liao et al, US 20220308284 A1 (Liao) in further view of Huang et al, CN 112466868 A (Huang) in further view of Pendse, US 20210013099 A1 (Pendse).
Regarding claim 13; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang teach all the limitations of claim 12.
Further, Lim teaches wherein the second chip comprises a plurality of mesa structures which are arranged orderly, a groove separates any two neighboring ones of the mesa structures, and each of the mesa structures of the second chip (Lim: Annotated Fig (5) shared in this OA: 220) is aligned with a corresponding one of the blocks of the first chip (120)
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang teaches the alignment of the mesa structures of the second chips with blocks of the first chip but fails to disclose the geometric structure and layout of the second chips. Thus, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang does not teach wherein the second chip comprises a plurality of mesa structures which are arranged orderly, a groove separates any two neighboring ones of the mesa structures, and each of the mesa structures of the second chip is aligned with a corresponding one of the blocks of the first chip.
Pendse teaches wherein the second chip comprises a plurality of mesa structures (Pendse: Fig (2B): 106) which are arranged orderly (see Fig (2B) of Pendse), a groove (see the region between structures 202a and 202b in Fig (2B)) separates any two neighboring ones of the mesa structures (106).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang by introducing the block structure of the second chip as disclosed in Pendse to achieve the predictable outcome of improving the density of chips in the device thus leading to a better performing device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Liao et al, US 20220308284 A1 (Liao) in further view of Huang et al, CN 112466868 A (Huang) in further view of Miyaji et al, JP 2016100252 A (Miyaji).
Regarding 18; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang teaches all the limitations of claim 12
However, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang does not teach wherein control of the columnar structures in one of the blocks is independent of control of the columnar structures in another one of the blocks.
Miyaji teaches wherein control of the columnar structures (Miyaji: Fig (2): A-H) in one of the blocks is independent of control (Claims section: Claim 1; “The plurality of light emitting diodes are divided into a plurality of control units that can be controlled to turn on / off independently”) of the columnar structures (A-H) in another one of the blocks.
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view Huang and Miyaji are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Miyaji by introducing the independent control mechanism of the columnar structures of the chips disclosed in Miyaji to improve the ability to control the various parts of the device.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Liao et al, US 20220308284 A1 (Liao) in further view of Huang et al, CN 112466868 A (Huang) in further view of Chen et al, US 20200020739 A1 (Chen)
Regarding claim 14; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang teaches all the limitations of claim 13.
However, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang does not teach wherein a first distance is a shortest distance between the columnar structures of two neighboring ones of the blocks of the first chip, the groove of the second chip has a first width, and the first distance is greater than the first width.
Chen teaches wherein a first distance (Chen: Annotated Fig (13) shared in this OA: First Distance) is a shortest distance between columnar structures (901) of two neighboring ones of the blocks of the first chip (20a), the groove (Groove) of the second chip (20b) has a first width, and the first distance (First Distance) is greater than the first width (First Width).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang and Chen are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang by introducing the distance between the blocks in the block structure of the chip as disclosed in Chen to achieve the predictable result of increasing the density of the devices on the chip thus leading to a better performing device.
PNG
media_image5.png
734
1060
media_image5.png
Greyscale
Regarding claim 15; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang in view of Chen teaches all the limitations of claim 14.
Further, Lim teaches wherein the first chip (Lim: Annotated Fig (5) shared in this OA: 120) comprises a third surface (Third Surface) and a fourth surface (Fourth Surface), the third surface (Third Surface) faces the first surface (First Surface), the fourth surface (Fourth Surface) faces away the first surface (First Surface), and the third surface (Third Surface) and the fourth surface (Fourth Surface) are opposite surfaces of the first chip (120); the second chip (220) comprises a fifth surface (Fifth Surface) and a sixth surface (Sixth Surface), the fifth surface (Fifth Surface) faces the fourth surface (Fourth Surface), the sixth surface (Sixth Surface) faces away the fourth surface (Fourth Surface), and the fifth surface (Fifth Surface) and the sixth surface (Sixth Surface) are opposite surfaces of the second chip (220); the fourth surface is the active surface of the first chip, and the fifth surface is the active surface of the second chip; wherein the chip package structure further comprises: a first conduction structure (121) and a second conduction structure (121), wherein the first conduction structure (121) is on the third surface (Third Surface) of the first chip (120) and connected to one of the first electrical conduction posts (122), and the second conduction structure (121) is on the third surface (Third Surface) of the first chip (120) and connected to another one of the first electrical conduction posts (122), so that the first chip (120) is electrically connected to the first electrical conduction posts (122); and a first conductive connection structure (221) and a second conductive connection structure (221), wherein the first conductive connection structure (221) is on the sixth surface (Sixth Surface) and connected to one of the second electrical conduction posts (213) through a wire (222), and the second conductive connection structure (221) is on the sixth surface (Sixth Surface) and connected to another one of the second electrical conduction posts (213) through another wire (222), so that the second chip (220) is electrically connected to the second electrical conduction posts (213).
Lim teaches the different surfaces of the chips and the connections between the chips and various electrically conductive paths in the package but fails to disclose any details of the active surfaces of the chips. Thus, Lim fails to disclose the fourth surface is the active surface of the first chip, and the fifth surface is the active surface of the second chip.
Lee teaches the fourth surface is the active surface of the first chip (Lee: Annotated Fig (4) shared in this OA: 12; [0048]-[0049]), and the fifth surface is the active surface of the second chip (14; [0048]-[0049]).
Lim and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of this application, to a person having ordinary skill in the art, to modify Lim by introducing the active areas of the devices facing each other as disclosed in Lee to achieve the predictable result of improving the accuracy of the detection of the optical signal thus leading to a better performing device.
Regarding claim 16; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Liao in further view of Huang in further view of Chen teaches all the limitations of claim 14.
Further, Lim teaches wherein the first chip (Lim: Annotated Fig (5) shared in this OA: 120) comprises a third surface (Third Surface) and a fourth surface (Fourth Surface), the third surface (Third Surface) faces the first surface (First Surface), the fourth surface (Fourth Surface) faces away the first surface (First Surface), and the third surface (Third Surface) and the fourth surface (Fourth Surface) are opposite surfaces of the first chip (120); the second chip (220) comprises a fifth surface (Fifth Surface) and a sixth surface (Sixth Surface), the fifth surface (Fifth Surface) faces the fourth surface (Fourth Surface), the sixth surface (Sixth Surface) faces away the fourth surface (Fourth Surface), and the fifth surface (Fifth Surface) and the sixth surface (Sixth Surface) are opposite surfaces of the second chip (220); the fourth surface is the active surface of the first chip, and the fifth surface is the active surface of the second chip; wherein the chip package structure further comprises: a first conduction structure (121) and a second conduction structure (122), wherein the first conduction structure (121) is on the third surface of the first chip (120) and the second conduction structure(121) is on the fourth surface of the first chip (120), the first conduction structure (121) is connected to at least one of the first electrical conduction posts (122), and the second conduction structure (121) is connected to at least another one of the first electrical conduction posts (122) through a first wire, so that the first chip is electrically connected to the substrate (110); and a first conductive connection structure (221) and a second conductive connection structure (221), wherein the first conductive connection structure (221) is on the sixth surface (Sixth Surface) and connected to one of the second electrical conduction posts (213) through a second wire (222), and the second conductive connection structure (221) is on the sixth surface (Sixth Surface) and connected to another one of the second electrical conduction posts (213) through another second wire (222), so that the second chip (220) is electrically connected to the substrate (110).
Lim teaches the different surfaces of the chips and the connections between the chips and various electrically conductive paths in the package but fails to disclose any details of the active surfaces of the chips. Thus, Lim fails to disclose the fourth surface is the active surface of the first chip, and the fifth surface is the active surface of the second chip.
Lee teaches the fourth surface is the active surface of the first chip (Lee: Annotated Fig (4) shared in this OA: 12; [0048]-[0049]), and the fifth surface is the active surface of the second chip (14; [0048]-[0049]).
Lim and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of this application, to a person having ordinary skill in the art, to modify Lim by introducing the active areas of the devices facing each other as disclosed in Lee to achieve the predictable result of improving the accuracy of the detection of the optical signal thus leading to a better performing device.
Lim teaches the details of the structure of connections in the package but fails to teach the first chip being connected to the substrate through a wire. Thus, Lim fails to teach the second conduction structure is connected to at least another one of the first electrical conduction posts through a first wire, so that the first chip is electrically connected to the substrate.
Given that Lim has used this technique of connecting the first chip to a substrate using a wire, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim by using a wire to connect the first chip to the substrate as disclosed in Lim for the second chip to make the chip connections easier and thus streamlining the device production process for higher and more efficient device production.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Chiba et al, WO 2021079862 A1 (Chiba) in further view of Beyer et al, US 20190044362 A1 (Beyer).
Regarding claim 20; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 teaches all the limitations of claim 1.
However, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 does not teach an automated external defibrillator comprising: a power module adapted to provide a constant-voltage input current; a high-voltage power module comprising the chip package structure according to claim 1 and adapted to receive the constant-voltage input current and output a high-voltage current; and an electrode pad module coupled to the high-voltage power module and adapted to output a high voltage so as to deliver a defibrillation shock.
Chiba teaches an automated external defibrillator comprising: a power module (Chiba: Fig (2): 19) adapted to provide a constant-voltage input current; a high-voltage power module (16) comprising the chip package structure according to claim 1 and adapted to receive the constant-voltage input current and output a high-voltage current; and an electrode pad module (Fig (3): 3A; 3B) coupled to the high-voltage power module (19) and adapted to output a high voltage so as to deliver a defibrillation shock (Abstract).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 and Chiba are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 to utilize the power module and electrode pad module in combination with the chip package as disclosed in Chiba to construct an efficient and reliable defibrillator.
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Chiba teaches the details of the components of the defibrillator system however, it fails to disclose the characteristics of the input voltage and output currents of the device. Thus, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Chiba fails to disclose adapted to receive constant-voltage input current and output a high-voltage current.
Beyer teaches to receive constant-voltage current and output a high-voltage current (Bayer: [0141]).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Chiba and Beyer are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 in further view of Chiba by introducing the high-voltage current converter disclosed in Beyer to improve the performance of the device.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Su et al, DE 102016015805 B3 (Su ‘805) in further view of Su, CN 102736189 A (Su ‘189) in further view of Ostrowski, US 20080076993 A1 (Ostrowski).
Regarding claim 23; Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 teaches all the limitations of the chip package structure according to claim 1.
However, Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 does not teach wherein a distance between the active surface of the first chip and the active surface of the second chip is in a range from 1 μm to 30 μm.
Ostrowski teaches wherein a distance between the active surface of the first chip (Ostrowski: Fig (5): 12) and the active surface of the second chip (14) is in a range from 1 μm to 30 μm ([0012]).
Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 and Ostrowski are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Su ‘805 in further view of Su ‘189 by making the distance between the transmitter and the receiver in the range disclosed in Ostrowski to lower the losses of the signal during detection and thus improve the efficiency of the device.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Huang et al, CN 112466868 A (Huang) in further view of Pendse, US 20210013099 A1 (Pendse).
Regarding claim 25; Lim teaches a chip package structure (Lim: Annotated Fig (5) shared in this OA: 300) comprising:
a substrate (110) comprising a first surface (First Surface) and a second surface (Second Surface) being opposite surfaces of the substrate (110); and
a chip set (120; 220) disposed in a chip region on the first surface (First Surface) and electrically connected to the substrate (110), wherein the chip set (120; 220) comprises a first chip (120) and a second chip (220), and
an active surface of the second chip faces an active surface of the first chip,
wherein the first chip comprises a plurality of blocks which are arranged orderly, the second chip comprises a plurality of mesa structures which are arranged orderly, and each of the mesa structures (220) of the second chip (220) is aligned with a corresponding one of the blocks of the first chip (110).
Lim does not teach an active surface of the second chip faces an active surface of the first chip.
Lee teaches an active surface of the second chip (Lee: Annotated Fig (4) shared in this OA:14) faces an active surface of the first chip (12; [0048]-[0049])
Lim and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim by introducing the active areas of the devices facing each other as disclosed in Lee to achieve the predictable result of improving the accuracy of the detection of the optical signal.
Lim in view of Lee does not teach wherein the first chip comprises a plurality of blocks which are arranged orderly.
Huang teaches wherein the first chip comprises a plurality of blocks (Huang: Fig (1): 011; 012) which are arranged orderly (see Fig (1)).
Lim in view of and Huang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee by using the first chip comprised of a plurality of blocks arranged orderly as disclosed in Huang to save space in the chip package and to simplify the electrical connections between different block components of the chips making the device production more efficient.
Lim in view of Lee in further view of Huang disclose the structure of the first chip but fails to disclose the structure of the second chip. Thus, Lim in view of Lee in further view of Huang fails to disclose the second chip comprises a plurality of mesa structures which are arranged orderly.
Pendse teaches the second chip (Pendse: Fig (2B): 202a; 202b; 202c) comprises a plurality of mesa structures (106) which are arranged orderly (see Fig (2B)).
Lim in view of Lee in further view of Huang and Pendse are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Huang by constructing the second chip in the manner disclosed in Pendse with a plurality of mesa structures arranged orderly to improve the organization of the different components on the chip and thus increase the number of components that can be placed on the chip leading to a higher performing device.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Huang et al, CN 112466868 A (Huang) in further view of Pendse, US 20210013099 A1 (Pendse) in further view of Jacobs, US 20170224585 A1 (Jacobs).
Regarding claim 26; Lim in view of Lee in further view of Huang in further view of Pendse teach all the limitations of the chip package structure according to claim 25
Lim in view of Lee in further view of Huang in further view of Pendse does not teach wherein the mesa structures of the second chip are connected in series.
Jacobs teaches wherein the mesa structures (Jacobs: Fig (3A): 305) of the second chip (Fig (5A): 505) are connected in series ([0035]).
Lim in view of Lee in further view of Huang in further view of Pendse and Jacobs are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Huang in further view of Pendse by connecting the mesa structures of the second chip in series as disclosed in Jacobs to limit the possible current surges in the device and thus improve the longevity and durability of the device.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al, US 20210035961 A1 (Lim) in view of Lee et al, US 20060208165 A1 (Lee) in further view of Huang et al, CN 112466868 A (Huang) in further view of Pendse, US 20210013099 A1 (Pendse) in further view of Hollman et al, US 20190361098 A1 (Hollmann).
Regarding claim 27; Lim in view of Lee in further view of Huang in further view of Pendse teach all the limitations of the chip package structure according to claim 25
Lim in view of Lee in further view of Huang in further view of Pendse does not teach wherein the mesa structures of the second chip are connected in parallel.
Hollmann teaches wherein the mesa structures (Hollmann: Fig (2B): 205) of the second chip (204) are connected in parallel ([0017]).
Lim in view of Lee in further view of Huang in further view of Pendse and Hollmann are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lim in view of Lee in further view of Huang in further view of Pendse by connecting the mesa structures of the second chip in parallel as disclosed in Hollmann to increase the detection ability of the device and thus improve the sensitivity of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
April 27, 2026
Prosecution Insights